From patchwork Wed Mar 6 07:38:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 138005 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DB1E443C56; Wed, 6 Mar 2024 08:39:29 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A6C0F4027C; Wed, 6 Mar 2024 08:39:29 +0100 (CET) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2076.outbound.protection.outlook.com [40.107.94.76]) by mails.dpdk.org (Postfix) with ESMTP id 8E03740156 for ; Wed, 6 Mar 2024 08:39:27 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ImL0tzC8W2seylXZpbvWc2hy4Cxl9EMtHSP/co+7o7LEMlniVZfW/ZLCtApiQszarZzmIv9Xc/zyiCdAK7X/UWCXQV7imT4sUFtENlNsiqtPvIaFrd8i0jSI1vd7+5tqCRr6BdWELeI0UN/DpKaD+LMs4KinBmxjYRurHTyG+vsSHLOZIMYJe/xb1EO6QR8qo80pvkhchsjeTBbmSdayRFUl6asrx3mIokUrZCPYQ+095IF1ko3FEV1TnsDIoI5nXVy7b9q3j1D35LXCqyD+/jtAVbWAdtc7LRIzzsplN1/XgVA3PXEVjXJVz43Uc1+4ljff/RqaN2hAX08mUjQWyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/+Lq5lJfuEHHzBK9ajUYj6PZcnUQNsx5hRo0i2W+1t8=; b=X1OOxVDj4ysE9y4NjCJ/wJOHGhH1Zqome82joc7neWKlYuAkrOOH4F2NIxOK2cqZup7DTI+oQlKuI+Z52J774whiYjNnPzmN9KyahL+BND2r9nQ7PLLsiQsLyZNJrxs+K6ZO9DISULtv+cUInqHjlXqr2ltap/ZsTF3Nhh2G8NC+GQbIXHKw1gLfZDrk3/L7B2hCDhwksovZRJFwjQHQpmelgMo8Os2v8f5vXMoIY4/MMmNLGTDEMDHwW9obcnOVbcKQ6/UgKw513PWLBowU7H8vaym3787+eiV9v4WAmpohI3tEki7aQF6g1hengz5kqWXv3os/tuzGeIZzoQkk3g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/+Lq5lJfuEHHzBK9ajUYj6PZcnUQNsx5hRo0i2W+1t8=; b=fw263W2K/lScTiha8dR+99ce+0OkwN92GKBqgnPRsFw6/Lh28szSNspterLnsWtOJ9AAk8oBCWbfW5N7hfm/vVjnUJnCjMpDi7ixI8rEOPA3mxNwJYJjaC7SDQBX7YFanGBtQZ2NCzxM0LE5seRAktyP85VVlipO04P0mGemQ6q7jvB13BcWzwQL+doWxo7BiKxKz31tAQT5kia0dfLajW+7EeIZ0T2eQ/tXdpKJ+Ly28CDI+wWIMqOBEiiWdBAvXMJfzod3t+nVnOb4xexv98g2oMs1nACuWo1AORDqfd/14NPdmE8kQB0EuiOJV0uCeNdgaLJftdv6NyeJq+dspw== Received: from DM6PR11CA0036.namprd11.prod.outlook.com (2603:10b6:5:190::49) by IA1PR12MB8555.namprd12.prod.outlook.com (2603:10b6:208:44f::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7362.24; Wed, 6 Mar 2024 07:39:24 +0000 Received: from DS1PEPF0001709C.namprd05.prod.outlook.com (2603:10b6:5:190:cafe::7e) by DM6PR11CA0036.outlook.office365.com (2603:10b6:5:190::49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7362.24 via Frontend Transport; Wed, 6 Mar 2024 07:39:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS1PEPF0001709C.mail.protection.outlook.com (10.167.18.106) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7362.11 via Frontend Transport; Wed, 6 Mar 2024 07:39:24 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 5 Mar 2024 23:39:13 -0800 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 5 Mar 2024 23:39:09 -0800 From: Gregory Etelson To: CC: , , , Dariusz Sosnowski , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Matan Azrad Subject: [PATCH] net/mlx5: fix pattern template size validation Date: Wed, 6 Mar 2024 09:38:56 +0200 Message-ID: <20240306073856.950136-1-getelson@nvidia.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709C:EE_|IA1PR12MB8555:EE_ X-MS-Office365-Filtering-Correlation-Id: e7d2111d-db33-439d-1f78-08dc3db08bc3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 04nDphL94bjK8qs4i2S8p1TsPxDAFAZHIA8PYItJOGoOAynGF36ziTnnsF47yk5TOYcancBdg79+wI4bcMDbY3AlZU6jj0tVC6vMVdpOtbcWCq3eGxp2fDksYJgonLtJoMFkuGh9lrSOK3UsCK6uAwuLadNBpyzBcYq8cn0smyPyYuRKONKqlC+Op3Y8chZI+cpWhjvOB5Tm4IW2MmeVT+ikNgzjmmy2wrOKsA+WmqpwIqK25OQqUx2W2PyFH4nOG+Lsb2dFfHnPgMSuMFk94h/YfE+4i6coihB5rPte4KZSYT/xrZawk38yI0kGTskcryBgdl7NTcGE2irohfzKagp7mKHEmmAkvlmD398D/F26RcfVsoGci6C4OvEW3fXgBPbHAF8jM7BfMhQU0hksI1P80nSqJtJ4T6PzeChiWedynI/SSlW+pqFoJHGUEQKTmnPYVxtny9lZF6NHXnnQD8/Nike1yeKNH0UgoJpRRYAyuRCsgKs966SZElLCM1ZkgsQUB9rx1AAFxz4rWA1t/jtliaRLJRJ8XUTt5plua/1c7oPUiFNIic5mni6oZrw7RCYT3F3Qjjrv7h3HAJmNwUnpdyb63tHK6eotuXzSmMifGfEp3i6vDUlEqH8tO4uPOjXz647O56Fo6nAODOd0vNkIfUIZeCe7e+Qp/KfVvdp5cJR1Qonvl/Vgo73MqrMHpiKPFten7SGrfhnM/cU+woKTEXw6o+KzLhxc9QORIcY5x3ENm+8ndqpE6E29eTFg X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(82310400014)(36860700004)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2024 07:39:24.6720 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7d2111d-db33-439d-1f78-08dc3db08bc3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8555 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org PMD running in HWS FDB mode can be configured to steer group 0 to FW. In that case PMD activates legacy DV pattern processing. There are control flows that require HWS pattern processing in group 0. Pattern template validation tried to create a matcher both in group 0 and HWS group. As the result, during group 0 validation HWS tuned pattern was processed as DV. The patch removed pattern validation for group 0. Fixes: f3aadd103358 ("net/mlx5: improve pattern template validation") Signed-off-by: Gregory Etelson Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow_hw.c | 49 +++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 4216433c6e..b37348c972 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -7668,48 +7668,57 @@ flow_hw_pattern_has_sq_match(const struct rte_flow_item *items) return false; } +/* + * Verify that the tested flow patterns fits STE size limit in HWS group. + * + * + * Return values: + * 0 : Tested patterns fit STE size limit + * -EINVAL : Invalid parameters detected + * -E2BIG : Tested patterns exceed STE size limit + */ static int pattern_template_validate(struct rte_eth_dev *dev, struct rte_flow_pattern_template *pt[], uint32_t pt_num) { - uint32_t group = 0; + struct rte_flow_error error; struct mlx5_flow_template_table_cfg tbl_cfg = { - .attr = (struct rte_flow_template_table_attr) { + .attr = { .nb_flows = 64, .insertion_type = RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN, .hash_func = RTE_FLOW_TABLE_HASH_FUNC_DEFAULT, .flow_attr = { + .group = 1, .ingress = pt[0]->attr.ingress, .egress = pt[0]->attr.egress, .transfer = pt[0]->attr.transfer } - }, - .external = true + } }; struct mlx5_priv *priv = dev->data->dev_private; struct rte_flow_actions_template *action_template; + struct rte_flow_template_table *tmpl_tbl; + int ret; - if (pt[0]->attr.ingress) { + if (pt[0]->attr.ingress) action_template = priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_RX]; - } else if (pt[0]->attr.egress) { + else if (pt[0]->attr.egress) action_template = priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_TX]; - } else if (pt[0]->attr.transfer) { + else if (pt[0]->attr.transfer) action_template = priv->action_template_drop[MLX5DR_TABLE_TYPE_FDB]; + else + return -EINVAL; + if (pt[0]->item_flags & MLX5_FLOW_ITEM_COMPARE) + tbl_cfg.attr.nb_flows = 1; + tmpl_tbl = flow_hw_table_create(dev, &tbl_cfg, pt, pt_num, + &action_template, 1, NULL); + if (tmpl_tbl) { + ret = 0; + flow_hw_table_destroy(dev, tmpl_tbl, &error); } else { - rte_errno = EINVAL; - return rte_errno; + ret = rte_errno == E2BIG ? -E2BIG : 0; } - do { - struct rte_flow_template_table *tmpl_tbl; - - tbl_cfg.attr.flow_attr.group = group; - tmpl_tbl = flow_hw_table_create(dev, &tbl_cfg, pt, pt_num, - &action_template, 1, NULL); - if (!tmpl_tbl) - return rte_errno; - flow_hw_table_destroy(dev, tmpl_tbl, NULL); - } while (++group <= 1); - return 0; + return ret; } /**