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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CH1PEPF0000AD7E.mail.protection.outlook.com (10.167.244.87) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7362.11 via Frontend Transport; Wed, 6 Mar 2024 20:23:15 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 6 Mar 2024 12:22:58 -0800 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Wed, 6 Mar 2024 12:22:56 -0800 From: Dariusz Sosnowski To: Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Matan Azrad CC: , Subject: [PATCH 4/4] net/mlx5: fix flow configure validation Date: Wed, 6 Mar 2024 21:21:50 +0100 Message-ID: <20240306202150.79577-4-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240306202150.79577-1-dsosnowski@nvidia.com> References: <20240306202150.79577-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7E:EE_|DS0PR12MB7925:EE_ X-MS-Office365-Filtering-Correlation-Id: 478b7541-2774-406b-618b-08dc3e1b4145 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2024 20:23:15.8310 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 478b7541-2774-406b-618b-08dc3e1b4145 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7925 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org There's an existing limitation in mlx5 PMD, that all configured flow queues must have the same size. Even though this condition is checked, some allocations are done before that. This lead to segmentation fault during rollback on error in rte_flow_configure() implementation. This patch fixes that by reorganizing validation, so that configuration options are validated before any allocations are done and necessary checks for NULL are added to error rollback. Bugzilla ID: 1199 Fixes: b401400db24e ("net/mlx5: add port flow configuration") Cc: stable@dpdk.org Signed-off-by: Dariusz Sosnowski Acked-by: Suanming Mou --- drivers/net/mlx5/mlx5_flow_hw.c | 62 +++++++++++++++++++++++---------- 1 file changed, 43 insertions(+), 19 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 17ab3a98fe..407a843578 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -10253,6 +10253,38 @@ mlx5_hwq_ring_create(uint16_t port_id, uint32_t queue, uint32_t size, const char RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ); } +static int +flow_hw_validate_attributes(const struct rte_flow_port_attr *port_attr, + uint16_t nb_queue, + const struct rte_flow_queue_attr *queue_attr[], + struct rte_flow_error *error) +{ + uint32_t size; + unsigned int i; + + if (port_attr == NULL) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "Port attributes must be non-NULL"); + + if (nb_queue == 0) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "At least one flow queue is required"); + + if (queue_attr == NULL) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "Queue attributes must be non-NULL"); + + size = queue_attr[0]->size; + for (i = 1; i < nb_queue; ++i) { + if (queue_attr[i]->size != size) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "All flow queues must have the same size"); + } + + return 0; +} + /** * Configure port HWS resources. * @@ -10304,10 +10336,8 @@ flow_hw_configure(struct rte_eth_dev *dev, int ret = 0; uint32_t action_flags; - if (!port_attr || !nb_queue || !queue_attr) { - rte_errno = EINVAL; - goto err; - } + if (flow_hw_validate_attributes(port_attr, nb_queue, queue_attr, error)) + return -rte_errno; /* * Calling rte_flow_configure() again is allowed if and only if * provided configuration matches the initially provided one. @@ -10354,14 +10384,6 @@ flow_hw_configure(struct rte_eth_dev *dev, /* Allocate the queue job descriptor LIFO. */ mem_size = sizeof(priv->hw_q[0]) * nb_q_updated; for (i = 0; i < nb_q_updated; i++) { - /* - * Check if the queues' size are all the same as the - * limitation from HWS layer. - */ - if (_queue_attr[i]->size != _queue_attr[0]->size) { - rte_errno = EINVAL; - goto err; - } mem_size += (sizeof(struct mlx5_hw_q_job *) + sizeof(struct mlx5_hw_q_job)) * _queue_attr[i]->size; } @@ -10643,14 +10665,16 @@ flow_hw_configure(struct rte_eth_dev *dev, __atomic_fetch_sub(&host_priv->shared_refcnt, 1, __ATOMIC_RELAXED); priv->shared_host = NULL; } - for (i = 0; i < nb_q_updated; i++) { - rte_ring_free(priv->hw_q[i].indir_iq); - rte_ring_free(priv->hw_q[i].indir_cq); - rte_ring_free(priv->hw_q[i].flow_transfer_pending); - rte_ring_free(priv->hw_q[i].flow_transfer_completed); + if (priv->hw_q) { + for (i = 0; i < nb_q_updated; i++) { + rte_ring_free(priv->hw_q[i].indir_iq); + rte_ring_free(priv->hw_q[i].indir_cq); + rte_ring_free(priv->hw_q[i].flow_transfer_pending); + rte_ring_free(priv->hw_q[i].flow_transfer_completed); + } + mlx5_free(priv->hw_q); + priv->hw_q = NULL; } - mlx5_free(priv->hw_q); - priv->hw_q = NULL; if (priv->acts_ipool) { mlx5_ipool_destroy(priv->acts_ipool); priv->acts_ipool = NULL;