diff mbox series

[v4,07/21] common/idpf: compress RXDID mask definitions

Message ID 20240618105722.2326987-8-soumyadeep.hore@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Bruce Richardson
Headers
Series Update MEV TS Base Driver |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Soumyadeep Hore June 18, 2024, 10:57 a.m. UTC 
Instead of using the long RXDID definitions, introduce a
macro which uses common part of the RXDID definitions i.e.
VIRTCHNL2_RXDID_ and the bit passed to generate a mask.

Signed-off-by: Soumyadeep Hore <soumyadeep.hore@intel.com>
---
 drivers/common/idpf/base/virtchnl2_lan_desc.h | 31 ++++++++++---------
 1 file changed, 16 insertions(+), 15 deletions(-)
diff mbox series

Patch

diff --git a/drivers/common/idpf/base/virtchnl2_lan_desc.h b/drivers/common/idpf/base/virtchnl2_lan_desc.h
index e6e782a219..f632271788 100644
--- a/drivers/common/idpf/base/virtchnl2_lan_desc.h
+++ b/drivers/common/idpf/base/virtchnl2_lan_desc.h
@@ -58,22 +58,23 @@ 
 /* VIRTCHNL2_RX_DESC_ID_BITMASKS
  * Receive descriptor ID bitmasks
  */
-#define VIRTCHNL2_RXDID_0_16B_BASE_M		BIT(VIRTCHNL2_RXDID_0_16B_BASE)
-#define VIRTCHNL2_RXDID_1_32B_BASE_M		BIT(VIRTCHNL2_RXDID_1_32B_BASE)
-#define VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M		BIT(VIRTCHNL2_RXDID_2_FLEX_SPLITQ)
-#define VIRTCHNL2_RXDID_2_FLEX_SQ_NIC_M		BIT(VIRTCHNL2_RXDID_2_FLEX_SQ_NIC)
-#define VIRTCHNL2_RXDID_3_FLEX_SQ_SW_M		BIT(VIRTCHNL2_RXDID_3_FLEX_SQ_SW)
-#define VIRTCHNL2_RXDID_4_FLEX_SQ_NIC_VEB_M	BIT(VIRTCHNL2_RXDID_4_FLEX_SQ_NIC_VEB)
-#define VIRTCHNL2_RXDID_5_FLEX_SQ_NIC_ACL_M	BIT(VIRTCHNL2_RXDID_5_FLEX_SQ_NIC_ACL)
-#define VIRTCHNL2_RXDID_6_FLEX_SQ_NIC_2_M	BIT(VIRTCHNL2_RXDID_6_FLEX_SQ_NIC_2)
-#define VIRTCHNL2_RXDID_7_HW_RSVD_M		BIT(VIRTCHNL2_RXDID_7_HW_RSVD)
+#define VIRTCHNL2_RXDID_M(bit)			BIT(VIRTCHNL2_RXDID_##bit)
+#define VIRTCHNL2_RXDID_0_16B_BASE_M		VIRTCHNL2_RXDID_M(0_16B_BASE)
+#define VIRTCHNL2_RXDID_1_32B_BASE_M		VIRTCHNL2_RXDID_M(1_32B_BASE)
+#define VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M		VIRTCHNL2_RXDID_M(2_FLEX_SPLITQ)
+#define VIRTCHNL2_RXDID_2_FLEX_SQ_NIC_M		VIRTCHNL2_RXDID_M(2_FLEX_SQ_NIC)
+#define VIRTCHNL2_RXDID_3_FLEX_SQ_SW_M		VIRTCHNL2_RXDID_M(3_FLEX_SQ_SW)
+#define VIRTCHNL2_RXDID_4_FLEX_SQ_NIC_VEB_M	VIRTCHNL2_RXDID_M(4_FLEX_SQ_NIC_VEB)
+#define VIRTCHNL2_RXDID_5_FLEX_SQ_NIC_ACL_M	VIRTCHNL2_RXDID_M(5_FLEX_SQ_NIC_ACL)
+#define VIRTCHNL2_RXDID_6_FLEX_SQ_NIC_2_M	VIRTCHNL2_RXDID_M(6_FLEX_SQ_NIC_2)
+#define VIRTCHNL2_RXDID_7_HW_RSVD_M		VIRTCHNL2_RXDID_M(7_HW_RSVD)
 /* 9 through 15 are reserved */
-#define VIRTCHNL2_RXDID_16_COMMS_GENERIC_M	BIT(VIRTCHNL2_RXDID_16_COMMS_GENERIC)
-#define VIRTCHNL2_RXDID_17_COMMS_AUX_VLAN_M	BIT(VIRTCHNL2_RXDID_17_COMMS_AUX_VLAN)
-#define VIRTCHNL2_RXDID_18_COMMS_AUX_IPV4_M	BIT(VIRTCHNL2_RXDID_18_COMMS_AUX_IPV4)
-#define VIRTCHNL2_RXDID_19_COMMS_AUX_IPV6_M	BIT(VIRTCHNL2_RXDID_19_COMMS_AUX_IPV6)
-#define VIRTCHNL2_RXDID_20_COMMS_AUX_FLOW_M	BIT(VIRTCHNL2_RXDID_20_COMMS_AUX_FLOW)
-#define VIRTCHNL2_RXDID_21_COMMS_AUX_TCP_M	BIT(VIRTCHNL2_RXDID_21_COMMS_AUX_TCP)
+#define VIRTCHNL2_RXDID_16_COMMS_GENERIC_M	VIRTCHNL2_RXDID_M(16_COMMS_GENERIC)
+#define VIRTCHNL2_RXDID_17_COMMS_AUX_VLAN_M	VIRTCHNL2_RXDID_M(17_COMMS_AUX_VLAN)
+#define VIRTCHNL2_RXDID_18_COMMS_AUX_IPV4_M	VIRTCHNL2_RXDID_M(18_COMMS_AUX_IPV4)
+#define VIRTCHNL2_RXDID_19_COMMS_AUX_IPV6_M	VIRTCHNL2_RXDID_M(19_COMMS_AUX_IPV6)
+#define VIRTCHNL2_RXDID_20_COMMS_AUX_FLOW_M	VIRTCHNL2_RXDID_M(20_COMMS_AUX_FLOW)
+#define VIRTCHNL2_RXDID_21_COMMS_AUX_TCP_M	VIRTCHNL2_RXDID_M(21_COMMS_AUX_TCP)
 /* 22 through 63 are reserved */
 
 /* Rx */