diff mbox series

dma/idxd: set defaults for GRPCFG traffic class

Message ID 20240626054523.3042796-1-shaiq.wani@intel.com (mailing list archive)
State Accepted, archived
Delegated to: David Marchand
Headers
Series dma/idxd: set defaults for GRPCFG traffic class |

Checks

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ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/Intel-compilation success Compilation OK
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ci/github-robot: build success github build: passed
ci/intel-Functional success Functional PASS
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ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-abi-testing success Testing PASS
ci/iol-compile-amd64-testing success Testing PASS
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Commit Message

Shaiq Wani June 26, 2024, 5:45 a.m. UTC 
Set GRPCFG traffic class to value of 1 for best performance on current
generation of accelerators. Applicable to gen1 and gen2 devices.

Signed-off-by: Shaiq Wani <shaiq.wani@intel.com>
---
 drivers/dma/idxd/idxd_pci.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Bruce Richardson Oct. 4, 2024, 4:49 p.m. UTC | #1 
On Wed, Jun 26, 2024 at 05:45:23AM +0000, Shaiq Wani wrote:
> Set GRPCFG traffic class to value of 1 for best performance on current
> generation of accelerators. Applicable to gen1 and gen2 devices.
> 
> Signed-off-by: Shaiq Wani <shaiq.wani@intel.com>
> ---
>  drivers/dma/idxd/idxd_pci.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
David Marchand Oct. 18, 2024, 4:46 p.m. UTC | #2 
On Fri, Oct 4, 2024 at 6:49 PM Bruce Richardson
<bruce.richardson@intel.com> wrote:
>
> On Wed, Jun 26, 2024 at 05:45:23AM +0000, Shaiq Wani wrote:
> > Set GRPCFG traffic class to value of 1 for best performance on current
> > generation of accelerators. Applicable to gen1 and gen2 devices.
> >
> > Signed-off-by: Shaiq Wani <shaiq.wani@intel.com>
> Acked-by: Bruce Richardson <bruce.richardson@intel.com>

Applied, thanks.
diff mbox series

Patch

diff --git a/drivers/dma/idxd/idxd_pci.c b/drivers/dma/idxd/idxd_pci.c
index 81637d9420..e551b2232d 100644
--- a/drivers/dma/idxd/idxd_pci.c
+++ b/drivers/dma/idxd/idxd_pci.c
@@ -12,6 +12,14 @@ 
 #define IDXD_VENDOR_ID		0x8086
 #define IDXD_DEVICE_ID_SPR	0x0B25
 
+#define DEVICE_VERSION_1	0x100
+#define DEVICE_VERSION_2	0x200
+/*
+ * Set bits for Traffic Class A & B
+ * TC-A (Bits 2:0) and TC-B (Bits 5:3)
+ */
+#define IDXD_SET_TC_A_B		0x9
+
 #define IDXD_PMD_DMADEV_NAME_PCI dmadev_idxd_pci
 
 const struct rte_pci_id pci_id_idxd_map[] = {
@@ -177,6 +185,7 @@  init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd,
 	uint16_t grp_offset, wq_offset; /* how far into bar0 the regs are */
 	uint16_t wq_size, total_wq_size;
 	uint8_t lg2_max_batch, lg2_max_copy_size;
+	uint32_t version;
 	unsigned int i, err_code;
 
 	pci = rte_malloc(NULL, sizeof(*pci), 0);
@@ -190,6 +199,7 @@  init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd,
 
 	/* assign the bar registers, and then configure device */
 	pci->regs = dev->mem_resource[0].addr;
+	version = pci->regs->version;
 	grp_offset = (uint16_t)pci->regs->offsets[0];
 	pci->grp_regs = RTE_PTR_ADD(pci->regs, grp_offset * 0x100);
 	wq_offset = (uint16_t)(pci->regs->offsets[0] >> 16);
@@ -234,6 +244,8 @@  init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd,
 	for (i = 0; i < nb_groups; i++) {
 		pci->grp_regs[i].grpengcfg = 0;
 		pci->grp_regs[i].grpwqcfg[0] = 0;
+		if (version <= DEVICE_VERSION_2)
+			pci->grp_regs[i].grpflags |= IDXD_SET_TC_A_B;
 	}
 	for (i = 0; i < nb_wqs; i++)
 		idxd_get_wq_cfg(pci, i)[0] = 0;
@@ -278,6 +290,7 @@  init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd,
 				(lg2_max_batch << WQ_BATCH_SZ_SHIFT);
 	}
 
+	IDXD_PMD_DEBUG("    Device Version: %"PRIx32, version);
 	/* dump the group configuration to output */
 	for (i = 0; i < nb_groups; i++) {
 		IDXD_PMD_DEBUG("## Group %d", i);