diff mbox series

[v2,17/30] dma/dpaa: qdma stall workaround for ERR050265

Message ID 20240722115843.1830105-18-g.singh@nxp.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series NXP DMA driver fixes and Enhancements |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Gagandeep Singh July 22, 2024, 11:58 a.m. UTC 
Non-prefetchable read setting in the source descriptor may be
required for targets other than local memory. Prefetchable read
setting will offer better performance for misaligned transfers
in the form of fewer transactions and should be set if possible.
This patch also fixes QDMA stall issue due to unaligned
transactions.

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
---
 config/arm/meson.build       | 3 ++-
 doc/guides/dmadevs/dpaa.rst  | 1 +
 drivers/dma/dpaa/dpaa_qdma.c | 6 ++++++
 drivers/dma/dpaa/dpaa_qdma.h | 1 +
 4 files changed, 10 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/config/arm/meson.build b/config/arm/meson.build
index f81e466318..f63ef41130 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -469,7 +469,8 @@  soc_dpaa = {
         ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
         ['RTE_MAX_LCORE', 16],
         ['RTE_MAX_NUMA_NODES', 1],
-	['RTE_DMA_DPAA_ERRATA_ERR050757', true]
+	['RTE_DMA_DPAA_ERRATA_ERR050757', true],
+	['RTE_DMA_DPAA_ERRATA_ERR050265', true]
     ],
     'numa': false
 }
diff --git a/doc/guides/dmadevs/dpaa.rst b/doc/guides/dmadevs/dpaa.rst
index 746919ec6b..8a7c0befc3 100644
--- a/doc/guides/dmadevs/dpaa.rst
+++ b/doc/guides/dmadevs/dpaa.rst
@@ -43,6 +43,7 @@  For builds using ``meson`` and ``ninja``, the driver will be built when the
 target platform is dpaa-based. No additional compilation steps are necessary.
 
 - ``RTE_DMA_DPAA_ERRATA_ERR050757`` - enable software workaround for Errata-A050757
+- ``RTE_DMA_DPAA_ERRATA_ERR050265`` - enable software workaround for Errata-A050265
 
 Initialization
 --------------
diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c
index a21279293c..f1878879af 100644
--- a/drivers/dma/dpaa/dpaa_qdma.c
+++ b/drivers/dma/dpaa/dpaa_qdma.c
@@ -179,6 +179,9 @@  fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
 	sdf = (struct fsl_qdma_sdf *)fsl_comp->desc_virt_addr;
 	sdf->cmd = rte_cpu_to_le_32(FSL_QDMA_CMD_RWTTYPE <<
 				FSL_QDMA_CMD_RWTTYPE_OFFSET);
+#ifdef RTE_DMA_DPAA_ERRATA_ERR050265
+	sdf->cmd |= rte_cpu_to_le_32(FSL_QDMA_CMD_PF);
+#endif
 	if (len > FSL_QDMA_CMD_SSS_DISTANCE) {
 		sdf->cmd |= rte_cpu_to_le_32(FSL_QDMA_CMD_SSEN);
 		cfg |= rte_cpu_to_le_32(FSL_QDMA_CMD_SSS_STRIDE <<
@@ -247,6 +250,9 @@  fsl_qdma_pre_request_enqueue_comp_sd_desc(
 		/* Descriptor Buffer */
 		sdf->cmd = rte_cpu_to_le_32(FSL_QDMA_CMD_RWTTYPE <<
 			       FSL_QDMA_CMD_RWTTYPE_OFFSET);
+#ifdef RTE_DMA_DPAA_ERRATA_ERR050265
+		sdf->cmd |= rte_cpu_to_le_32(FSL_QDMA_CMD_PF);
+#endif
 		ddf->cmd = rte_cpu_to_le_32(FSL_QDMA_CMD_RWTTYPE <<
 			       FSL_QDMA_CMD_RWTTYPE_OFFSET);
 		ddf->cmd |= rte_cpu_to_le_32(FSL_QDMA_CMD_LWC <<
diff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h
index 361f88856b..8cb4042bd0 100644
--- a/drivers/dma/dpaa/dpaa_qdma.h
+++ b/drivers/dma/dpaa/dpaa_qdma.h
@@ -80,6 +80,7 @@ 
 
 #define FSL_QDMA_CMD_RWTTYPE_OFFSET	28
 #define FSL_QDMA_CMD_LWC_OFFSET		16
+#define FSL_QDMA_CMD_PF			BIT(17)
 
 #define FSL_QDMA_CMD_SSEN		BIT(19)
 #define FSL_QDMA_CFG_SSS_OFFSET		12