From patchwork Thu Sep 5 07:46:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 143627 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A240C45909; Thu, 5 Sep 2024 09:46:44 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D3E3C42DBD; Thu, 5 Sep 2024 09:46:42 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 338AA42DBB for ; Thu, 5 Sep 2024 09:46:41 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48547jkV013950 for ; Thu, 5 Sep 2024 00:46:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=C IDlCFwcqA67yASM4CT2OM7oABKzeSgUtVHsksffD8s=; b=hMJ+Ht/jcU+bEIQq1 6y7AybVYAtzQaNq3ry7U887bkck8a9kY4pJoETQ/Csk0P5xJmTXTJq+vAzGBLlQu UkOlkqdlkiIpej7lyNq1NnUjzhvkVWLH+sN1eH7VhDtJs3vJm/V3iBCw1VI5Rd3y jCCl3aCIiYgZkASZAE+g/R7zLsT+wup5wrbhT643wHUSBX9vUlhahvhPqzhIA3aI Ui/baMswUTgIuZZ4ZTofN/Lh9V6FtbruNAj8au03kM+CkYCDN3i0abaxOxDM/AzE qAK71kxnI+9u5i+m8SRmDSomwa6SonTWLvQOkDhecMPve7tsBLS1Xwnr5/12eR90 oXWUg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 41ev31tfn5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 05 Sep 2024 00:46:40 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 5 Sep 2024 00:46:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 5 Sep 2024 00:46:38 -0700 Received: from hyd1554.caveonetworks.com (unknown [10.29.56.32]) by maili.marvell.com (Postfix) with ESMTP id 4ED333F70A7; Thu, 5 Sep 2024 00:46:37 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Vidya Sagar Velumuri , Anoob Joseph , Subject: [PATCH 02/11] crypto/cnxk: add multi segment support for Rx inject Date: Thu, 5 Sep 2024 13:16:22 +0530 Message-ID: <20240905074631.1462357-3-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240905074631.1462357-1-ktejasree@marvell.com> References: <20240905074631.1462357-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Ph6oHZNV4plq2miHr2dKdiSULyTJ8eP0 X-Proofpoint-GUID: Ph6oHZNV4plq2miHr2dKdiSULyTJ8eP0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-05_04,2024-09-04_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Add support for multi segmented packet in Rx inject. Signed-off-by: Vidya Sagar Velumuri --- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 53 ++++++++++++++++++----- drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 9 +++- 2 files changed, 50 insertions(+), 12 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index 780785d656..64d015aba2 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -1366,8 +1366,8 @@ cn10k_cryptodev_sec_inb_rx_inject(void *dev, struct rte_mbuf **pkts, union cpt_fc_write_s fc; struct cnxk_cpt_vf *vf; struct rte_mbuf *m; + uint64_t u64_dptr; uint64_t *fc_addr; - uint64_t dptr; int i; vf = cdev->data->dev_private; @@ -1401,11 +1401,6 @@ cn10k_cryptodev_sec_inb_rx_inject(void *dev, struct rte_mbuf **pkts, break; } - if (unlikely(!rte_pktmbuf_is_contiguous(m))) { - plt_dp_err("Multi seg is not supported"); - break; - } - l2_len = m->l2_len; *rte_security_dynfield(m) = (uint64_t)sec_sess->userdata; @@ -1415,6 +1410,46 @@ cn10k_cryptodev_sec_inb_rx_inject(void *dev, struct rte_mbuf **pkts, hw_res = RTE_PTR_ALIGN_CEIL(hw_res, 16); /* Prepare CPT instruction */ + if (m->nb_segs > 1) { + struct rte_mbuf *last = rte_pktmbuf_lastseg(m); + uintptr_t dptr, rxphdr, wqe_hdr; + uint16_t i; + + if ((m->nb_segs > CNXK_CPT_MAX_SG_SEGS) || + (rte_pktmbuf_tailroom(m) < CNXK_CPT_MIN_TAILROOM_REQ)) + goto exit; + + wqe_hdr = rte_pktmbuf_mtod_offset(last, uintptr_t, last->data_len); + wqe_hdr += BIT_ULL(7); + wqe_hdr = (wqe_hdr - 1) & ~(BIT_ULL(7) - 1); + + /* Pointer to WQE header */ + *(uint64_t *)(m + 1) = wqe_hdr; + + /* Reserve SG list after end of last mbuf data location. */ + rxphdr = wqe_hdr + 8; + dptr = rxphdr + 7 * 8; + + /* Prepare Multiseg SG list */ + i = fill_sg2_comp_from_pkt((struct roc_sg2list_comp *)dptr, 0, m); + u64_dptr = dptr | ((uint64_t)(i) << 60); + } else { + struct roc_sg2list_comp *sg2; + uintptr_t dptr, wqe_hdr; + + /* Reserve space for WQE, NIX_RX_PARSE_S and SG_S. + * Populate SG_S with num segs and seg length + */ + wqe_hdr = (uintptr_t)(m + 1); + *(uint64_t *)(m + 1) = wqe_hdr; + + sg2 = (struct roc_sg2list_comp *)(wqe_hdr + 8 * 8); + sg2->u.s.len[0] = rte_pktmbuf_pkt_len(m); + sg2->u.s.valid_segs = 1; + + dptr = (uint64_t)rte_pktmbuf_iova(m); + u64_dptr = dptr; + } /* Word 0 and 1 */ inst_01 = vdupq_n_u64(0); @@ -1434,16 +1469,12 @@ cn10k_cryptodev_sec_inb_rx_inject(void *dev, struct rte_mbuf **pkts, inst_45 = vdupq_n_u64(0); u64_0 = sec_sess->inst.w4 | (rte_pktmbuf_pkt_len(m)); inst_45 = vsetq_lane_u64(u64_0, inst_45, 0); - dptr = (uint64_t)rte_pktmbuf_iova(m); - u64_1 = dptr; - inst_45 = vsetq_lane_u64(u64_1, inst_45, 1); + inst_45 = vsetq_lane_u64(u64_dptr, inst_45, 1); vst1q_u64(&inst->w4.u64, inst_45); /* Word 6 and 7 */ inst_67 = vdupq_n_u64(0); - u64_0 = dptr; u64_1 = sec_sess->inst.w7; - inst_67 = vsetq_lane_u64(u64_0, inst_67, 0); inst_67 = vsetq_lane_u64(u64_1, inst_67, 1); vst1q_u64(&inst->w6.u64, inst_67); diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h index caf6ac35e5..460e4803d3 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h @@ -18,7 +18,14 @@ /* Space for ctrl_word(8B), IV(48B), passthrough alignment(8B) */ #define CNXK_CPT_MIN_HEADROOM_REQ 64 -#define CNXK_CPT_MIN_TAILROOM_REQ 102 +/* Tailroom required for RX-inject path. + * In RX-inject path, space is required for below entities: + * WQE header and NIX_RX_PARSE_S + * SG list format for 6 IOVA pointers + * Space for 128 byte alignment. + */ +#define CNXK_CPT_MIN_TAILROOM_REQ 256 +#define CNXK_CPT_MAX_SG_SEGS 6 /* Default command timeout in seconds */ #define DEFAULT_COMMAND_TIMEOUT 4