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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CY4PEPF0000EE3D.mail.protection.outlook.com (10.167.242.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7918.13 via Frontend Transport; Fri, 6 Sep 2024 10:22:26 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 6 Sep 2024 03:22:11 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 6 Sep 2024 03:22:08 -0700 From: Gavin Li To: , , , , Dariusz Sosnowski , Bing Zhao , Suanming Mou , Alexander Kozyrev CC: , , "Minggang Li (Gavin)" , Subject: [PATCH 1/3] net/mlx5: set rte errno if malloc failed Date: Fri, 6 Sep 2024 13:21:49 +0300 Message-ID: <20240906102151.171965-2-gavinl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240906102151.171965-1-gavinl@nvidia.com> References: <20240906102151.171965-1-gavinl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3D:EE_|CH3PR12MB9097:EE_ X-MS-Office365-Filtering-Correlation-Id: 343dc923-1ea4-4f43-6435-08dcce5dce5e X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Sep 2024 10:22:26.7778 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 343dc923-1ea4-4f43-6435-08dcce5dce5e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9097 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: "Minggang Li (Gavin)" rte_errno should be set if anything wrong happened in under layer so that user can figure out what's going on. There were some cases that did not set it when ipool allcation failed. To fix the issue, set rte_errno to ENOMEM if mlx5_ipool_malloc failed to allocate ID. Fixes: c40c061a02 ("net/mlx5: add basic flow queue operation") Fixes: 48fbb0e93d ("net/mlx5: support flow meter mark indirect action with HWS") cc: stable@dpdk.org Signed-off-by: Gavin Li Acked-by: Bing Zhao --- drivers/net/mlx5/mlx5_flow_hw.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 50888944a5..509de2a6a4 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -1897,7 +1897,7 @@ flow_hw_meter_mark_alloc(struct rte_eth_dev *dev, uint32_t queue, const struct rte_flow_action_meter_mark *meter_mark = action->conf; struct mlx5_aso_mtr *aso_mtr; struct mlx5_flow_meter_info *fm; - uint32_t mtr_id; + uint32_t mtr_id = 0; uintptr_t handle = (uintptr_t)MLX5_INDIRECT_ACTION_TYPE_METER_MARK << MLX5_INDIRECT_ACTION_TYPE_OFFSET; @@ -1909,8 +1909,15 @@ flow_hw_meter_mark_alloc(struct rte_eth_dev *dev, uint32_t queue, if (meter_mark->profile == NULL) return NULL; aso_mtr = mlx5_ipool_malloc(pool->idx_pool, &mtr_id); - if (!aso_mtr) + if (!aso_mtr) { + rte_flow_error_set(error, ENOMEM, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "failed to allocate aso meter entry"); + if (mtr_id) + mlx5_ipool_free(pool->idx_pool, mtr_id); return NULL; + } /* Fill the flow meter parameters. */ aso_mtr->type = ASO_METER_INDIRECT; fm = &aso_mtr->fm; @@ -3918,8 +3925,10 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev, return NULL; } flow = mlx5_ipool_malloc(table->flow, &flow_idx); - if (!flow) + if (!flow) { + rte_errno = ENOMEM; goto error; + } rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue); /* * Set the table here in order to know the destination table @@ -3930,8 +3939,10 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev, flow->idx = flow_idx; if (table->resource) { mlx5_ipool_malloc(table->resource, &res_idx); - if (!res_idx) + if (!res_idx) { + rte_errno = ENOMEM; goto error; + } flow->res_idx = res_idx; } else { flow->res_idx = flow_idx; @@ -4062,8 +4073,10 @@ flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev, return NULL; } flow = mlx5_ipool_malloc(table->flow, &flow_idx); - if (!flow) + if (!flow) { + rte_errno = ENOMEM; goto error; + } rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue); /* * Set the table here in order to know the destination table @@ -4074,8 +4087,10 @@ flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev, flow->idx = flow_idx; if (table->resource) { mlx5_ipool_malloc(table->resource, &res_idx); - if (!res_idx) + if (!res_idx) { + rte_errno = ENOMEM; goto error; + } flow->res_idx = res_idx; } else { flow->res_idx = flow_idx; @@ -4210,8 +4225,10 @@ flow_hw_async_flow_update(struct rte_eth_dev *dev, nf->idx = of->idx; if (table->resource) { mlx5_ipool_malloc(table->resource, &res_idx); - if (!res_idx) + if (!res_idx) { + rte_errno = ENOMEM; goto error; + } nf->res_idx = res_idx; } else { nf->res_idx = of->res_idx;