diff mbox series

net/mlx5: fix internal SQ item definition

Message ID 20241027140941.127233-1-getelson@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: fix internal SQ item definition |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/github-robot: build success github build: passed
ci/intel-Functional success Functional PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-marvell-Functional success Functional Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-unit-amd64-testing success Testing PASS
ci/iol-unit-arm64-testing warning Testing issues
ci/iol-compile-arm64-testing success Testing PASS
ci/iol-compile-amd64-testing success Testing PASS
ci/iol-sample-apps-testing success Testing PASS

Commit Message

Etelson, Gregory Oct. 27, 2024, 2:09 p.m. UTC 
When DPDK copies flow items with the `rte_flow_conv` call, it assumes
that size of PMD private data has pointer size - see patch [1]

MLX5 PMD defined `struct mlx5_rte_flow_item_sq` as 32 bits.
As the result, on 64 bits systems, when DPDK copied
MLX5_RTE_FLOW_ITEM_TYPE_SQ item, the target buffer was assigned
additional 32 bits.

The patch expands size of `struct mlx5_rte_flow_item_sq` to 64 bits
on 64 bits systems.

[1]:
commit 6cf72047332b ("ethdev: support flow elements with variable length")

Fixes: 75a00812b18f ("net/mlx5: add hardware steering item translation")

Cc: stable@dpdk.org

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow.h | 3 +++
 1 file changed, 3 insertions(+)

Comments

Raslan Darawsheh Oct. 28, 2024, 1:17 p.m. UTC | #1 
Hi,

From: Gregory Etelson <getelson@nvidia.com>
Sent: Sunday, October 27, 2024 4:09 PM
To: dev@dpdk.org
Cc: Gregory Etelson; Maayan Kashani; Raslan Darawsheh; stable@dpdk.org; Dariusz Sosnowski; Slava Ovsiienko; Bing Zhao; Ori Kam; Suanming Mou; Matan Azrad
Subject: [PATCH] net/mlx5: fix internal SQ item definition

When DPDK copies flow items with the `rte_flow_conv` call, it assumes
that size of PMD private data has pointer size - see patch [1]

MLX5 PMD defined `struct mlx5_rte_flow_item_sq` as 32 bits.
As the result, on 64 bits systems, when DPDK copied
MLX5_RTE_FLOW_ITEM_TYPE_SQ item, the target buffer was assigned
additional 32 bits.

The patch expands size of `struct mlx5_rte_flow_item_sq` to 64 bits
on 64 bits systems.

[1]:
commit 6cf72047332b ("ethdev: support flow elements with variable length")

Fixes: 75a00812b18f ("net/mlx5: add hardware steering item translation")

Cc: stable@dpdk.org

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index db56ae051d..9cf54c3a6a 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -168,6 +168,9 @@  struct mlx5_flow_action_copy_mreg {
 /* Matches on source queue. */
 struct mlx5_rte_flow_item_sq {
 	uint32_t queue; /* DevX SQ number */
+#ifdef RTE_ARCH_64
+	uint32_t reserved;
+#endif
 };
 
 /* Map from registers to modify fields. */