[v8,1/9] net/zxdh: add zxdh ethdev pmd driver
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Commit Message
Add basic zxdh ethdev init and register PCI probe functions
Update doc files.
Signed-off-by: Junlong Wang <wang.junlong1@zte.com.cn>
---
MAINTAINERS | 6 ++
doc/guides/nics/features/zxdh.ini | 9 +++
doc/guides/nics/index.rst | 1 +
doc/guides/nics/zxdh.rst | 31 +++++++++
doc/guides/rel_notes/release_24_11.rst | 4 ++
drivers/net/meson.build | 1 +
drivers/net/zxdh/meson.build | 18 +++++
drivers/net/zxdh/zxdh_ethdev.c | 92 ++++++++++++++++++++++++++
drivers/net/zxdh/zxdh_ethdev.h | 44 ++++++++++++
9 files changed, 206 insertions(+)
create mode 100644 doc/guides/nics/features/zxdh.ini
create mode 100644 doc/guides/nics/zxdh.rst
create mode 100644 drivers/net/zxdh/meson.build
create mode 100644 drivers/net/zxdh/zxdh_ethdev.c
create mode 100644 drivers/net/zxdh/zxdh_ethdev.h
--
2.27.0
Comments
On 11/1/2024 6:21 AM, Junlong Wang wrote:
> v9:
> - fix 'v8 3/9' patch use PCI bus API,
> and common PCI constants according to David Marchand's comments.
>
> v8:
> - fix flexible arrays、Waddress-of-packed-member error.
> - all structs、enum、define ,etc use zxdh/ZXDH_ prefixed.
> - use zxdh_try/release_lock,and move loop into zxdh_timedlock,
> make hardware lock follow spinlock pattern.
>
> v7:
> - add release notes and modify zxdh.rst issues.
> - avoid use pthread and use rte_spinlock_lock.
> - using the prefix ZXDH_ before some definitions.
> - resole issues according to thomas's comments.
>
> v6:
> - Resolve ci/intel compilation issues.
> - fix meson.build indentation in earlier patch.
>
> V5:
> - split driver into multiple patches,part of the zxdh driver,
> later provide dev start/stop,queue_setup,npsdk_init,mac,vlan,rss ,etc.
> - fix errors reported by scripts.
> - move the product link in zxdh.rst.
> - fix meson check use RTE_ARCH_X86_64/RTE_ARCH_ARM64.
> - modify other comments according to Ferruh's comments.
>
> Junlong Wang (9):
> net/zxdh: add zxdh ethdev pmd driver
> net/zxdh: add logging implementation
> net/zxdh: add zxdh device pci init implementation
> net/zxdh: add msg chan and msg hwlock init
> net/zxdh: add msg chan enable implementation
> net/zxdh: add zxdh get device backend infos
> net/zxdh: add configure zxdh intr implementation
> net/zxdh: add zxdh dev infos get ops
> net/zxdh: add zxdh dev configure ops
>
Hi Junlong,
I can see not all of the eth_dev_ops implemented, and datapath not
implemented, so driver is not functional right now.
What happens if you want to run testpmd with the current state of the
driver, I assume it crashes?
And what is the plan for the driver? Are you planning to upstream
remaining support in this release or in future releases?
As the driver is not functional yet, to set the expectation right for
the users, I suggest marking driver as experimental in the maintainers
file and document the restrictions in the driver documentation, also
clarify this in the release notes update, what do you think?
@@ -1043,6 +1043,12 @@ F: drivers/net/virtio/
F: doc/guides/nics/virtio.rst
F: doc/guides/nics/features/virtio*.ini
+ZTE zxdh
+M: Lijie Shan <shan.lijie@zte.com.cn>
+F: drivers/net/zxdh/
+F: doc/guides/nics/zxdh.rst
+F: doc/guides/nics/features/zxdh.ini
+
Wind River AVP
M: Steven Webster <steven.webster@windriver.com>
M: Matt Peters <matt.peters@windriver.com>
new file mode 100644
@@ -0,0 +1,9 @@
+;
+; Supported features of the 'zxdh' network poll mode driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Linux = Y
+x86-64 = Y
+ARMv8 = Y
@@ -69,3 +69,4 @@ Network Interface Controller Drivers
vhost
virtio
vmxnet3
+ zxdh
new file mode 100644
@@ -0,0 +1,31 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2024 ZTE Corporation.
+
+ZXDH Poll Mode Driver
+======================
+
+The ZXDH PMD (**librte_net_zxdh**) provides poll mode driver support
+for 25/100 Gbps ZXDH NX Series Ethernet Controller based on
+the ZTE Ethernet Controller E310/E312.
+
+- Learn about ZXDH NX Series Ethernet Controller NICs using
+ `<https://enterprise.zte.com.cn/sup-detail.html?id=271&suptype=1>`_.
+
+Features
+--------
+
+Features of the ZXDH PMD are:
+
+- Multi arch support: x86_64, ARMv8.
+
+
+Driver compilation and testing
+------------------------------
+
+Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`
+for details.
+
+Limitations or Known issues
+---------------------------
+
+X86-32, Power8, ARMv7, RISC-V, Windows and BSD are not supported yet.
@@ -161,6 +161,10 @@ New Features
* Added initialization of FPGA modules related to flow HW offload.
* Added basic handling of the virtual queues.
+ * **Updated ZTE zxdh net driver.**
+
+ * Added ethdev driver support for zxdh NX Series Ethernet Controller.
+
* **Added cryptodev queue pair reset support.**
A new API ``rte_cryptodev_queue_pair_reset`` is added
@@ -62,6 +62,7 @@ drivers = [
'vhost',
'virtio',
'vmxnet3',
+ 'zxdh',
]
std_deps = ['ethdev', 'kvargs'] # 'ethdev' also pulls in mbuf, net, eal etc
std_deps += ['bus_pci'] # very many PMDs depend on PCI, so make std
new file mode 100644
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2024 ZTE Corporation
+
+if not is_linux
+ build = false
+ reason = 'only supported on Linux'
+ subdir_done()
+endif
+
+if not dpdk_conf.has('RTE_ARCH_X86_64') or not dpdk_conf.get('RTE_ARCH_64')
+ build = false
+ reason = 'only supported on x86_64 and aarch64'
+ subdir_done()
+endif
+
+sources = files(
+ 'zxdh_ethdev.c',
+)
new file mode 100644
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 ZTE Corporation
+ */
+
+#include <ethdev_pci.h>
+#include <bus_pci_driver.h>
+#include <rte_ethdev.h>
+
+#include "zxdh_ethdev.h"
+
+static int zxdh_eth_dev_init(struct rte_eth_dev *eth_dev)
+{
+ struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
+ struct zxdh_hw *hw = eth_dev->data->dev_private;
+ int ret = 0;
+
+ eth_dev->dev_ops = NULL;
+
+ /* Allocate memory for storing MAC addresses */
+ eth_dev->data->mac_addrs = rte_zmalloc("zxdh_mac",
+ ZXDH_MAX_MAC_ADDRS * RTE_ETHER_ADDR_LEN, 0);
+ if (eth_dev->data->mac_addrs == NULL)
+ return -ENOMEM;
+
+ memset(hw, 0, sizeof(*hw));
+ hw->bar_addr[0] = (uint64_t)pci_dev->mem_resource[0].addr;
+ if (hw->bar_addr[0] == 0)
+ return -EIO;
+
+ hw->device_id = pci_dev->id.device_id;
+ hw->port_id = eth_dev->data->port_id;
+ hw->eth_dev = eth_dev;
+ hw->speed = RTE_ETH_SPEED_NUM_UNKNOWN;
+ hw->duplex = RTE_ETH_LINK_FULL_DUPLEX;
+ hw->is_pf = 0;
+
+ if (pci_dev->id.device_id == ZXDH_E310_PF_DEVICEID ||
+ pci_dev->id.device_id == ZXDH_E312_PF_DEVICEID) {
+ hw->is_pf = 1;
+ }
+
+ return ret;
+}
+
+static int zxdh_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+ struct rte_pci_device *pci_dev)
+{
+ return rte_eth_dev_pci_generic_probe(pci_dev,
+ sizeof(struct zxdh_hw),
+ zxdh_eth_dev_init);
+}
+
+static int zxdh_dev_close(struct rte_eth_dev *dev __rte_unused)
+{
+ int ret = 0;
+
+ return ret;
+}
+
+static int zxdh_eth_dev_uninit(struct rte_eth_dev *eth_dev)
+{
+ int ret = 0;
+
+ ret = zxdh_dev_close(eth_dev);
+
+ return ret;
+}
+
+static int zxdh_eth_pci_remove(struct rte_pci_device *pci_dev)
+{
+ int ret = rte_eth_dev_pci_generic_remove(pci_dev, zxdh_eth_dev_uninit);
+
+ return ret;
+}
+
+static const struct rte_pci_id pci_id_zxdh_map[] = {
+ {RTE_PCI_DEVICE(ZXDH_PCI_VENDOR_ID, ZXDH_E310_PF_DEVICEID)},
+ {RTE_PCI_DEVICE(ZXDH_PCI_VENDOR_ID, ZXDH_E310_VF_DEVICEID)},
+ {RTE_PCI_DEVICE(ZXDH_PCI_VENDOR_ID, ZXDH_E312_PF_DEVICEID)},
+ {RTE_PCI_DEVICE(ZXDH_PCI_VENDOR_ID, ZXDH_E312_VF_DEVICEID)},
+ {.vendor_id = 0, /* sentinel */ },
+};
+static struct rte_pci_driver zxdh_pmd = {
+ .id_table = pci_id_zxdh_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
+ .probe = zxdh_eth_pci_probe,
+ .remove = zxdh_eth_pci_remove,
+};
+
+RTE_PMD_REGISTER_PCI(net_zxdh, zxdh_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(net_zxdh, pci_id_zxdh_map);
+RTE_PMD_REGISTER_KMOD_DEP(net_zxdh, "* vfio-pci");
new file mode 100644
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 ZTE Corporation
+ */
+
+#ifndef ZXDH_ETHDEV_H
+#define ZXDH_ETHDEV_H
+
+#include "ethdev_driver.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ZXDH PCI vendor/device ID. */
+#define ZXDH_PCI_VENDOR_ID 0x1cf2
+
+#define ZXDH_E310_PF_DEVICEID 0x8061
+#define ZXDH_E310_VF_DEVICEID 0x8062
+#define ZXDH_E312_PF_DEVICEID 0x8049
+#define ZXDH_E312_VF_DEVICEID 0x8060
+
+#define ZXDH_MAX_UC_MAC_ADDRS 32
+#define ZXDH_MAX_MC_MAC_ADDRS 32
+#define ZXDH_MAX_MAC_ADDRS (ZXDH_MAX_UC_MAC_ADDRS + ZXDH_MAX_MC_MAC_ADDRS)
+
+#define ZXDH_NUM_BARS 2
+
+struct zxdh_hw {
+ struct rte_eth_dev *eth_dev;
+ uint64_t bar_addr[ZXDH_NUM_BARS];
+
+ uint32_t speed;
+ uint16_t device_id;
+ uint16_t port_id;
+
+ uint8_t duplex;
+ uint8_t is_pf;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZXDH_ETHDEV_H */