diff mbox series

net/mlx5: fix GRE open matcher does not match packet

Message ID 20250128075930.175636-1-mkashani@nvidia.com (mailing list archive)
State Awaiting Upstream
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: fix GRE open matcher does not match packet |

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Commit Message

Maayan Kashani Jan. 28, 2025, 7:59 a.m. UTC 
The previous GRE fix was meant to handle HWS behavior
and changed the behavior for SWS causing degradation.

After the previous fix, in case of an empty GRE match,
GRE mask was initialized with protocol full mask,
Instead of the empty mask with protocol mask equals zero.

The Current fix handles the SWS case as before the GRE fix,
and HWS according to the latest fix.
Also, combined common logic.

Fixes: 25ab2cbba31d ("net/mlx5: fix GRE flow item translation for root table")
Cc: stable@dpdk.org
Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_dv.c | 27 +++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)

Comments

Raslan Darawsheh Feb. 10, 2025, 10:31 a.m. UTC | #1 
Hi,

From: Maayan Kashani <mkashani@nvidia.com>
Sent: Tuesday, January 28, 2025 9:59 AM
To: dev@dpdk.org
Cc: Maayan Kashani; Raslan Darawsheh; stable@dpdk.org; Bing Zhao; Dariusz Sosnowski; Slava Ovsiienko; Ori Kam; Suanming Mou; Matan Azrad; Gregory Etelson
Subject: [PATCH] net/mlx5: fix GRE open matcher does not match packet

The previous GRE fix was meant to handle HWS behavior
and changed the behavior for SWS causing degradation.

After the previous fix, in case of an empty GRE match,
GRE mask was initialized with protocol full mask,
Instead of the empty mask with protocol mask equals zero.

The Current fix handles the SWS case as before the GRE fix,
and HWS according to the latest fix.
Also, combined common logic.

Fixes: 25ab2cbba31d ("net/mlx5: fix GRE flow item translation for root table")
Cc: stable@dpdk.org
Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 41ebe0b61a4..633c41e358b 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -9839,23 +9839,26 @@  flow_dv_translate_item_gre(void *key, const struct rte_flow_item *item,
 	} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
 	uint16_t protocol_m, protocol_v;
 
-	if (key_type & MLX5_SET_MATCHER_M) {
+	/* Common logic to SWS/HWS */
+	if (key_type & MLX5_SET_MATCHER_M)
 		MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 0xff);
+	else
+		MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
+			IPPROTO_GRE);
+	/* HWS mask logic only */
+	if (key_type & MLX5_SET_MATCHER_HS_M) {
 		if (!gre_m)
 			gre_m = &rte_flow_item_gre_mask;
 		gre_v = gre_m;
-	} else {
-		MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
-			 IPPROTO_GRE);
-		if (!gre_v) {
-			gre_v = &empty_gre;
-			gre_m = &empty_gre;
-		} else if (!gre_m) {
-			gre_m = &rte_flow_item_gre_mask;
-		}
-		if (key_type == MLX5_SET_MATCHER_HS_V)
-			gre_m = gre_v;
+	} else if (!gre_v) {
+		gre_v = &empty_gre;
+		gre_m = &empty_gre;
+	} else if (!gre_m) {
+		gre_m = &rte_flow_item_gre_mask;
 	}
+	/* SWS logic only */
+	if (key_type & MLX5_SET_MATCHER_SW_M)
+		gre_v = gre_m;
 	gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
 	gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
 	MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,