diff mbox series

[v1,19/30] net/i40e/base: align registers to the specification

Message ID 3bcfe533ee6dfe3b5f05ed6da0c897188d97e9a3.1725270827.git.anatoly.burakov@intel.com (mailing list archive)
State Accepted
Delegated to: Bruce Richardson
Headers
Series Update net/i40e base driver |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Burakov, Anatoly Sept. 2, 2024, 9:54 a.m. UTC 
From: Michal Nowak <michal2.nowak@intel.com>

The I40E_PFPM_APM, I40E_PFPM_WUC, I40E_PFPM_WUFC, and I40E_PFPM_WUS should
read bits per PF.

Signed-off-by: Michal Nowak <michal2.nowak@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
 drivers/net/i40e/base/i40e_register.h | 8 ++++----
 drivers/net/i40e/i40e_regs.h          | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h
index 55f671c3c5..f440f0cbd1 100644
--- a/drivers/net/i40e/base/i40e_register.h
+++ b/drivers/net/i40e/base/i40e_register.h
@@ -3072,17 +3072,17 @@ 
 #define I40E_GLPM_WUMC_RESERVED_4_MASK    I40E_MASK(0x1FFF, I40E_GLPM_WUMC_RESERVED_4_SHIFT)
 #define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT    16
 #define I40E_GLPM_WUMC_MNG_WU_PF_MASK     I40E_MASK(0xFFFF, I40E_GLPM_WUMC_MNG_WU_PF_SHIFT)
-#define I40E_PFPM_APM            0x000B8080 /* Reset: POR */
+#define I40E_PFPM_APM(_PF)       (0x000B8080 + ((_PF) * 4)) /* Reset: POR */
 #define I40E_PFPM_APM_APME_SHIFT 0
 #define I40E_PFPM_APM_APME_MASK  I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT)
 #define I40E_PFPM_FHFT_LENGTH(_i)          (0x0006A000 + ((_i) * 128)) /* _i=0...7 */ /* Reset: POR */
 #define I40E_PFPM_FHFT_LENGTH_MAX_INDEX    7
 #define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0
 #define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK  I40E_MASK(0xFF, I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT)
-#define I40E_PFPM_WUC                 0x0006B200 /* Reset: POR */
+#define I40E_PFPM_WUC(_PF)            (0x0006B200 + ((_PF) * 4)) /* Reset: POR */
 #define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5
 #define I40E_PFPM_WUC_EN_APM_D0_MASK  I40E_MASK(0x1, I40E_PFPM_WUC_EN_APM_D0_SHIFT)
-#define I40E_PFPM_WUFC                 0x0006B400 /* Reset: POR */
+#define I40E_PFPM_WUFC(_PF)            (0x0006B400 + ((_PF) * 4)) /* Reset: POR */
 #define I40E_PFPM_WUFC_LNKC_SHIFT      0
 #define I40E_PFPM_WUFC_LNKC_MASK       I40E_MASK(0x1, I40E_PFPM_WUFC_LNKC_SHIFT)
 #define I40E_PFPM_WUFC_MAG_SHIFT       1
@@ -3123,7 +3123,7 @@ 
 #define I40E_PFPM_WUFC_FLX7_MASK       I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_SHIFT)
 #define I40E_PFPM_WUFC_FW_RST_WK_SHIFT 31
 #define I40E_PFPM_WUFC_FW_RST_WK_MASK  I40E_MASK(0x1, I40E_PFPM_WUFC_FW_RST_WK_SHIFT)
-#define I40E_PFPM_WUS                  0x0006B600 /* Reset: POR */
+#define I40E_PFPM_WUS(_PF)             (0x0006B600 + ((_PF) * 4)) /* Reset: POR */
 #define I40E_PFPM_WUS_LNKC_SHIFT       0
 #define I40E_PFPM_WUS_LNKC_MASK        I40E_MASK(0x1, I40E_PFPM_WUS_LNKC_SHIFT)
 #define I40E_PFPM_WUS_MAG_SHIFT        1
diff --git a/drivers/net/i40e/i40e_regs.h b/drivers/net/i40e/i40e_regs.h
index e6f8866e9f..35ff12f1f7 100644
--- a/drivers/net/i40e/i40e_regs.h
+++ b/drivers/net/i40e/i40e_regs.h
@@ -339,9 +339,9 @@  static const struct i40e_reg_info i40e_regs_others[] = {
 	{I40E_GLLAN_TSOMSK_L, 0, 0, 0, 0, "GLLAN_TSOMSK_L"},
 	{I40E_GL_RDPU_CNTRL, 0, 0, 0, 0, "GL_RDPU_CNTRL"},
 	{I40E_PFPM_FHFT_LENGTH(0), 7, 128, 0, 0, "PFPM_FHFT_LENGTH"},
-	{I40E_PFPM_WUC, 0, 0, 0, 0, "PFPM_WUC"},
-	{I40E_PFPM_WUFC, 0, 0, 0, 0, "PFPM_WUFC"},
-	{I40E_PFPM_WUS, 0, 0, 0, 0, "PFPM_WUS"},
+	{I40E_PFPM_WUC(0), 0, 0, 0, 0, "PFPM_WUC"},
+	{I40E_PFPM_WUFC(0), 0, 0, 0, 0, "PFPM_WUFC"},
+	{I40E_PFPM_WUS(0), 0, 0, 0, 0, "PFPM_WUS"},
 	{I40E_PRTPM_FHFHR, 0, 0, 0, 0, "PRTPM_FHFHR"},
 	{I40E_GLPM_WUMC, 0, 0, 0, 0, "GLPM_WUMC"},
 	{I40E_VPLAN_QTABLE(0, 0), 15, 1024, 127, 4, "VPLAN_QTABLE"},
@@ -524,7 +524,7 @@  static const struct i40e_reg_info i40e_regs_others[] = {
 	{I40E_MNGSB_WDATA, 0, 0, 0, 0, "MNGSB_WDATA"},
 	{I40E_MNGSB_RHDR0, 0, 0, 0, 0, "MNGSB_RHDR0"},
 	{I40E_MNGSB_RDATA, 0, 0, 0, 0, "MNGSB_RDATA"},
-	{I40E_PFPM_APM, 0, 0, 0, 0, "PFPM_APM"},
+	{I40E_PFPM_APM(0), 0, 0, 0, 0, "PFPM_APM"},
 	{I40E_PRTGEN_STATUS, 0, 0, 0, 0, "PRTGEN_STATUS"},
 	{I40E_PRTGEN_CNF, 0, 0, 0, 0, "PRTGEN_CNF"},
 	{I40E_PRTPM_GC, 0, 0, 0, 0, "PRTPM_GC"},