From: Nir Efrati <nir.efrati@intel.com>
Remove workaround for hardware synchronization before reset. The original
bug that was fixed by this workaround was root caused later and fixed in
other ways.
Signed-off-by: Nir Efrati <nir.efrati@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
drivers/net/intel/e1000/base/e1000_ich8lan.c | 17 -----------------
1 file changed, 17 deletions(-)
@@ -4922,7 +4922,6 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
u16 kum_cfg;
u32 ctrl, reg;
s32 ret_val;
- u16 pci_cfg;
DEBUGFUNC("e1000_reset_hw_ich8lan");
@@ -4984,27 +4983,11 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
}
ret_val = e1000_acquire_swflag_ich8lan(hw);
- /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
- * may occur during global reset and cause system hang.
- * Configuration space access creates the needed delay.
- * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
- * insures configuration space read is done before global reset.
- */
- e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
- E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
DEBUGOUT("Issuing a global reset to ich8lan\n");
E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
/* cannot issue a flush here because it hangs the hardware */
msec_delay(20);
- /* Configuration space access improve HW level time sync mechanism.
- * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
- * value to insure configuration space read is done
- * before any access to mac register.
- */
- e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
- E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
-
/* Set Phy Config Counter to 50msec */
if (hw->mac.type == e1000_pch2lan) {
reg = E1000_READ_REG(hw, E1000_FEXTNVM3);