Checks
Context | Check | Description |
---|---|---|
ci/checkpatch | warning | coding style issues |
Commit Message
Burakov, Anatoly
June 12, 2024, 3 p.m. UTC
From: Ian Stokes <ian.stokes@intel.com> Update the offsets, and remove the ICE_TX_GCS_DESC_ENA define since a non-0 value used for the ICE_TX_GCS_DESC_TYPE field will enable GCS offload; there is no dedicated bit to enable it anymore. Signed-off-by: Eric Joyner <eric.joyner@intel.com> Signed-off-by: Ian Stokes <ian.stokes@intel.com> --- drivers/net/ice/base/ice_lan_tx_rx.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h index d816df0ff6..39673e36f7 100644 --- a/drivers/net/ice/base/ice_lan_tx_rx.h +++ b/drivers/net/ice/base/ice_lan_tx_rx.h @@ -1074,10 +1074,9 @@ struct ice_tx_ctx_desc { __le64 qw1; }; -#define ICE_TX_GSC_DESC_START 0 /* 7 BITS */ -#define ICE_TX_GSC_DESC_OFFSET 7 /* 4 BITS */ -#define ICE_TX_GSC_DESC_TYPE 11 /* 2 BITS */ -#define ICE_TX_GSC_DESC_ENA 13 /* 1 BIT */ +#define ICE_TX_GCS_DESC_START 0 /* 8 BITS */ +#define ICE_TX_GCS_DESC_OFFSET 8 /* 4 BITS */ +#define ICE_TX_GCS_DESC_TYPE 12 /* 3 BITS */ #define ICE_TXD_CTX_QW1_DTYPE_S 0 #define ICE_TXD_CTX_QW1_DTYPE_M (0xFUL << ICE_TXD_CTX_QW1_DTYPE_S)