Checks
Context | Check | Description |
---|---|---|
ci/checkpatch | success | coding style OK |
Commit Message
Anatoly Burakov
June 12, 2024, 3 p.m. UTC
From: Ian Stokes <ian.stokes@intel.com> Add a mask used to extract FW load status from GL_MNG_FWSM. Signed-off-by: Jan Sokolowski <jan.sokolowski@intel.com> Signed-off-by: Ian Stokes <ian.stokes@intel.com> --- drivers/net/ice/base/ice_hw_autogen.h | 1 + 1 file changed, 1 insertion(+)
Comments
On Wed, Jun 12, 2024 at 04:00:34PM +0100, Anatoly Burakov wrote: > From: Ian Stokes <ian.stokes@intel.com> > > Add a mask used to extract FW load status from GL_MNG_FWSM. > > Signed-off-by: Jan Sokolowski <jan.sokolowski@intel.com> > Signed-off-by: Ian Stokes <ian.stokes@intel.com> > --- > drivers/net/ice/base/ice_hw_autogen.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h > index 3d5d8950bf..fde5f9d86f 100644 > --- a/drivers/net/ice/base/ice_hw_autogen.h > +++ b/drivers/net/ice/base/ice_hw_autogen.h > @@ -5474,6 +5474,7 @@ > #define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_S 1 > #define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_M BIT(1) > #define GL_MNG_FWSM 0x000B6134 /* Reset Source: POR */ > +#define GL_MNG_FWSM_FW_LOADING_M BIT(30) > #define GL_MNG_FWSM_FW_MODES_S 0 > #define GL_MNG_FWSM_FW_MODES_M MAKEMASK(0x7, 0) > #define GL_MNG_FWSM_RSV0_S 3 > -- This can be merged into another patch. Either patch 37 as I suggested in comment on it, or perhaps better in patch 3. /Bruce
diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h index 3d5d8950bf..fde5f9d86f 100644 --- a/drivers/net/ice/base/ice_hw_autogen.h +++ b/drivers/net/ice/base/ice_hw_autogen.h @@ -5474,6 +5474,7 @@ #define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_S 1 #define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_M BIT(1) #define GL_MNG_FWSM 0x000B6134 /* Reset Source: POR */ +#define GL_MNG_FWSM_FW_LOADING_M BIT(30) #define GL_MNG_FWSM_FW_MODES_S 0 #define GL_MNG_FWSM_FW_MODES_M MAKEMASK(0x7, 0) #define GL_MNG_FWSM_RSV0_S 3