[v2,47/54] net/e1000/base: fix static analysis warnings

Message ID c18fa0ca0bac6a59ae4559a8f4bb250d2730e653.1738681726.git.anatoly.burakov@intel.com (mailing list archive)
State Superseded
Delegated to: Bruce Richardson
Headers
Series Merge Intel IGC and E1000 drivers, and update E1000 base code |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Burakov, Anatoly Feb. 4, 2025, 3:10 p.m. UTC
From: Przemysław Ciesielski <przemyslaw.ciesielski@intel.com>

There are some static analysis warnings due to wrong data types being used
for various operations. Fix them with explicit typecasts.

Fixes: 5a32a257f957 ("e1000: more NICs in base driver")
Fixes: 38db3f7f50bd ("e1000: update base driver")
Cc: stable@dpdk.org

Signed-off-by: Przemysław Ciesielski <przemyslaw.ciesielski@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
 drivers/net/intel/e1000/base/e1000_80003es2lan.c | 2 +-
 drivers/net/intel/e1000/base/e1000_nvm.c         | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)
  

Patch

diff --git a/drivers/net/intel/e1000/base/e1000_80003es2lan.c b/drivers/net/intel/e1000/base/e1000_80003es2lan.c
index b1f2df3803..1cbce5bedd 100644
--- a/drivers/net/intel/e1000/base/e1000_80003es2lan.c
+++ b/drivers/net/intel/e1000/base/e1000_80003es2lan.c
@@ -426,7 +426,7 @@  STATIC void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 		; /* Empty */
 
 	swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
-	swfw_sync &= ~mask;
+	swfw_sync &= ~(u32)mask;
 	E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
 
 	e1000_put_hw_semaphore_generic(hw);
diff --git a/drivers/net/intel/e1000/base/e1000_nvm.c b/drivers/net/intel/e1000/base/e1000_nvm.c
index 0d43a49c14..70259da090 100644
--- a/drivers/net/intel/e1000/base/e1000_nvm.c
+++ b/drivers/net/intel/e1000/base/e1000_nvm.c
@@ -934,14 +934,14 @@  s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
 		DEBUGOUT("NVM Not Supported\n");
 		return -E1000_NOT_IMPLEMENTED;
 	}
-	*pba_num = (u32)(nvm_data << 16);
+	*pba_num = ((u32)nvm_data << 16);
 
 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
 	if (ret_val) {
 		DEBUGOUT("NVM Read Error\n");
 		return ret_val;
 	}
-	*pba_num |= nvm_data;
+	*pba_num |= (u32)nvm_data;
 
 	return E1000_SUCCESS;
 }