diff mbox series

[v2,069/148] net/ice/base: be more verbose when preparing timer sync

Message ID c19a2b53c0ab96c36c55f1c0eefd028c783a6a7b.1718204528.git.anatoly.burakov@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Bruce Richardson
Headers
Series Update net/ice base driver to latest upstream snapshot |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Burakov, Anatoly June 12, 2024, 3:01 p.m. UTC 
Add an informative error message when preparing external PHYs for a timer
sync fails.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
 drivers/net/ice/base/ice_ptp_hw.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 31d6c7cf81..81b57b068c 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -4932,9 +4932,16 @@  int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
 			  bool lock_sbq)
 {
 	u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
+	int err;
 
-	return ice_write_phy_reg_e810_lp(hw, E810_ETH_GLTSYN_CMD, val,
-					 lock_sbq);
+	err = ice_write_phy_reg_e810_lp(hw, E810_ETH_GLTSYN_CMD, val,
+					lock_sbq);
+	if (err) {
+		ice_debug(hw, ICE_DBG_PTP, "Failed to write back GLTSYN_CMD, err %d\n", err);
+		return err;
+	}
+
+	return 0;
 }
 
 /* E810T SMA functions