[v2,120/148] net/ice/base: add E830 PTP init

Message ID c5ddc5c11f3a9e97af992b19af5775bd047c5a2c.1718204529.git.anatoly.burakov@intel.com (mailing list archive)
State Superseded
Delegated to: Bruce Richardson
Headers
Series Update net/ice base driver to latest upstream snapshot |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Burakov, Anatoly June 12, 2024, 3:01 p.m. UTC
  Add E830 PTP initialization flow.

TXPP requires SW and HW timer clock synchronization which is done during
the PTP initialization flow.

The E810 and E830 PTP initialization flows are similar. The primary
difference that E810 initializes the PHY via AQCs, and E830 does not
initialize the external PHY.

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
 drivers/net/ice/base/ice_ptp_hw.c | 41 +++++++++++++++++++++++++++++--
 1 file changed, 39 insertions(+), 2 deletions(-)
  

Patch

diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index f287834a4d..487eb0bd92 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -911,6 +911,18 @@  static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
 	ice_flush(hw);
 }
 
+/**
+ * ice_ptp_zero_syn_dlay - Set synchronization delay to zero
+ * @hw: pointer to HW struct
+ *
+ * Zero E810 and E830 specific PTP hardware clock synchronization delay.
+ */
+static void ice_ptp_zero_syn_dlay(struct ice_hw *hw)
+{
+	wr32(hw, GLTSYN_SYNC_DLAY, 0);
+	ice_flush(hw);
+}
+
 enum eth56g_res_type {
 	ETH56G_PHY_REG,
 	ETH56G_PHY_MEM,
@@ -4899,8 +4911,7 @@  int ice_ptp_init_phy_e810(struct ice_hw *hw)
  */
 static int ice_ptp_init_phc_e810(struct ice_hw *hw)
 {
-	/* Ensure synchronization delay is zero */
-	wr32(hw, GLTSYN_SYNC_DLAY, 0);
+	ice_ptp_zero_syn_dlay(hw);
 
 	/* Initialize the PHY */
 	return ice_ptp_init_phy_e810(hw);
@@ -5400,6 +5411,24 @@  int ice_ptp_read_sdp_section_from_nvm(struct ice_hw *hw, bool *section_exist,
 	return err;
 }
 
+/* E830 functions
+ *
+ * The following functions operate on the E830 series devices.
+ *
+ */
+
+/**
+ * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization
+ * @hw: pointer to HW struct
+ *
+ * Perform E830-specific PTP hardware clock initialization steps.
+ */
+static int ice_ptp_init_phc_e830(struct ice_hw *hw)
+{
+	ice_ptp_zero_syn_dlay(hw);
+	return 0;
+}
+
 /**
  * ice_ptp_write_direct_incval_e830 - Prep PHY port increment value change
  * @hw: pointer to HW struct
@@ -5636,6 +5665,8 @@  void ice_ptp_init_phy_model(struct ice_hw *hw)
 
 	if (ice_is_e810(hw))
 		hw->phy_model = ICE_PHY_E810;
+	else if (ice_is_e830(hw))
+		hw->phy_model = ICE_PHY_E830;
 	else
 		hw->phy_model = ICE_PHY_E822;
 	hw->phy_ports = ICE_NUM_EXTERNAL_PORTS;
@@ -6113,6 +6144,7 @@  void ice_ptp_reset_ts_memory(struct ice_hw *hw)
 		ice_ptp_reset_ts_memory_e822(hw);
 		break;
 	case ICE_PHY_E810:
+	case ICE_PHY_E830:
 	default:
 		return;
 	}
@@ -6141,6 +6173,8 @@  int ice_ptp_init_phc(struct ice_hw *hw)
 		return ice_ptp_init_phc_e810(hw);
 	case ICE_PHY_E822:
 		return ice_ptp_init_phc_e822(hw);
+	case ICE_PHY_E830:
+		return ice_ptp_init_phc_e830(hw);
 	default:
 		return ICE_ERR_NOT_SUPPORTED;
 	}
@@ -6163,6 +6197,9 @@  int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)
 	case ICE_PHY_ETH56G:
 		return ice_get_phy_tx_tstamp_ready_eth56g(hw, block,
 							  tstamp_ready);
+	case ICE_PHY_E830:
+		return ice_get_phy_tx_tstamp_ready_e830(hw, block,
+							tstamp_ready);
 	case ICE_PHY_E810:
 		return ice_get_phy_tx_tstamp_ready_e810(hw, block,
 							tstamp_ready);