@@ -429,9 +429,11 @@
#define PF0INT_OICR_CPM_PAGE_QUEUE_S 1
#define PF0INT_OICR_CPM_PAGE_QUEUE_M BIT(1)
#define PF0INT_OICR_CPM_PAGE_RSV1_S 2
-#define PF0INT_OICR_CPM_PAGE_RSV1_M MAKEMASK(0xFF, 2)
-#define PF0INT_OICR_CPM_PAGE_HH_COMP_S 10
-#define PF0INT_OICR_CPM_PAGE_HH_COMP_M BIT(10)
+#define PF0INT_OICR_CPM_PAGE_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_CPM_PAGE_RSV1_M : E800_PF0INT_OICR_CPM_PAGE_RSV1_M)
+#define E800_PF0INT_OICR_CPM_PAGE_RSV1_M MAKEMASK(0xFF, 2)
+#define E830_PF0INT_OICR_CPM_PAGE_RSV1_M MAKEMASK(0x3F, 2)
+#define E800_PF0INT_OICR_CPM_PAGE_HH_COMP_S 10
+#define E800_PF0INT_OICR_CPM_PAGE_HH_COMP_M BIT(10)
#define PF0INT_OICR_CPM_PAGE_TSYN_TX_S 11
#define PF0INT_OICR_CPM_PAGE_TSYN_TX_M BIT(11)
#define PF0INT_OICR_CPM_PAGE_TSYN_EVNT_S 12
@@ -493,9 +495,11 @@
#define PF0INT_OICR_HLP_PAGE_QUEUE_S 1
#define PF0INT_OICR_HLP_PAGE_QUEUE_M BIT(1)
#define PF0INT_OICR_HLP_PAGE_RSV1_S 2
-#define PF0INT_OICR_HLP_PAGE_RSV1_M MAKEMASK(0xFF, 2)
-#define PF0INT_OICR_HLP_PAGE_HH_COMP_S 10
-#define PF0INT_OICR_HLP_PAGE_HH_COMP_M BIT(10)
+#define PF0INT_OICR_HLP_PAGE_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_HLP_PAGE_RSV1_M : E800_PF0INT_OICR_HLP_PAGE_RSV1_M)
+#define E800_PF0INT_OICR_HLP_PAGE_RSV1_M MAKEMASK(0xFF, 2)
+#define E830_PF0INT_OICR_HLP_PAGE_RSV1_M MAKEMASK(0x3F, 2)
+#define E800_PF0INT_OICR_HLP_PAGE_HH_COMP_S 10
+#define E800_PF0INT_OICR_HLP_PAGE_HH_COMP_M BIT(10)
#define PF0INT_OICR_HLP_PAGE_TSYN_TX_S 11
#define PF0INT_OICR_HLP_PAGE_TSYN_TX_M BIT(11)
#define PF0INT_OICR_HLP_PAGE_TSYN_EVNT_S 12
@@ -542,9 +546,11 @@
#define PF0INT_OICR_PSM_PAGE_QUEUE_S 1
#define PF0INT_OICR_PSM_PAGE_QUEUE_M BIT(1)
#define PF0INT_OICR_PSM_PAGE_RSV1_S 2
-#define PF0INT_OICR_PSM_PAGE_RSV1_M MAKEMASK(0xFF, 2)
-#define PF0INT_OICR_PSM_PAGE_HH_COMP_S 10
-#define PF0INT_OICR_PSM_PAGE_HH_COMP_M BIT(10)
+#define PF0INT_OICR_PSM_PAGE_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_PSM_PAGE_RSV1_M : E800_PF0INT_OICR_PSM_PAGE_RSV1_M)
+#define E800_PF0INT_OICR_PSM_PAGE_RSV1_M MAKEMASK(0xFF, 2)
+#define E830_PF0INT_OICR_PSM_PAGE_RSV1_M MAKEMASK(0x3F, 2)
+#define E800_PF0INT_OICR_PSM_PAGE_HH_COMP_S 10
+#define E800_PF0INT_OICR_PSM_PAGE_HH_COMP_M BIT(10)
#define PF0INT_OICR_PSM_PAGE_TSYN_TX_S 11
#define PF0INT_OICR_PSM_PAGE_TSYN_TX_M BIT(11)
#define PF0INT_OICR_PSM_PAGE_TSYN_EVNT_S 12
@@ -4397,11 +4403,11 @@
#define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)
#define GLTPB_100G_MAC_FC_THRESH_PORT1_FC_THRESH_S 16
#define GLTPB_100G_MAC_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)
-#define GLTPB_100G_RPB_FC_THRESH 0x0009963C /* Reset Source: CORER */
-#define GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_S 0
-#define GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)
-#define GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_S 16
-#define GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E800_GLTPB_100G_RPB_FC_THRESH 0x0009963C /* Reset Source: CORER */
+#define E800_GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_S 0
+#define E800_GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E800_GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_S 16
+#define E800_GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)
#define GLTPB_PACING_10G 0x000994E4 /* Reset Source: CORER */
#define GLTPB_PACING_10G_N_S 0
#define GLTPB_PACING_10G_N_M MAKEMASK(0xFF, 0)
@@ -4545,7 +4551,9 @@
#define GLINT_TSYN_PFMSTR_PF_MASTER_M MAKEMASK(0x7, 0)
#define GLINT_TSYN_PHY 0x0016CC50 /* Reset Source: CORER */
#define GLINT_TSYN_PHY_PHY_INDX_S 0
-#define GLINT_TSYN_PHY_PHY_INDX_M MAKEMASK(0x1F, 0)
+#define GLINT_TSYN_PHY_PHY_INDX_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLINT_TSYN_PHY_PHY_INDX_M : E800_GLINT_TSYN_PHY_PHY_INDX_M)
+#define E800_GLINT_TSYN_PHY_PHY_INDX_M MAKEMASK(0x1F, 0)
+#define E830_GLINT_TSYN_PHY_PHY_INDX_M MAKEMASK(0xFF, 0)
#define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
#define GLINT_VECT2FUNC_MAX_INDEX 2047
#define GLINT_VECT2FUNC_VF_NUM_S 0
@@ -4605,9 +4613,11 @@
#define PF0INT_OICR_CPM_QUEUE_S 1
#define PF0INT_OICR_CPM_QUEUE_M BIT(1)
#define PF0INT_OICR_CPM_RSV1_S 2
-#define PF0INT_OICR_CPM_RSV1_M MAKEMASK(0xFF, 2)
-#define PF0INT_OICR_CPM_HH_COMP_S 10
-#define PF0INT_OICR_CPM_HH_COMP_M BIT(10)
+#define PF0INT_OICR_CPM_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_CPM_RSV1_M : E800_PF0INT_OICR_CPM_RSV1_M)
+#define E800_PF0INT_OICR_CPM_RSV1_M MAKEMASK(0xFF, 2)
+#define E830_PF0INT_OICR_CPM_RSV1_M MAKEMASK(0x3F, 2)
+#define E800_PF0INT_OICR_CPM_HH_COMP_S 10
+#define E800_PF0INT_OICR_CPM_HH_COMP_M BIT(10)
#define PF0INT_OICR_CPM_TSYN_TX_S 11
#define PF0INT_OICR_CPM_TSYN_TX_M BIT(11)
#define PF0INT_OICR_CPM_TSYN_EVNT_S 12
@@ -4696,9 +4706,11 @@
#define PF0INT_OICR_HLP_QUEUE_S 1
#define PF0INT_OICR_HLP_QUEUE_M BIT(1)
#define PF0INT_OICR_HLP_RSV1_S 2
-#define PF0INT_OICR_HLP_RSV1_M MAKEMASK(0xFF, 2)
-#define PF0INT_OICR_HLP_HH_COMP_S 10
-#define PF0INT_OICR_HLP_HH_COMP_M BIT(10)
+#define PF0INT_OICR_HLP_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_HLP_RSV1_M : E800_PF0INT_OICR_HLP_RSV1_M)
+#define E800_PF0INT_OICR_HLP_RSV1_M MAKEMASK(0xFF, 2)
+#define E830_PF0INT_OICR_HLP_RSV1_M MAKEMASK(0x3F, 2)
+#define E800_PF0INT_OICR_HLP_HH_COMP_S 10
+#define E800_PF0INT_OICR_HLP_HH_COMP_M BIT(10)
#define PF0INT_OICR_HLP_TSYN_TX_S 11
#define PF0INT_OICR_HLP_TSYN_TX_M BIT(11)
#define PF0INT_OICR_HLP_TSYN_EVNT_S 12
@@ -4745,9 +4757,11 @@
#define PF0INT_OICR_PSM_QUEUE_S 1
#define PF0INT_OICR_PSM_QUEUE_M BIT(1)
#define PF0INT_OICR_PSM_RSV1_S 2
-#define PF0INT_OICR_PSM_RSV1_M MAKEMASK(0xFF, 2)
-#define PF0INT_OICR_PSM_HH_COMP_S 10
-#define PF0INT_OICR_PSM_HH_COMP_M BIT(10)
+#define PF0INT_OICR_PSM_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_PSM_RSV1_M : E800_PF0INT_OICR_PSM_RSV1_M)
+#define E800_PF0INT_OICR_PSM_RSV1_M MAKEMASK(0xFF, 2)
+#define E830_PF0INT_OICR_PSM_RSV1_M MAKEMASK(0x3F, 2)
+#define E800_PF0INT_OICR_PSM_HH_COMP_S 10
+#define E800_PF0INT_OICR_PSM_HH_COMP_M BIT(10)
#define PF0INT_OICR_PSM_TSYN_TX_S 11
#define PF0INT_OICR_PSM_TSYN_TX_M BIT(11)
#define PF0INT_OICR_PSM_TSYN_EVNT_S 12
@@ -4868,9 +4882,11 @@
#define PFINT_OICR_QUEUE_S 1
#define PFINT_OICR_QUEUE_M BIT(1)
#define PFINT_OICR_RSV1_S 2
-#define PFINT_OICR_RSV1_M MAKEMASK(0xFF, 2)
-#define PFINT_OICR_HH_COMP_S 10
-#define PFINT_OICR_HH_COMP_M BIT(10)
+#define PFINT_OICR_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFINT_OICR_RSV1_M : E800_PFINT_OICR_RSV1_M)
+#define E800_PFINT_OICR_RSV1_M MAKEMASK(0xFF, 2)
+#define E830_PFINT_OICR_RSV1_M MAKEMASK(0x3F, 2)
+#define E800_PFINT_OICR_HH_COMP_S 10
+#define E800_PFINT_OICR_HH_COMP_M BIT(10)
#define PFINT_OICR_TSYN_TX_S 11
#define PFINT_OICR_TSYN_TX_M BIT(11)
#define PFINT_OICR_TSYN_EVNT_S 12
@@ -4936,7 +4952,9 @@
#define PFINT_SB_CTL_INTEVENT_M BIT(31)
#define PFINT_TSYN_MSK 0x0016C980 /* Reset Source: CORER */
#define PFINT_TSYN_MSK_PHY_INDX_S 0
-#define PFINT_TSYN_MSK_PHY_INDX_M MAKEMASK(0x1F, 0)
+#define PFINT_TSYN_MSK_PHY_INDX_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFINT_TSYN_MSK_PHY_INDX_M : E800_PFINT_TSYN_MSK_PHY_INDX_M)
+#define E800_PFINT_TSYN_MSK_PHY_INDX_M MAKEMASK(0x1F, 0)
+#define E830_PFINT_TSYN_MSK_PHY_INDX_M MAKEMASK(0xFF, 0)
#define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
#define QINT_RQCTL_MAX_INDEX 2047
#define QINT_RQCTL_MSIX_INDX_S 0
@@ -5443,7 +5461,9 @@
#define GL_FWRESETCNT 0x00083100 /* Reset Source: POR */
#define GL_FWRESETCNT_FWRESETCNT_S 0
#define GL_FWRESETCNT_FWRESETCNT_M MAKEMASK(0xFFFFFFFF, 0)
-#define GL_MNG_FW_RAM_STAT 0x0008309C /* Reset Source: POR */
+#define GL_MNG_FW_RAM_STAT_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_FW_RAM_STAT : E800_GL_MNG_FW_RAM_STAT)
+#define E800_GL_MNG_FW_RAM_STAT 0x0008309C /* Reset Source: POR */
+#define E830_GL_MNG_FW_RAM_STAT 0x000830F4 /* Reset Source: POR */
#define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_S 0
#define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_M BIT(0)
#define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_S 1