diff mbox series

[V2] test_plans/nic_single_core&pmd: modify test plan to adapt meson build

Message ID 20220429053703.2248656-1-yingyax.han@intel.com (mailing list archive)
State Accepted
Headers
Series [V2] test_plans/nic_single_core&pmd: modify test plan to adapt meson build |

Checks

Context Check Description
ci/Intel-dts-format-test fail Testing issues
ci/Intel-dts-pylama-test fail Testing issues
ci/Intel-dts-doc-test success Testing OK
ci/Intel-dts-suite-test warning SKIPPED

Commit Message

Yingya Han April 29, 2022, 5:37 a.m. UTC 
Signed-off-by: hanyingya <yingyax.han@intel.com>
---
 test_plans/nic_single_core_perf_test_plan.rst | 11 ++++++-----
 test_plans/pmd_test_plan.rst                  |  9 +++++----
 2 files changed, 11 insertions(+), 9 deletions(-)

Comments

Tu, Lijuan May 5, 2022, 6:06 a.m. UTC | #1 
On Fri, 29 Apr 2022 13:37:03 +0800, hanyingya <yingyax.han@intel.com> wrote:
> Signed-off-by: hanyingya <yingyax.han@intel.com>

Reviewed-by: Lijuan Tu <lijuan.tu@intel.com>
Applied, thanks
diff mbox series

Patch

diff --git a/test_plans/nic_single_core_perf_test_plan.rst b/test_plans/nic_single_core_perf_test_plan.rst
index 7f86312f..459ad87f 100644
--- a/test_plans/nic_single_core_perf_test_plan.rst
+++ b/test_plans/nic_single_core_perf_test_plan.rst
@@ -64,12 +64,13 @@  Prerequisites
     4 TG 10g ports for 4 NNT10G ports
 
 4. Case config::
-    For FVL40g, if test 16 Byte Descriptor, need to set the "CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=y"
-    in ./config/common_base and re-build DPDK.
 
-    For CVL25G, if test 16 Byte Descriptor, need to set the "CONFIG_RTE_LIBRTE_ICE_16BYTE_RX_DESC=y"
-    in ./config/common_base and re-build DPDK.
-    
+    For FVL40g, if test 16 Byte Descriptor, need to be configured with the
+    "-Dc_args=-DRTE_LIBRTE_I40E_16BYTE_RX_DESC" option at compile time.
+
+    For CVL25G, if test 16 Byte Descriptor, need to be configured with the
+    "-Dc_args=-DRTE_LIBRTE_ICE_16BYTE_RX_DESC" option at compile time.
+
 Test Case : Single Core Performance Measurement
 ===============================================
 1) Bind tested ports to igb_uio
diff --git a/test_plans/pmd_test_plan.rst b/test_plans/pmd_test_plan.rst
index 7b7d994f..88671419 100644
--- a/test_plans/pmd_test_plan.rst
+++ b/test_plans/pmd_test_plan.rst
@@ -81,11 +81,12 @@  If using igb_uio::
    usertools/dpdk-devbind.py --bind=igb_uio device_bus_id
 
 Case config::
-   For FVL40g, if test 16 Byte Descriptor, need to set the "CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=y"
-   in ./config/common_base and re-build DPDK.
 
-   For CVL25G, if test 16 Byte Descriptor, need to set the "CONFIG_RTE_LIBRTE_ICE_16BYTE_RX_DESC=y"
-   in ./config/common_base and re-build DPDK.
+   For FVL40g, if test 16 Byte Descriptor, need to be configured with the
+   "-Dc_args=-DRTE_LIBRTE_I40E_16BYTE_RX_DESC" option at compile time.
+
+   For CVL25G, if test 16 Byte Descriptor, need to be configured with the
+   "-Dc_args=-DRTE_LIBRTE_ICE_16BYTE_RX_DESC" option at compile time.
 
 Test Case: Packet Checking
 ==========================