[V1] tests/perf_test_base: add the correct corelist
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ci/Intel-dts-suite-test |
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SKIPPED
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Commit Message
Signed-off-by: Yingya Han <yingyax.han@intel.com>
---
tests/perf_test_base.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
> -----Original Message-----
> From: Yingya Han <yingyax.han@intel.com>
> Sent: Friday, May 20, 2022 9:52 AM
> To: dts@dpdk.org
> Cc: Han, YingyaX <yingyax.han@intel.com>
> Subject: [dts][PATCH V1]tests/perf_test_base: add the correct corelist
>
> Signed-off-by: Yingya Han <yingyax.han@intel.com>
> ---
Tested-by: Yu Jiang <YuX.Jiang@intel.com>
@@ -1366,7 +1366,7 @@ class PerfTestBase(object):
configs.append(
[
test_item,
- _corelist,
+ corelist,
",".join(
[
"({0},{1},{2})".format(port, queue, core)