[V1] tests/perf_test_base: add the correct corelist

Message ID 20220520015215.3385269-1-yingyax.han@intel.com (mailing list archive)
State Changes Requested
Headers
Series [V1] tests/perf_test_base: add the correct corelist |

Checks

Context Check Description
ci/Intel-dts-suite-test warning SKIPPED

Commit Message

Yingya Han May 20, 2022, 1:52 a.m. UTC
Signed-off-by: Yingya Han <yingyax.han@intel.com>
---
 tests/perf_test_base.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
  

Comments

Jiang, YuX May 25, 2022, 10:27 a.m. UTC | #1
> -----Original Message-----
> From: Yingya Han <yingyax.han@intel.com>
> Sent: Friday, May 20, 2022 9:52 AM
> To: dts@dpdk.org
> Cc: Han, YingyaX <yingyax.han@intel.com>
> Subject: [dts][PATCH V1]tests/perf_test_base: add the correct corelist
> 
> Signed-off-by: Yingya Han <yingyax.han@intel.com>
> ---
Tested-by: Yu Jiang <YuX.Jiang@intel.com>
  

Patch

diff --git a/tests/perf_test_base.py b/tests/perf_test_base.py
index d60572e0..74a2a37e 100644
--- a/tests/perf_test_base.py
+++ b/tests/perf_test_base.py
@@ -1366,7 +1366,7 @@  class PerfTestBase(object):
                     configs.append(
                         [
                             test_item,
-                            _corelist,
+                            corelist,
                             ",".join(
                                 [
                                     "({0},{1},{2})".format(port, queue, core)