From patchwork Fri Jan 8 08:25:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ruifeng Wang X-Patchwork-Id: 86183 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DEC23A0524; Fri, 8 Jan 2021 09:26:19 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC1A6140E55; Fri, 8 Jan 2021 09:26:19 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id C376B140DA0 for ; Fri, 8 Jan 2021 09:26:17 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4E4D331B; Fri, 8 Jan 2021 00:26:17 -0800 (PST) Received: from net-arm-n1amp-01.shanghai.arm.com (net-arm-n1amp-01.shanghai.arm.com [10.169.208.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 44D8D3F70D; Fri, 8 Jan 2021 00:26:14 -0800 (PST) From: Ruifeng Wang To: Jan Viktorin , Ruifeng Wang , Jerin Jacob , Bruce Richardson , Vladimir Medvedkin Cc: dev@dpdk.org, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com Date: Fri, 8 Jan 2021 08:25:19 +0000 Message-Id: <20210108082523.1062058-2-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210108082523.1062058-1-ruifeng.wang@arm.com> References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210108082523.1062058-1-ruifeng.wang@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 1/5] lpm: add sve support for lookup on Arm platform X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added new path to do lpm4 lookup by using scalable vector extension. The SVE path will be selected if compiler has flag SVE set. Signed-off-by: Ruifeng Wang Acked-by: Vladimir Medvedkin --- lib/librte_eal/arm/include/rte_vect.h | 3 + lib/librte_lpm/meson.build | 2 +- lib/librte_lpm/rte_lpm.h | 4 ++ lib/librte_lpm/rte_lpm_sve.h | 83 +++++++++++++++++++++++++++ 4 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 lib/librte_lpm/rte_lpm_sve.h diff --git a/lib/librte_eal/arm/include/rte_vect.h b/lib/librte_eal/arm/include/rte_vect.h index a739e6e66..093e9122a 100644 --- a/lib/librte_eal/arm/include/rte_vect.h +++ b/lib/librte_eal/arm/include/rte_vect.h @@ -9,6 +9,9 @@ #include "generic/rte_vect.h" #include "rte_debug.h" #include "arm_neon.h" +#ifdef __ARM_FEATURE_SVE +#include +#endif #ifdef __cplusplus extern "C" { diff --git a/lib/librte_lpm/meson.build b/lib/librte_lpm/meson.build index 6cfc083c5..f93c86640 100644 --- a/lib/librte_lpm/meson.build +++ b/lib/librte_lpm/meson.build @@ -5,6 +5,6 @@ sources = files('rte_lpm.c', 'rte_lpm6.c') headers = files('rte_lpm.h', 'rte_lpm6.h') # since header files have different names, we can install all vector headers # without worrying about which architecture we actually need -headers += files('rte_lpm_altivec.h', 'rte_lpm_neon.h', 'rte_lpm_sse.h') +headers += files('rte_lpm_altivec.h', 'rte_lpm_neon.h', 'rte_lpm_sse.h', 'rte_lpm_sve.h') deps += ['hash'] deps += ['rcu'] diff --git a/lib/librte_lpm/rte_lpm.h b/lib/librte_lpm/rte_lpm.h index 1afe55cdc..28b57683b 100644 --- a/lib/librte_lpm/rte_lpm.h +++ b/lib/librte_lpm/rte_lpm.h @@ -402,7 +402,11 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv); #if defined(RTE_ARCH_ARM) +#ifdef __ARM_FEATURE_SVE +#include "rte_lpm_sve.h" +#else #include "rte_lpm_neon.h" +#endif #elif defined(RTE_ARCH_PPC_64) #include "rte_lpm_altivec.h" #else diff --git a/lib/librte_lpm/rte_lpm_sve.h b/lib/librte_lpm/rte_lpm_sve.h new file mode 100644 index 000000000..2e319373e --- /dev/null +++ b/lib/librte_lpm/rte_lpm_sve.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2020 Arm Limited + */ + +#ifndef _RTE_LPM_SVE_H_ +#define _RTE_LPM_SVE_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +__rte_internal +static void +__rte_lpm_lookup_vec(const struct rte_lpm *lpm, const uint32_t *ips, + uint32_t *__rte_restrict next_hops, const uint32_t n) +{ + uint32_t i = 0; + svuint32_t v_ip, v_idx, v_tbl24, v_tbl8, v_hop; + svuint32_t v_mask_xv, v_mask_v, v_mask_hop; + svbool_t pg = svwhilelt_b32(i, n); + svbool_t pv; + + do { + v_ip = svld1(pg, &ips[i]); + /* Get indices for tbl24[] */ + v_idx = svlsr_x(pg, v_ip, 8); + /* Extract values from tbl24[] */ + v_tbl24 = svld1_gather_index(pg, (const uint32_t *)lpm->tbl24, + v_idx); + + /* Create mask with valid set */ + v_mask_v = svdup_u32_z(pg, RTE_LPM_LOOKUP_SUCCESS); + /* Create mask with valid and valid_group set */ + v_mask_xv = svdup_u32_z(pg, RTE_LPM_VALID_EXT_ENTRY_BITMASK); + /* Create predicate for tbl24 entries: (valid && !valid_group) */ + pv = svcmpeq(pg, svand_z(pg, v_tbl24, v_mask_xv), v_mask_v); + /* Create mask for next_hop in table entry */ + v_mask_hop = svdup_u32_z(pg, 0x00ffffff); + /* Extract next_hop and write back */ + v_hop = svand_x(pv, v_tbl24, v_mask_hop); + svst1(pv, &next_hops[i], v_hop); + + /* Update predicate for tbl24 entries: (valid && valid_group) */ + pv = svcmpeq(pg, svand_z(pg, v_tbl24, v_mask_xv), v_mask_xv); + /* Compute tbl8 index */ + v_idx = svand_x(pv, v_tbl24, svdup_u32_z(pv, 0xffffff)); + v_idx = svmul_x(pv, v_idx, RTE_LPM_TBL8_GROUP_NUM_ENTRIES); + v_idx = svadd_x(pv, svand_x(pv, v_ip, svdup_u32_z(pv, 0xff)), + v_idx); + /* Extract values from tbl8[] */ + v_tbl8 = svld1_gather_index(pv, (const uint32_t *)lpm->tbl8, + v_idx); + /* Update predicate for tbl8 entries: (valid) */ + pv = svcmpeq(pv, svand_z(pv, v_tbl8, v_mask_v), v_mask_v); + /* Extract next_hop and write back */ + v_hop = svand_x(pv, v_tbl8, v_mask_hop); + svst1(pv, &next_hops[i], v_hop); + + i += svlen(v_ip); + pg = svwhilelt_b32(i, n); + } while (svptest_any(svptrue_b32(), pg)); +} + +static inline void +rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], + uint32_t defv) +{ + uint32_t i, ips[4]; + + vst1q_s32((int32_t *)ips, ip); + for (i = 0; i < 4; i++) + hop[i] = defv; + + __rte_lpm_lookup_vec(lpm, ips, hop, 4); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_LPM_SVE_H_ */ From patchwork Fri Jan 8 08:25:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ruifeng Wang X-Patchwork-Id: 86184 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 31D73A0524; Fri, 8 Jan 2021 09:26:29 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1C1A2140E58; Fri, 8 Jan 2021 09:26:29 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 5B2FB140DA0; Fri, 8 Jan 2021 09:26:27 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D3817ED1; Fri, 8 Jan 2021 00:26:26 -0800 (PST) Received: from net-arm-n1amp-01.shanghai.arm.com (net-arm-n1amp-01.shanghai.arm.com [10.169.208.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 23B643F70D; Fri, 8 Jan 2021 00:26:21 -0800 (PST) From: Ruifeng Wang To: "Wei Hu (Xavier)" , "Min Hu (Connor)" , Yisen Zhuang , Lijun Ou , Huisong Li , Chengchang Tang , Chengwen Feng Cc: dev@dpdk.org, vladimir.medvedkin@intel.com, jerinj@marvell.com, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com, Ruifeng Wang , stable@dpdk.org Date: Fri, 8 Jan 2021 08:25:20 +0000 Message-Id: <20210108082523.1062058-3-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210108082523.1062058-1-ruifeng.wang@arm.com> References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210108082523.1062058-1-ruifeng.wang@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 2/5] net/hns3: fix build with sve enabled X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Building with SVE extension enabled stopped with error: error: ACLE function ‘svwhilelt_b64_s32’ requires ISA extension ‘sve’ 18 | #define PG64_256BIT svwhilelt_b64(0, 4) This is caused by unintentional cflags reset. Fixed the issue by appending required flag to cflags instead of overriding it. Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") Cc: xavier.huwei@huawei.com Cc: stable@dpdk.org Signed-off-by: Ruifeng Wang --- drivers/net/hns3/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build index 45cee34d9..798086357 100644 --- a/drivers/net/hns3/meson.build +++ b/drivers/net/hns3/meson.build @@ -32,7 +32,7 @@ deps += ['hash'] if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') sources += files('hns3_rxtx_vec.c') if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' - cflags = ['-DCC_SVE_SUPPORT'] + cflags += ['-DCC_SVE_SUPPORT'] sources += files('hns3_rxtx_vec_sve.c') endif endif From patchwork Fri Jan 8 08:25:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ruifeng Wang X-Patchwork-Id: 86185 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 11FC1A0524; Fri, 8 Jan 2021 09:26:38 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8D2E6140EA4; Fri, 8 Jan 2021 09:26:35 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 7E88A140E53; Fri, 8 Jan 2021 09:26:34 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 039D031B; Fri, 8 Jan 2021 00:26:34 -0800 (PST) Received: from net-arm-n1amp-01.shanghai.arm.com (net-arm-n1amp-01.shanghai.arm.com [10.169.208.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6A35F3F70D; Fri, 8 Jan 2021 00:26:30 -0800 (PST) From: Ruifeng Wang To: Harman Kalra , Jerin Jacob , Santosh Shukla Cc: dev@dpdk.org, vladimir.medvedkin@intel.com, jerinj@marvell.com, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com, Ruifeng Wang , stable@dpdk.org Date: Fri, 8 Jan 2021 08:25:21 +0000 Message-Id: <20210108082523.1062058-4-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210108082523.1062058-1-ruifeng.wang@arm.com> References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210108082523.1062058-1-ruifeng.wang@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 3/5] net/octeontx: fix build with sve enabled X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Building with gcc 10.2 with SVE extension enabled got error: {standard input}: Assembler messages: {standard input}:91: Error: selected processor does not support `addvl x4,x8,#-1' {standard input}:95: Error: selected processor does not support `ptrue p1.d,all' {standard input}:135: Error: selected processor does not support `whilelo p2.d,xzr,x5' {standard input}:137: Error: selected processor does not support `decb x1' This is because inline assembly code explicitly resets cpu model to not have SVE support. Thus SVE instructions generated by compiler auto vectorization got rejected by assembler. Fixed the issue by replacing inline assembly with equivalent atomic built-ins. Compiler will generate LSE instructions for cpu that has the extension. Fixes: f0c7bb1bf778 ("net/octeontx/base: add octeontx IO operations") Cc: jerinj@marvell.com Cc: stable@dpdk.org Signed-off-by: Ruifeng Wang --- drivers/net/octeontx/base/octeontx_io.h | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/net/octeontx/base/octeontx_io.h b/drivers/net/octeontx/base/octeontx_io.h index 04b9ce191..0bf9b100d 100644 --- a/drivers/net/octeontx/base/octeontx_io.h +++ b/drivers/net/octeontx/base/octeontx_io.h @@ -58,14 +58,8 @@ do { \ static inline uint64_t octeontx_reg_ldadd_u64(void *addr, int64_t off) { - uint64_t old_val; - - __asm__ volatile( - " .cpu generic+lse\n" - " ldadd %1, %0, [%2]\n" - : "=r" (old_val) : "r" (off), "r" (addr) : "memory"); - - return old_val; + return (uint64_t)__atomic_fetch_add((int64_t *)addr, off, + __ATOMIC_RELAXED); } /** @@ -97,10 +91,8 @@ octeontx_reg_lmtst(void *lmtline_va, void *ioreg_va, const uint64_t cmdbuf[], } /* LDEOR initiates atomic transfer to I/O device */ - __asm__ volatile( - " .cpu generic+lse\n" - " ldeor xzr, %0, [%1]\n" - : "=r" (result) : "r" (ioreg_va) : "memory"); + result = __atomic_fetch_xor((uint64_t *)ioreg_va, 0, + __ATOMIC_RELAXED); } while (!result); } From patchwork Fri Jan 8 08:25:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ruifeng Wang X-Patchwork-Id: 86186 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A80D9A0524; Fri, 8 Jan 2021 09:26:49 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D9454140EB0; Fri, 8 Jan 2021 09:26:40 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id D1754140E53; Fri, 8 Jan 2021 09:26:39 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5701C31B; Fri, 8 Jan 2021 00:26:39 -0800 (PST) Received: from net-arm-n1amp-01.shanghai.arm.com (net-arm-n1amp-01.shanghai.arm.com [10.169.208.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0C0713F70D; Fri, 8 Jan 2021 00:26:35 -0800 (PST) From: Ruifeng Wang To: Jerin Jacob , Nithin Dabilpuram , Pavan Nikhilesh Cc: dev@dpdk.org, vladimir.medvedkin@intel.com, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com, Ruifeng Wang , stable@dpdk.org Date: Fri, 8 Jan 2021 08:25:22 +0000 Message-Id: <20210108082523.1062058-5-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210108082523.1062058-1-ruifeng.wang@arm.com> References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210108082523.1062058-1-ruifeng.wang@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 4/5] common/octeontx2: fix build with sve enabled X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Building with gcc 10.2 with SVE extension enabled got error: {standard input}: Assembler messages: {standard input}:4002: Error: selected processor does not support `mov z3.b,#0' {standard input}:4003: Error: selected processor does not support `whilelo p1.b,xzr,x7' {standard input}:4005: Error: selected processor does not support `ld1b z0.b,p1/z,[x8]' {standard input}:4006: Error: selected processor does not support `whilelo p4.s,wzr,w7' This is because inline assembly code explicitly resets cpu model to not have SVE support. Thus SVE instructions generated by compiler auto vectorization got rejected by assembler. Fixed the issue by replacing inline assembly with equivalent atomic built-ins. Compiler will generate LSE instructions for cpu that has the extension. Fixes: 8a4f835971f5 ("common/octeontx2: add IO handling APIs") Cc: jerinj@marvell.com Cc: stable@dpdk.org Signed-off-by: Ruifeng Wang --- drivers/common/octeontx2/otx2_io_arm64.h | 37 +++--------------------- 1 file changed, 4 insertions(+), 33 deletions(-) diff --git a/drivers/common/octeontx2/otx2_io_arm64.h b/drivers/common/octeontx2/otx2_io_arm64.h index b5c85d9a6..8843a79b5 100644 --- a/drivers/common/octeontx2/otx2_io_arm64.h +++ b/drivers/common/octeontx2/otx2_io_arm64.h @@ -24,55 +24,26 @@ static __rte_always_inline uint64_t otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr) { - uint64_t result; - /* Atomic add with no ordering */ - asm volatile ( - ".cpu generic+lse\n" - "ldadd %x[i], %x[r], [%[b]]" - : [r] "=r" (result), "+m" (*ptr) - : [i] "r" (incr), [b] "r" (ptr) - : "memory"); - return result; + return (uint64_t)__atomic_fetch_add(ptr, incr, __ATOMIC_RELAXED); } static __rte_always_inline uint64_t otx2_atomic64_add_sync(int64_t incr, int64_t *ptr) { - uint64_t result; - - /* Atomic add with ordering */ - asm volatile ( - ".cpu generic+lse\n" - "ldadda %x[i], %x[r], [%[b]]" - : [r] "=r" (result), "+m" (*ptr) - : [i] "r" (incr), [b] "r" (ptr) - : "memory"); - return result; + return (uint64_t)__atomic_fetch_add(ptr, incr, __ATOMIC_ACQUIRE); } static __rte_always_inline uint64_t otx2_lmt_submit(rte_iova_t io_address) { - uint64_t result; - - asm volatile ( - ".cpu generic+lse\n" - "ldeor xzr,%x[rf],[%[rs]]" : - [rf] "=r"(result): [rs] "r"(io_address)); - return result; + return __atomic_fetch_xor((uint64_t *)io_address, 0, __ATOMIC_RELAXED); } static __rte_always_inline uint64_t otx2_lmt_submit_release(rte_iova_t io_address) { - uint64_t result; - - asm volatile ( - ".cpu generic+lse\n" - "ldeorl xzr,%x[rf],[%[rs]]" : - [rf] "=r"(result) : [rs] "r"(io_address)); - return result; + return __atomic_fetch_xor((uint64_t *)io_address, 0, __ATOMIC_RELEASE); } static __rte_always_inline void From patchwork Fri Jan 8 08:25:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ruifeng Wang X-Patchwork-Id: 86187 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1D28BA0524; Fri, 8 Jan 2021 09:27:01 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6F797140EA2; Fri, 8 Jan 2021 09:26:47 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 358A4140E53 for ; Fri, 8 Jan 2021 09:26:46 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BC34BED1; Fri, 8 Jan 2021 00:26:45 -0800 (PST) Received: from net-arm-n1amp-01.shanghai.arm.com (net-arm-n1amp-01.shanghai.arm.com [10.169.208.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B43AC3F70D; Fri, 8 Jan 2021 00:26:42 -0800 (PST) From: Ruifeng Wang To: Jerin Jacob , Ruifeng Wang , Jan Viktorin , Bruce Richardson Cc: dev@dpdk.org, vladimir.medvedkin@intel.com, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com Date: Fri, 8 Jan 2021 08:25:23 +0000 Message-Id: <20210108082523.1062058-6-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210108082523.1062058-1-ruifeng.wang@arm.com> References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210108082523.1062058-1-ruifeng.wang@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 5/5] config: add Arm Neoverse N2 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add Arm Neoverse N2 cpu support. Signed-off-by: Ruifeng Wang --- config/arm/arm64_n2_linux_gcc | 17 +++++++++++++++++ config/arm/meson.build | 11 ++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 config/arm/arm64_n2_linux_gcc diff --git a/config/arm/arm64_n2_linux_gcc b/config/arm/arm64_n2_linux_gcc new file mode 100644 index 000000000..78f6f3e2b --- /dev/null +++ b/config/arm/arm64_n2_linux_gcc @@ -0,0 +1,17 @@ +[binaries] +c = 'aarch64-linux-gnu-gcc' +cpp = 'aarch64-linux-gnu-cpp' +ar = 'aarch64-linux-gnu-gcc-ar' +strip = 'aarch64-linux-gnu-strip' +pkgconfig = 'aarch64-linux-gnu-pkg-config' +pcap-config = '' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8-a' +endian = 'little' + +[properties] +implementor_id = '0x41' +implementor_pn = '0xd49' diff --git a/config/arm/meson.build b/config/arm/meson.build index 42b4e43c7..58e0ae643 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -89,6 +89,14 @@ flags_n1generic_extra = [ ['RTE_MAX_NUMA_NODES', 1], ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false], ['RTE_LIBRTE_VHOST_NUMA', false]] +flags_n2generic_extra = [ + ['RTE_MACHINE', '"neoverse-n2"'], + ['RTE_MAX_LCORE', 64], + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_ARM_FEATURE_ATOMICS', true], + ['RTE_USE_C11_MEM_MODEL', true], + ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false], + ['RTE_LIBRTE_VHOST_NUMA', false]] machine_args_generic = [ ['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@ -100,7 +108,8 @@ machine_args_generic = [ ['0xd09', ['-mcpu=cortex-a73']], ['0xd0a', ['-mcpu=cortex-a75']], ['0xd0b', ['-mcpu=cortex-a76']], - ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_n1generic_extra]] + ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_n1generic_extra], + ['0xd49', ['-march=armv8.5-a+crypto+sve'], flags_n2generic_extra]] machine_args_cavium = [ ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],