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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT060.mail.protection.outlook.com (10.13.177.211) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4352.24 via Frontend Transport; Tue, 20 Jul 2021 15:38:38 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Jul 2021 15:38:35 +0000 From: Gregory Etelson To: CC: , , Viacheslav Ovsiienko , Matan Azrad , Shahaf Shuler Date: Tue, 20 Jul 2021 18:38:19 +0300 Message-ID: <20210720153819.32496-1-getelson@nvidia.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9658daad-6d61-4704-429c-08d94b9471e0 X-MS-TrafficTypeDiagnostic: CH0PR12MB5124: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1923; 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CAT:NONE; SFS:(4636009)(346002)(136003)(396003)(376002)(39860400002)(46966006)(36840700001)(82740400003)(47076005)(83380400001)(186003)(36756003)(26005)(16526019)(478600001)(82310400003)(356005)(7636003)(36860700001)(1076003)(107886003)(426003)(8676002)(6286002)(7696005)(55016002)(450100002)(4326008)(6666004)(5660300002)(70586007)(70206006)(54906003)(2616005)(336012)(6916009)(86362001)(2906002)(8936002)(316002)(36906005)(21314003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2021 15:38:38.4422 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9658daad-6d61-4704-429c-08d94b9471e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5124 Subject: [dpdk-dev] [PATCH] net/mlx5: fix representor interrupts handler assignment X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In mlx5 PMD the PCI device interrupt vector was used by Uplink representor exclusively and other VF representors did not support interrupt mode. All the VFs and Uplink representors are separate ethernet devices and must have dedicated interrupt vectors. The fix provides each representor with a dedicated interrupt vector. Cc: stable@dpdk.org Fixes: 5882bde88da2 ("net/mlx5: fix representor interrupts handler") Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/linux/mlx5_os.c | 25 +++++++++++++++++++++++++ drivers/net/mlx5/mlx5.c | 5 +++++ drivers/net/mlx5/mlx5_rxq.c | 6 ------ 3 files changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index be22d9cbd2..96e18f9f57 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -2389,6 +2389,31 @@ mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev, } restore = list[i].eth_dev->data->dev_flags; rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); + /** + * Each representor has a dedicated interrupts vector. + * rte_eth_copy_pci_info() assigns PF interrupts handle to + * representor eth_dev object because representor and PF + * share the same PCI address. + * Override representor device with a dedicated + * interrupts handle here. + * Representor interrupts handle is released in mlx5_dev_stop(). + */ + if (list[i].info.representor) { + struct rte_intr_handle *intr_handle; + intr_handle = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, + sizeof(*intr_handle), 0, + SOCKET_ID_ANY); + if (!intr_handle) { + DRV_LOG(ERR, + "port %u failed to allocate memory for interrupt handler " + "Rx interrupts will not be supported", + i); + rte_errno = ENOMEM; + ret = -rte_errno; + goto exit; + } + list[i].eth_dev->intr_handle = intr_handle; + } /* Restore non-PCI flags cleared by the above call. */ list[i].eth_dev->data->dev_flags |= restore; rte_eth_dev_probing_finish(list[i].eth_dev); diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 44fbc2da83..251ae7181d 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1548,6 +1548,11 @@ mlx5_dev_close(struct rte_eth_dev *dev) priv->rxqs_n = 0; priv->rxqs = NULL; } + if (priv->representor) { + /* Each representor has a dedicated interrupts handler */ + mlx5_free(dev->intr_handle); + dev->intr_handle = NULL; + } if (priv->txqs != NULL) { /* XXX race condition if mlx5_tx_burst() is still running. */ rte_delay_us_sleep(1000); diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index bb9a908087..769b8c625d 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -834,9 +834,6 @@ mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev) unsigned int count = 0; struct rte_intr_handle *intr_handle = dev->intr_handle; - /* Representor shares dev->intr_handle with PF. */ - if (priv->representor) - return 0; if (!dev->data->dev_conf.intr_conf.rxq) return 0; mlx5_rx_intr_vec_disable(dev); @@ -917,9 +914,6 @@ mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev) unsigned int rxqs_n = priv->rxqs_n; unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID); - /* Representor shares dev->intr_handle with PF. */ - if (priv->representor) - return; if (!dev->data->dev_conf.intr_conf.rxq) return; if (!intr_handle->intr_vec)