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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.35 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.35; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.35) by CO1NAM11FT049.mail.protection.outlook.com (10.13.175.50) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4478.19 via Frontend Transport; Tue, 31 Aug 2021 20:40:35 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 31 Aug 2021 20:40:35 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 31 Aug 2021 20:40:34 +0000 From: Michael Baum To: CC: Matan Azrad , Date: Tue, 31 Aug 2021 23:40:15 +0300 Message-ID: <20210831204015.3411435-1-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b45fb643-0d24-4d4d-6577-08d96cbf95e6 X-MS-TrafficTypeDiagnostic: DM5PR12MB4680: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2201; 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CAT:NONE; SFS:(4636009)(376002)(39860400002)(136003)(346002)(396003)(36840700001)(46966006)(6666004)(1076003)(16526019)(2906002)(6916009)(54906003)(86362001)(6286002)(70206006)(83380400001)(5660300002)(55016002)(70586007)(36860700001)(336012)(4326008)(47076005)(36756003)(7696005)(26005)(2616005)(426003)(186003)(82740400003)(450100002)(8676002)(356005)(7636003)(8936002)(478600001)(36906005)(316002)(82310400003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2021 20:40:35.7734 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b45fb643-0d24-4d4d-6577-08d96cbf95e6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.35]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB4680 Subject: [dpdk-dev] [PATCH] crypto/mlx5: support timestamp format X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds support for the timestamp format settings for the receive and send queues. If the firmware version x.30.1000 or above is installed and the NIC timestamps are configured with the real-time format, the default zero values for newly added fields cause the queue creation to fail. The patch queries the timestamp formats supported by the hardware and sets the configuration values in queue context accordingly. Fixes: 6152534e211e ("crypto/mlx5: support queue pairs operations") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/crypto/mlx5/mlx5_crypto.c | 2 ++ drivers/crypto/mlx5/mlx5_crypto.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index b3d5200ca3..e01be15ade 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -707,6 +707,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, attr.wq_umem_id = qp->umem_obj->umem_id; attr.wq_umem_offset = 0; attr.dbr_umem_id = qp->umem_obj->umem_id; + attr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format); attr.dbr_address = RTE_BIT64(log_nb_desc) * priv->wqe_set_size; qp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr); if (qp->qp_obj == NULL) { @@ -1049,6 +1050,7 @@ mlx5_crypto_dev_probe(struct rte_device *dev) priv->ctx = ctx; priv->login_obj = login; priv->crypto_dev = crypto_dev; + priv->qp_ts_format = attr.qp_ts_format; if (mlx5_crypto_hw_global_prepare(priv) != 0) { rte_cryptodev_pmd_destroy(priv->crypto_dev); claim_zero(mlx5_glue->close_device(priv->ctx)); diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index d49b0001f0..722acb8d19 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -25,6 +25,7 @@ struct mlx5_crypto_priv { volatile uint64_t *uar_addr; uint32_t pdn; /* Protection Domain number. */ uint32_t max_segs_num; /* Maximum supported data segs. */ + uint8_t qp_ts_format; /* Whether QP supports timestamp formats. */ struct ibv_pd *pd; struct mlx5_hlist *dek_hlist; /* Dek hash list. */ struct rte_cryptodev_config dev_config;