From patchwork Thu Sep 2 07:00:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 97761 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7FC0FA0547; Thu, 2 Sep 2021 09:00:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A3D3340DDE; Thu, 2 Sep 2021 09:00:52 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 76F6E40142 for ; Thu, 2 Sep 2021 09:00:50 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1823lgrH027710; Thu, 2 Sep 2021 00:00:47 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=edI1ULTNqzsAEtAG8EyY0TSiuTDi/E3MRXq4mfaj7N4=; b=Nt2HtPjzTRwlUILNGQPdvcQJQnNeamisUuv7XAQjyUK/2BnlqqsNt33KzQcqDEDXhZTB 5oOCPqhxeUCWa9gUWBanS4BrujjMkTFH2t1j+Luh9/AnOrGuMoTAII88VWHjZe2KdF2S 5jqDYCWAy6KbqplUYGUEAXIEfXG9EZeZSzzLKckRR5Ok5kPHRAYtk1wZHq2foEERXzIP UH4hh9q5MtODx5z8JqfmSaCqHUTjGwukj2EKnH/Dl2UPb2Moo55tev8gQGoV1roMx6w3 pEQcX8kieBRSftlhJUEs7wuDjqP1JhkGIUy0J97Te9cGDOiip+s1R0k2nLGf21KJrC7x 8w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3atdwqae6g-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 02 Sep 2021 00:00:46 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 2 Sep 2021 00:00:44 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 2 Sep 2021 00:00:44 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 525D23F7051; Thu, 2 Sep 2021 00:00:42 -0700 (PDT) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Pavan Nikhilesh Date: Thu, 2 Sep 2021 12:30:32 +0530 Message-ID: <20210902070034.1086-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: LZTp_Ov-dCvo5VGNmQfa3IEqovbrNCl3 X-Proofpoint-GUID: LZTp_Ov-dCvo5VGNmQfa3IEqovbrNCl3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-02_02,2021-09-01_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 1/2] common/cnxk: add SSO XAQ pool create and free X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add common API to create and free SSO XAQ pool. Signed-off-by: Pavan Nikhilesh --- Depends-on: series-18612 ("net/cnxk: support for inline ipsec") drivers/common/cnxk/roc_sso.c | 122 +++++++++++++++++++++++++++++ drivers/common/cnxk/roc_sso.h | 14 ++++ drivers/common/cnxk/roc_sso_priv.h | 5 ++ drivers/common/cnxk/version.map | 2 + 4 files changed, 143 insertions(+) -- 2.32.0 diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index bdf973fc2a..31cae30c88 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -5,6 +5,8 @@ #include "roc_api.h" #include "roc_priv.h" +#define SSO_XAQ_CACHE_CNT (0x7) + /* Private functions. */ int sso_lf_alloc(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf, @@ -387,6 +389,126 @@ roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso, struct roc_sso_hwgrp_qos *qos, return mbox_process(dev->mbox); } +int +sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, + uint32_t nb_xae, uint32_t xae_waes, + uint32_t xaq_buf_size, uint16_t nb_hwgrp) +{ + struct npa_pool_s pool; + struct npa_aura_s aura; + plt_iova_t iova; + uint32_t i; + int rc; + + if (xaq->mem != NULL) { + rc = sso_hwgrp_release_xaq(dev, nb_hwgrp); + if (rc < 0) { + plt_err("Failed to release XAQ %d", rc); + return rc; + } + roc_npa_pool_destroy(xaq->aura_handle); + plt_free(xaq->fc); + plt_free(xaq->mem); + memset(xaq, 0, sizeof(struct roc_sso_xaq_data)); + } + + xaq->fc = plt_zmalloc(ROC_ALIGN, ROC_ALIGN); + if (xaq->fc == NULL) { + plt_err("Failed to allocate XAQ FC"); + rc = -ENOMEM; + goto fail; + } + + /* Taken from HRM 14.3.3(4) */ + nb_xae += (xae_waes * SSO_XAQ_CACHE_CNT * nb_hwgrp); + xaq->nb_xae = nb_xae; + xaq->nb_xaq = xaq->nb_xae / xae_waes; + + xaq->mem = plt_zmalloc(xaq_buf_size * xaq->nb_xaq, xaq_buf_size); + if (xaq->mem == NULL) { + plt_err("Failed to allocate XAQ mem"); + rc = -ENOMEM; + goto free_fc; + } + + memset(&pool, 0, sizeof(struct npa_pool_s)); + pool.nat_align = 1; + + memset(&aura, 0, sizeof(aura)); + aura.fc_ena = 1; + aura.fc_addr = (uint64_t)xaq->fc; + aura.fc_hyst_bits = 0; /* Store count on all updates */ + rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, + &aura, &pool); + if (rc) { + plt_err("Failed to create XAQ pool"); + goto npa_fail; + } + + iova = (uint64_t)xaq->mem; + for (i = 0; i < xaq->nb_xaq; i++) { + roc_npa_aura_op_free(xaq->aura_handle, 0, iova); + iova += xaq_buf_size; + } + roc_npa_aura_op_range_set(xaq->aura_handle, (uint64_t)xaq->mem, iova); + + /* When SW does addwork (enqueue) check if there is space in XAQ by + * comparing fc_addr above against the xaq_lmt calculated below. + * There should be a minimum headroom of one XAQ per HWGRP for SSO + * to request XAQ to cache them even before enqueue is called. + */ + xaq->xaq_lmt = xaq->nb_xaq - nb_hwgrp; + return 0; +npa_fail: + plt_free(xaq->mem); +free_fc: + plt_free(xaq->fc); +fail: + memset(xaq, 0, sizeof(struct roc_sso_xaq_data)); + return rc; +} + +int +roc_sso_hwgrp_init_xaq_aura(struct roc_sso *roc_sso, uint32_t nb_xae) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + + return sso_hwgrp_init_xaq_aura(dev, &roc_sso->xaq, nb_xae, + roc_sso->xae_waes, roc_sso->xaq_buf_size, + roc_sso->nb_hwgrp); +} + +int +sso_hwgrp_free_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, + uint16_t nb_hwgrp) +{ + int rc; + + if (xaq->mem != NULL) { + if (nb_hwgrp) { + rc = sso_hwgrp_release_xaq(dev, nb_hwgrp); + if (rc < 0) { + plt_err("Failed to release XAQ %d", rc); + return rc; + } + } + roc_npa_pool_destroy(xaq->aura_handle); + plt_free(xaq->fc); + plt_free(xaq->mem); + } + memset(xaq, 0, sizeof(struct roc_sso_xaq_data)); + + return 0; +} + +int +roc_sso_hwgrp_free_xaq_aura(struct roc_sso *roc_sso, uint16_t nb_hwgrp) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + + return sso_hwgrp_free_xaq_aura(dev, &roc_sso->xaq, nb_hwgrp); +} + int sso_hwgrp_alloc_xaq(struct dev *dev, uint32_t npa_aura_id, uint16_t hwgrps) { diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index b28f6089cc..27d49c6c68 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -27,6 +27,15 @@ struct roc_sso_hwgrp_stats { uint64_t page_cnt; }; +struct roc_sso_xaq_data { + uint32_t nb_xaq; + uint32_t nb_xae; + uint32_t xaq_lmt; + uint64_t aura_handle; + void *fc; + void *mem; +}; + struct roc_sso { struct plt_pci_device *pci_dev; /* Public data. */ @@ -35,6 +44,7 @@ struct roc_sso { uint16_t nb_hwgrp; uint8_t nb_hws; uintptr_t lmt_base; + struct roc_sso_xaq_data xaq; /* HW Const. */ uint32_t xae_waes; uint32_t xaq_buf_size; @@ -95,6 +105,10 @@ int __roc_api roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso, uintptr_t __roc_api roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws); uintptr_t __roc_api roc_sso_hwgrp_base_get(struct roc_sso *roc_sso, uint16_t hwgrp); +int __roc_api roc_sso_hwgrp_init_xaq_aura(struct roc_sso *roc_sso, + uint32_t nb_xae); +int __roc_api roc_sso_hwgrp_free_xaq_aura(struct roc_sso *roc_sso, + uint16_t nb_hwgrp); /* Debug */ void __roc_api roc_sso_dump(struct roc_sso *roc_sso, uint8_t nb_hws, diff --git a/drivers/common/cnxk/roc_sso_priv.h b/drivers/common/cnxk/roc_sso_priv.h index 8dffa3fbf4..2e1b025d1c 100644 --- a/drivers/common/cnxk/roc_sso_priv.h +++ b/drivers/common/cnxk/roc_sso_priv.h @@ -47,6 +47,11 @@ void sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp, uint16_t hwgrp[], uint16_t n, uint16_t enable); int sso_hwgrp_alloc_xaq(struct dev *dev, uint32_t npa_aura_id, uint16_t hwgrps); int sso_hwgrp_release_xaq(struct dev *dev, uint16_t hwgrps); +int sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, + uint32_t nb_xae, uint32_t xae_waes, + uint32_t xaq_buf_size, uint16_t nb_hwgrp); +int sso_hwgrp_free_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, + uint16_t nb_hwgrp); /* SSO IRQ */ int sso_register_irqs_priv(struct roc_sso *roc_sso, diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 9fcc677e34..153c45b910 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -280,7 +280,9 @@ INTERNAL { roc_sso_dump; roc_sso_hwgrp_alloc_xaq; roc_sso_hwgrp_base_get; + roc_sso_hwgrp_free_xaq_aura; roc_sso_hwgrp_hws_link_status; + roc_sso_hwgrp_init_xaq_aura; roc_sso_hwgrp_qos_config; roc_sso_hwgrp_release_xaq; roc_sso_hwgrp_set_priority; From patchwork Thu Sep 2 07:00:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 97760 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 96938A0547; Thu, 2 Sep 2021 09:00:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 80B1040142; Thu, 2 Sep 2021 09:00:51 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 63E2C4013F for ; Thu, 2 Sep 2021 09:00:50 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1823lgcu027670 for ; Thu, 2 Sep 2021 00:00:49 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=O9iyS2SaeqHlenZa/rEAc7PSbSMy8pFT4aC6U3RLLig=; b=VePFWymHNgm5JNw8MtF8UZT7brrqs8Hn/hYR9pxXOxTA3Pjwa2g1XNatUHpkw6PoKcK6 f/xBY3XdebroSf+en8C/jyZ6PlQQ2Vt+A5a3hzFl1qSGXNOwziUzNLWuQd8nx25W8XXk Xxp0N8T4SZuRmzo2uKCHGTkunNfdWtczxJ6GGut8obadNQe6xRU1c0ROZyq8sGtkh1mo CPmVVYwza3xrp+SUjHsDh25Bzd7RF0dBDjrtuho2CBa3hVhBGR1fOzJQPzRhk5ZJL6zn fx5913D3fD3kUjSK0hO1Fj89mTfYGR1rRwkKIB6JXgRS0cjK2C2ZfUWpQ2rbBTE59KqA yQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3atdwqae6t-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 02 Sep 2021 00:00:49 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 2 Sep 2021 00:00:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 2 Sep 2021 00:00:47 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 31C1E3F7051; Thu, 2 Sep 2021 00:00:45 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Thu, 2 Sep 2021 12:30:33 +0530 Message-ID: <20210902070034.1086-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210902070034.1086-1-pbhagavatula@marvell.com> References: <20210902070034.1086-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: S9OQFb7jNqjSe_p-efrb4293IDoGskqk X-Proofpoint-GUID: S9OQFb7jNqjSe_p-efrb4293IDoGskqk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-02_02,2021-09-01_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 2/2] event/cnxk: use common XAQ pool APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Use the common APIs to create and fre XAQ pool. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 4 +- drivers/event/cnxk/cn9k_eventdev.c | 6 +- drivers/event/cnxk/cnxk_eventdev.c | 127 ++++------------------------ drivers/event/cnxk/cnxk_eventdev.h | 3 - 4 files changed, 21 insertions(+), 119 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index bd1cf55d2c..ed185262d1 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -98,7 +98,7 @@ cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) rte_memcpy(ws->grps_base, grps_base, sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP); - ws->fc_mem = dev->fc_mem; + ws->fc_mem = (uint64_t *)dev->fc_iova; ws->xaq_lmt = dev->xaq_lmt; /* Set get_work timeout for HWS */ @@ -467,8 +467,6 @@ cn10k_sso_dev_configure(const struct rte_eventdev *event_dev) return -EINVAL; } - roc_sso_rsrc_fini(&dev->sso); - rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports, dev->nb_event_queues); if (rc < 0) { diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 0c7206cb96..7a2dbcbe35 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -100,7 +100,7 @@ cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) dws = hws; rte_memcpy(dws->grps_base, grps_base, sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP); - dws->fc_mem = dev->fc_mem; + dws->fc_mem = (uint64_t *)dev->fc_iova; dws->xaq_lmt = dev->xaq_lmt; plt_write64(val, dws->base[0] + SSOW_LF_GWS_NW_TIM); @@ -109,7 +109,7 @@ cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) ws = hws; rte_memcpy(ws->grps_base, grps_base, sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP); - ws->fc_mem = dev->fc_mem; + ws->fc_mem = (uint64_t *)dev->fc_iova; ws->xaq_lmt = dev->xaq_lmt; plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM); @@ -728,8 +728,6 @@ cn9k_sso_dev_configure(const struct rte_eventdev *event_dev) return -EINVAL; } - roc_sso_rsrc_fini(&dev->sso); - rc = cn9k_sso_rsrc_init(dev, dev->nb_event_ports, dev->nb_event_queues); if (rc < 0) { plt_err("Failed to initialize SSO resources"); diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 9a87239a59..84bf8cb6d1 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -125,101 +125,30 @@ cnxk_sso_info_get(struct cnxk_sso_evdev *dev, int cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev) { - char pool_name[RTE_MEMZONE_NAMESIZE]; - uint32_t xaq_cnt, npa_aura_id; - const struct rte_memzone *mz; - struct npa_aura_s *aura; - static int reconfig_cnt; + uint32_t xae_cnt; int rc; - if (dev->xaq_pool) { - rc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues); - if (rc < 0) { - plt_err("Failed to release XAQ %d", rc); - return rc; - } - rte_mempool_free(dev->xaq_pool); - dev->xaq_pool = NULL; - } - - /* - * Allocate memory for Add work backpressure. - */ - mz = rte_memzone_lookup(CNXK_SSO_FC_NAME); - if (mz == NULL) - mz = rte_memzone_reserve_aligned(CNXK_SSO_FC_NAME, - sizeof(struct npa_aura_s) + - RTE_CACHE_LINE_SIZE, - 0, 0, RTE_CACHE_LINE_SIZE); - if (mz == NULL) { - plt_err("Failed to allocate mem for fcmem"); - return -ENOMEM; - } - - dev->fc_iova = mz->iova; - dev->fc_mem = mz->addr; - - aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + - RTE_CACHE_LINE_SIZE); - memset(aura, 0, sizeof(struct npa_aura_s)); - - aura->fc_ena = 1; - aura->fc_addr = dev->fc_iova; - aura->fc_hyst_bits = 0; /* Store count on all updates */ - - /* Taken from HRM 14.3.3(4) */ - xaq_cnt = dev->nb_event_queues * CNXK_SSO_XAQ_CACHE_CNT; + xae_cnt = 0; if (dev->xae_cnt) - xaq_cnt += dev->xae_cnt / dev->sso.xae_waes; + xae_cnt += dev->xae_cnt; else if (dev->adptr_xae_cnt) - xaq_cnt += (dev->adptr_xae_cnt / dev->sso.xae_waes) + - (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues); + xae_cnt += (dev->adptr_xae_cnt); else - xaq_cnt += (dev->sso.iue / dev->sso.xae_waes) + - (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues); - - plt_sso_dbg("Configuring %d xaq buffers", xaq_cnt); - /* Setup XAQ based on number of nb queues. */ - snprintf(pool_name, 30, "cnxk_xaq_buf_pool_%d", reconfig_cnt); - dev->xaq_pool = (void *)rte_mempool_create_empty( - pool_name, xaq_cnt, dev->sso.xaq_buf_size, 0, 0, - rte_socket_id(), 0); - - if (dev->xaq_pool == NULL) { - plt_err("Unable to create empty mempool."); - rte_memzone_free(mz); - return -ENOMEM; - } - - rc = rte_mempool_set_ops_byname(dev->xaq_pool, - rte_mbuf_platform_mempool_ops(), aura); - if (rc != 0) { - plt_err("Unable to set xaqpool ops."); - goto alloc_fail; - } + xae_cnt += dev->sso.iue; - rc = rte_mempool_populate_default(dev->xaq_pool); + plt_sso_dbg("Configuring %d xae buffers", xae_cnt); + rc = roc_sso_hwgrp_init_xaq_aura(&dev->sso, xae_cnt); if (rc < 0) { - plt_err("Unable to set populate xaqpool."); - goto alloc_fail; + plt_err("Failed to configure XAQ aura"); + return rc; } - reconfig_cnt++; - /* When SW does addwork (enqueue) check if there is space in XAQ by - * comparing fc_addr above against the xaq_lmt calculated below. - * There should be a minimum headroom (CNXK_SSO_XAQ_SLACK / 2) for SSO - * to request XAQ to cache them even before enqueue is called. - */ - dev->xaq_lmt = - xaq_cnt - (CNXK_SSO_XAQ_SLACK / 2 * dev->nb_event_queues); - dev->nb_xaq_cfg = xaq_cnt; - - npa_aura_id = roc_npa_aura_handle_to_aura(dev->xaq_pool->pool_id); - return roc_sso_hwgrp_alloc_xaq(&dev->sso, npa_aura_id, - dev->nb_event_queues); -alloc_fail: - rte_mempool_free(dev->xaq_pool); - rte_memzone_free(mz); - return rc; + dev->xaq_lmt = dev->sso.xaq.xaq_lmt; + dev->fc_iova = (uint64_t)dev->sso.xaq.fc; + + return roc_sso_hwgrp_alloc_xaq( + &dev->sso, + roc_npa_aura_handle_to_aura(dev->sso.xaq.aura_handle), + dev->nb_event_queues); } int @@ -231,14 +160,6 @@ cnxk_sso_xae_reconfigure(struct rte_eventdev *event_dev) if (event_dev->data->dev_started) event_dev->dev_ops->dev_stop(event_dev); - rc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues); - if (rc < 0) { - plt_err("Failed to release XAQ %d", rc); - return rc; - } - - rte_mempool_free(dev->xaq_pool); - dev->xaq_pool = NULL; rc = cnxk_sso_xaq_allocate(dev); if (rc < 0) { plt_err("Failed to alloc XAQ %d", rc); @@ -320,7 +241,6 @@ cnxk_sso_dev_validate(const struct rte_eventdev *event_dev) struct rte_event_dev_config *conf = &event_dev->data->dev_conf; struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); uint32_t deq_tmo_ns; - int rc; deq_tmo_ns = conf->dequeue_timeout_ns; @@ -354,15 +274,8 @@ cnxk_sso_dev_validate(const struct rte_eventdev *event_dev) return -EINVAL; } - if (dev->xaq_pool) { - rc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues); - if (rc < 0) { - plt_err("Failed to release XAQ %d", rc); - return rc; - } - rte_mempool_free(dev->xaq_pool); - dev->xaq_pool = NULL; - } + roc_sso_rsrc_fini(&dev->sso); + roc_sso_hwgrp_free_xaq_aura(&dev->sso, dev->sso.nb_hwgrp); dev->nb_event_queues = conf->nb_event_queues; dev->nb_event_ports = conf->nb_event_ports; @@ -556,12 +469,8 @@ cnxk_sso_close(struct rte_eventdev *event_dev, cnxk_sso_unlink_t unlink_fn) } roc_sso_rsrc_fini(&dev->sso); - rte_mempool_free(dev->xaq_pool); - rte_memzone_free(rte_memzone_lookup(CNXK_SSO_FC_NAME)); dev->fc_iova = 0; - dev->fc_mem = NULL; - dev->xaq_pool = NULL; dev->configured = false; dev->is_timeout_deq = 0; dev->nb_event_ports = 0; diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 8a5c737e4b..ccd09b1d82 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -91,11 +91,8 @@ struct cnxk_sso_evdev { uint32_t min_dequeue_timeout_ns; uint32_t max_dequeue_timeout_ns; int32_t max_num_events; - uint64_t *fc_mem; uint64_t xaq_lmt; - uint64_t nb_xaq_cfg; rte_iova_t fc_iova; - struct rte_mempool *xaq_pool; uint64_t rx_offloads; uint64_t tx_offloads; uint64_t adptr_xae_cnt;