From patchwork Fri Sep 17 09:34:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 99096 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 01F37A0C46; Fri, 17 Sep 2021 11:36:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D7610406B4; Fri, 17 Sep 2021 11:36:08 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 6F38C40689 for ; Fri, 17 Sep 2021 11:36:07 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18GNEipd030397 for ; Fri, 17 Sep 2021 02:36:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=vrgTe+Qw2NKf3vNoSImkeomO20cQALzTwH6hocsuL9k=; b=eRJWt87Ic0ghp0cQ15EHpSL+7rw1JAig74DE8xRsi1rziii+DPHRM5RoT/MueJ13uWmp JKedwM2t/rN0X4cy02OymhcMK0xzw9QSKLs+Z8XHqx9+Vz9+3D8YiVQseZ3jdbzMob02 wMaWVnpBsAQIYu+4is34MHpTMaDEUpyWv6vNpcWPxO+6snKTu6Eq8oD4CIaFSZssxI9x 4fblZWNeijc85IOADx+O4tJoRrSEFtfnYY7HTwhfKViTSe2SvhWAHoCmNpRyHP9G9+5v pysGLW76oCuIlZBZaS4kfcmSb3eGWgbpvGukXaIE0/eAdd04AFJMgJRPZ35YAdzUOiY7 ng== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 3b4fe1sks5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 17 Sep 2021 02:36:06 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 17 Sep 2021 02:36:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 17 Sep 2021 02:36:04 -0700 Received: from lab-ci-142.marvell.com (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id 0F2CD3F704E; Fri, 17 Sep 2021 02:36:00 -0700 (PDT) From: Ashwin Sekhar T K To: CC: , , , , , , , , Date: Fri, 17 Sep 2021 15:04:36 +0530 Message-ID: <20210917093437.269363-1-asekhar@marvell.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210830162903.2736191-1-asekhar@marvell.com> References: <20210830162903.2736191-1-asekhar@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: -zrRQEokifi919FwwORBJkhsRcqUanMW X-Proofpoint-ORIG-GUID: -zrRQEokifi919FwwORBJkhsRcqUanMW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-17_04,2021-09-16_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 1/2] common/cnxk: update roc models X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Make following updates to roc models. - Use consistent upper/lower case in macros defining different ROC models. - Add api to detect cn96 Cx stepping. - Make all current cn10k models as A0 stepping. Signed-off-by: Ashwin Sekhar T K --- drivers/common/cnxk/roc_model.c | 51 +++++++++++++++---------------- drivers/common/cnxk/roc_model.h | 53 +++++++++++++++++++++++++-------- 2 files changed, 67 insertions(+), 37 deletions(-) diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c index bc255b53cc..e5aeabe2e2 100644 --- a/drivers/common/cnxk/roc_model.c +++ b/drivers/common/cnxk/roc_model.c @@ -13,14 +13,14 @@ struct roc_model *roc_model; #define SOC_PART_CN10K 0xD49 -#define PART_106XX 0xB9 -#define PART_105XX 0xBA -#define PART_105XXN 0xBC -#define PART_98XX 0xB1 -#define PART_96XX 0xB2 -#define PART_95XX 0xB3 -#define PART_95XXN 0xB4 -#define PART_95XXMM 0xB5 +#define PART_106xx 0xB9 +#define PART_105xx 0xBA +#define PART_105xxN 0xBC +#define PART_98xx 0xB1 +#define PART_96xx 0xB2 +#define PART_95xx 0xB3 +#define PART_95xxN 0xB4 +#define PART_95xxMM 0xB5 #define PART_95O 0xB6 #define MODEL_IMPL_BITS 8 @@ -44,20 +44,21 @@ static const struct model_db { uint64_t flag; char name[ROC_MODEL_STR_LEN_MAX]; } model_db[] = { - {VENDOR_ARM, PART_106XX, 0, 0, ROC_MODEL_CN106XX, "cn10ka"}, - {VENDOR_ARM, PART_105XX, 0, 0, ROC_MODEL_CNF105XX, "cnf10ka"}, - {VENDOR_ARM, PART_105XXN, 0, 0, ROC_MODEL_CNF105XXN, "cnf10kb"}, - {VENDOR_CAVIUM, PART_98XX, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"}, - {VENDOR_CAVIUM, PART_96XX, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"}, - {VENDOR_CAVIUM, PART_96XX, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"}, - {VENDOR_CAVIUM, PART_96XX, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"}, - {VENDOR_CAVIUM, PART_95XX, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"}, - {VENDOR_CAVIUM, PART_95XX, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"}, - {VENDOR_CAVIUM, PART_95XXN, 0, 0, ROC_MODEL_CNF95XXN_A0, "cnf95xxn_a0"}, - {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95XXO_A0, "cnf95O_a0"}, - {VENDOR_CAVIUM, PART_95XXMM, 0, 0, ROC_MODEL_CNF95XXMM_A0, - "cnf95xxmm_a0"} -}; + {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"}, + {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"}, + {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"}, + {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"}, + {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"}, + {VENDOR_CAVIUM, PART_96xx, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"}, + {VENDOR_CAVIUM, PART_96xx, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"}, + {VENDOR_CAVIUM, PART_96xx, 2, 1, ROC_MODEL_CN96xx_C0, "cn96xx_c1"}, + {VENDOR_CAVIUM, PART_95xx, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"}, + {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"}, + {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"}, + {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"}, + {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"}, + {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0, + "cnf95xxmm_a0"}}; static uint32_t cn10k_part_get(void) @@ -85,11 +86,11 @@ cn10k_part_get(void) } ptr++; if (strcmp("cn10ka", ptr) == 0) { - soc = PART_106XX; + soc = PART_106xx; } else if (strcmp("cnf10ka", ptr) == 0) { - soc = PART_105XX; + soc = PART_105xx; } else if (strcmp("cnf10kb", ptr) == 0) { - soc = PART_105XXN; + soc = PART_105xxN; } else { plt_err("Unidentified 'CPU compatible': <%s>", ptr); goto fclose; diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index c1d11b77c6..a54f435b46 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -15,13 +15,14 @@ struct roc_model { #define ROC_MODEL_CN96xx_C0 BIT_ULL(2) #define ROC_MODEL_CNF95xx_A0 BIT_ULL(4) #define ROC_MODEL_CNF95xx_B0 BIT_ULL(6) -#define ROC_MODEL_CNF95XXMM_A0 BIT_ULL(8) -#define ROC_MODEL_CNF95XXN_A0 BIT_ULL(12) -#define ROC_MODEL_CNF95XXO_A0 BIT_ULL(13) +#define ROC_MODEL_CNF95xxMM_A0 BIT_ULL(8) +#define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12) +#define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13) +#define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14) #define ROC_MODEL_CN98xx_A0 BIT_ULL(16) -#define ROC_MODEL_CN106XX BIT_ULL(20) -#define ROC_MODEL_CNF105XX BIT_ULL(21) -#define ROC_MODEL_CNF105XXN BIT_ULL(22) +#define ROC_MODEL_CN106xx_A0 BIT_ULL(20) +#define ROC_MODEL_CNF105xx_A0 BIT_ULL(21) +#define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22) uint64_t flag; #define ROC_MODEL_STR_LEN_MAX 128 @@ -31,11 +32,15 @@ struct roc_model { #define ROC_MODEL_CN96xx_Ax (ROC_MODEL_CN96xx_A0 | ROC_MODEL_CN96xx_B0) #define ROC_MODEL_CN9K \ (ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \ - ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95XXMM_A0 | \ - ROC_MODEL_CNF95XXO_A0 | ROC_MODEL_CNF95XXN_A0 | ROC_MODEL_CN98xx_A0) + ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \ + ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \ + ROC_MODEL_CNF95xxN_A1) +#define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0) +#define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0) +#define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0) #define ROC_MODEL_CN10K \ - (ROC_MODEL_CN106XX | ROC_MODEL_CNF105XX | ROC_MODEL_CNF105XXN) + (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN) /* Runtime variants */ static inline uint64_t @@ -105,6 +110,12 @@ roc_model_is_cn96_ax(void) return (roc_model->flag & ROC_MODEL_CN96xx_Ax); } +static inline uint64_t +roc_model_is_cn96_cx(void) +{ + return (roc_model->flag & ROC_MODEL_CN96xx_C0); +} + static inline uint64_t roc_model_is_cn95_a0(void) { @@ -114,19 +125,37 @@ roc_model_is_cn95_a0(void) static inline uint64_t roc_model_is_cn10ka(void) { - return roc_model->flag & ROC_MODEL_CN106XX; + return roc_model->flag & ROC_MODEL_CN106xx; } static inline uint64_t roc_model_is_cnf10ka(void) { - return roc_model->flag & ROC_MODEL_CNF105XX; + return roc_model->flag & ROC_MODEL_CNF105xx; } static inline uint64_t roc_model_is_cnf10kb(void) { - return roc_model->flag & ROC_MODEL_CNF105XXN; + return roc_model->flag & ROC_MODEL_CNF105xxN; +} + +static inline uint64_t +roc_model_is_cn10ka_a0(void) +{ + return roc_model->flag & ROC_MODEL_CN106xx_A0; +} + +static inline uint64_t +roc_model_is_cnf10ka_a0(void) +{ + return roc_model->flag & ROC_MODEL_CNF105xx_A0; +} + +static inline uint64_t +roc_model_is_cnf10kb_a0(void) +{ + return roc_model->flag & ROC_MODEL_CNF105xxN_A0; } int roc_model_init(struct roc_model *model); From patchwork Fri Sep 17 09:34:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 99097 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5797BA0C46; Fri, 17 Sep 2021 11:36:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E7F4F410EA; Fri, 17 Sep 2021 11:36:12 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 53403410E9 for ; Fri, 17 Sep 2021 11:36:11 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18GNENha030260 for ; Fri, 17 Sep 2021 02:36:10 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=KyrH971xUB6Yd6Ki8hce1Oxu8jOzCWB+Xy94tdAmKcg=; b=YTwHn5rtG2Nd1qc06S9Gz4STBS0bX2K1AbmebctyjwdweW6ddRP886eAIOALpmZgf5jb 3UeVFJ6n69wY6kqF59u6HCVYzo5ySBDffQdIGtJFonVw0lspPOyktXwLsEW1TyL7s882 0n+FEAJjVDktgrTOI4bGvTQRBS8sNWnHn2jGiDG3fkSoNaiKC3j1Zl02mag50axgWWHn MC9OxKkG/UWirB4UTld8hBn9YDNaSPjC4smfeyoR9jHZg6mLSKLgfbyZbBBB/GEOVdei xedZCXqLvYtTAwTyJV5DTkXaPEEF3YmadG/3bGeAObjj2x6m74yRogsndqUbRF3TzW6Z PA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3b4fe1sksb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 17 Sep 2021 02:36:10 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 17 Sep 2021 02:36:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 17 Sep 2021 02:36:09 -0700 Received: from lab-ci-142.marvell.com (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id 6C8FF3F707D; Fri, 17 Sep 2021 02:36:05 -0700 (PDT) From: Ashwin Sekhar T K To: CC: , , , , , , , , Date: Fri, 17 Sep 2021 15:04:37 +0530 Message-ID: <20210917093437.269363-2-asekhar@marvell.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210917093437.269363-1-asekhar@marvell.com> References: <20210830162903.2736191-1-asekhar@marvell.com> <20210917093437.269363-1-asekhar@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: GhQIBMcm0HHLKE_VsYCRYxINksRRfmWK X-Proofpoint-ORIG-GUID: GhQIBMcm0HHLKE_VsYCRYxINksRRfmWK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-17_04,2021-09-16_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 2/2] common/cnxk: avoid using stashing option of stype X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Avoid using stashing option of stype in NPA in cn10k-a0 stepping. This is a workaround for a HW Errata due to which NPA stashing operations will never result in writing the data into L2 cache. But instead, it will be written into LLC. Signed-off-by: Ashwin Sekhar T K Acked-by: Jerin Jacob --- drivers/common/cnxk/roc_nix_queue.c | 4 ++++ drivers/common/cnxk/roc_nix_tm_ops.c | 7 +++++++ drivers/common/cnxk/roc_npa.h | 2 +- 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 7e2f86eca7..76e439e7a9 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -585,6 +585,10 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) memset(&aura, 0, sizeof(aura)); aura.fc_ena = 1; + if (roc_model_is_cn9k() || roc_model_is_cn10ka_a0()) + aura.fc_stype = 0x0; /* STF */ + else + aura.fc_stype = 0x3; /* STSTP */ aura.fc_addr = (uint64_t)sq->fc; aura.fc_hyst_bits = 0; /* Store count on all updates */ rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, NIX_MAX_SQB, &aura, diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index ed244d4214..f2173c9a58 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -38,6 +38,13 @@ roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable) req->aura.fc_ena = enable; req->aura_mask.fc_ena = 1; + if (roc_model_is_cn9k() || roc_model_is_cn10ka_a0()) { + req->aura.fc_stype = 0x0; /* STF */ + req->aura_mask.fc_stype = 0x0; /* STF */ + } else { + req->aura.fc_stype = 0x3; /* STSTP */ + req->aura_mask.fc_stype = 0x3; /* STSTP */ + } rc = mbox_process(mbox); if (rc) diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index 3fc6192e57..1cf50e5c4e 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -214,7 +214,7 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf, cmp.u = 0; cmp.compare_s.aura = roc_npa_aura_handle_to_aura(aura_handle); cmp.compare_s.drop = drop; - cmp.compare_s.stype = ALLOC_STYPE_STSTP; + cmp.compare_s.stype = ALLOC_STYPE_STF; cmp.compare_s.dis_wait = dis_wait; cmp.compare_s.count = num;