From patchwork Thu Sep 30 05:44:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raja Zidane X-Patchwork-Id: 100048 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 20B8AA0C41; Thu, 30 Sep 2021 07:45:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E572541101; Thu, 30 Sep 2021 07:45:04 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2077.outbound.protection.outlook.com [40.107.94.77]) by mails.dpdk.org (Postfix) with ESMTP id 55BC6410FA for ; Thu, 30 Sep 2021 07:44:59 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=KqjJtXulFKnPHDB+/HCQML5q4ZKc2kBn43wqn69WUoV8e24BiEt8xaNJnigul/Sot3uHzVwyyioeapHhnvTho6SxOntDqcty7puixUUSv6rd1Efn9rlOzGLPl5H6iHBTMa9FxA3K/XtGsdf4CtVKtOk43JLbrLqLbqz4C9gVE469l2i54eNdjLsUl6zbQjkGZaQBUpw8vYwm4u0s3sCVdhJEZeIecvZCG+PE9Trv0qea2WloGlQljghJzfUiLodsCtiKac825G70qqUFJbJ5SJ1GBHWhglQUfzyGDN3WCBgMawvUz+s+/RCgrWFsNXMV6RV9FOP2tCwPSN30dHIeiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=az4dcQDxfF/2sJZK/g0n7nY+9/ROQkNXxpPVM/L0hJo=; b=fxCKYxjyVOxIcOW+QMt0Rt0GxGTpiFdrZxIBVHffpvUsfAZn9y9+KC5TLr9kp/inc2AOx2m7FGVGGl0hphDMjcR8le2gDlbfzsqa/WEj5H8CaxZqDKtXZ9sJB0jO4eAbBySBBDkXeujnashMoJfmf86n1WN+F2UKvLAzH79vlrkkdVRCkTaHcdI8mUXpkcOOE7b44+CGYkhMI+gjyjiKe/Ww+bgPq3+FmQWcmN/X7mq7/zFS3yYo4I08p3E3ottbKWYNMhj0C6cDt3ON8WF2tfGqpl8lyZ8ohXjmZ2i6eKcN0JlrdMbQy00KCuX0CtVzgv3TRWUtK7rLPqUqUtHQUw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=az4dcQDxfF/2sJZK/g0n7nY+9/ROQkNXxpPVM/L0hJo=; b=Evzr8yYiI7rqfmo7jRpjtjbQO4R1IzVUvIfCai3TGyQYdiYZq8vnqR55sPrFf99sasHWMhkUqkoAdIr7eUgVZcEvNkhS+iZQecoCuZngnPm5zdx/r5wOq2UtW2vi/uFfPLHCQQFHgyKKyop/+LSp7ALJzXIi8dheNAC23Srj0Jw/uCSf7IoQU81yc1JPpJqo95epmdArXQ6pi1zKbiuv9ffCF939bBAzlnvV7Q9OfU6v3HoWRpobErNV/117/uFDpW8wJikXVQtJ0uxh/JCNEEgT0ff5UpDam4EYhsWhgFl0CcSH2/xqkwv+FI4gCNE28WQDu5e50hDA9itMQbN8Ww== Received: from CO2PR06CA0066.namprd06.prod.outlook.com (2603:10b6:104:3::24) by BN6PR1201MB0228.namprd12.prod.outlook.com (2603:10b6:405:57::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4544.18; Thu, 30 Sep 2021 05:44:57 +0000 Received: from CO1NAM11FT060.eop-nam11.prod.protection.outlook.com (2603:10b6:104:3:cafe::fe) by CO2PR06CA0066.outlook.office365.com (2603:10b6:104:3::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 05:44:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT060.mail.protection.outlook.com (10.13.175.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 05:44:57 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 05:44:55 +0000 From: Raja Zidane To: Date: Thu, 30 Sep 2021 05:44:34 +0000 Message-ID: <20210930054438.5960-2-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210930054438.5960-1-rzidane@nvidia.com> References: <20210928121650.40181-1-rzidane@nvidia.com> <20210930054438.5960-1-rzidane@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1b71bda8-5d05-46cb-6e8f-08d983d56f93 X-MS-TrafficTypeDiagnostic: BN6PR1201MB0228: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1186; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: if2Nbeq1+o18p1hVMtHuCEMlei9cGEM4h/t8cqHTtXHq73TbOZVJkVtTWQiVDfIqCPGNQj0JmJpRpeOcI5zxYEkFMAIF0j4avPAAoddSmShRJBfwMT/QYA8mN/8SQSpMIClNNsJv4ITMOjEYjgSfPUOjkbf0qg0s4AC9TH0xLo+cx3r02gxT7IwlONgCYZLrztJdagGP0Jq9OX3gr82tGP0uIrwhQQCR7rwnZiwmsq8KkwCh7gyjNhQ6huLcsmcDSrQHbfEQChczHqkyZaWrvI4I3Fv5kStSUwIFjqOhf5pzzE6WEo1V1lXXWJaktlju3WfNeeZF2n6+kI/ks+kUTfPksIH1Y35xhCPjialj9ukX7Ooa9GYZ2/nmsjtPXNFQX73HROpm7oLkl+UCzRqGjMpjRUe9eUweClcl2mD+ps8lyytqKuT4lG2p78vaeEuvguBmPwfPJ63hlZhZuTXsuGdiqr4uiMvRLciP5h1t+I6M3M+nqfqcsRqZNbq2TGHBg+Ut3RBven8M5N5iORXn0gUYkQrLmtVACZWecc8mo3qPeVtymcc/0I/BfM/BSqyy08RraWbiAtJaahE2FvMnefyfOkW63F/ZaR7m61Qg1U3/l/LBKll9iIg6kJdg6iaFL8cOKXGVtEDPNZz5ZTAEAG8F5xchaspSsTgfmqfkqOmgHO5hqJs1EHJSsJSPRzDo6ZsbtsrwHfofKbdacLLGcQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(2906002)(1076003)(6286002)(316002)(7636003)(83380400001)(47076005)(86362001)(356005)(36860700001)(82310400003)(6666004)(5660300002)(26005)(36756003)(8676002)(70206006)(70586007)(426003)(336012)(55016002)(6916009)(508600001)(7696005)(2616005)(8936002)(16526019)(186003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2021 05:44:57.1712 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b71bda8-5d05-46cb-6e8f-08d983d56f93 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0228 Subject: [dpdk-dev] [PATCH V5 1/5] common/mlx5: update new MMO HCA capabilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" New MMO HCA capabilities were added and others were renamed. Align hca capabilities with new prm. Add support in devx interface for changes in HCA capabilities. Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 15 ++++++++++++--- drivers/common/mlx5/mlx5_devx_cmds.h | 11 ++++++++--- drivers/common/mlx5/mlx5_prm.h | 20 ++++++++++++++------ drivers/compress/mlx5/mlx5_compress.c | 4 ++-- 4 files changed, 36 insertions(+), 14 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index ac554cca05..00c78b1288 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -858,9 +858,18 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); attr->reg_c_preserve = MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); - attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo); - attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress); - attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress); + attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); + attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); + attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); + attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, + compress_mmo_sq); + attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, + decompress_mmo_sq); + attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); + attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, + compress_mmo_qp); + attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, + decompress_mmo_qp); attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, compress_min_block_size); attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index c071629904..b21df0fd9b 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -173,9 +173,14 @@ struct mlx5_hca_attr { uint32_t log_max_srq; uint32_t log_max_srq_sz; uint32_t rss_ind_tbl_cap; - uint32_t mmo_dma_en:1; - uint32_t mmo_compress_en:1; - uint32_t mmo_decompress_en:1; + uint32_t mmo_dma_sq_en:1; + uint32_t mmo_compress_sq_en:1; + uint32_t mmo_decompress_sq_en:1; + uint32_t mmo_dma_qp_en:1; + uint32_t mmo_compress_qp_en:1; + uint32_t mmo_decompress_qp_en:1; + uint32_t mmo_regex_qp_en:1; + uint32_t mmo_regex_sq_en:1; uint32_t compress_min_block_size:4; uint32_t log_max_mmo_dma:5; uint32_t log_max_mmo_compress:5; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index d361bcf90e..ec5f871c61 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1386,10 +1386,10 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 rtr2rts_qp_counters_set_id[0x1]; u8 rts2rts_udp_sport[0x1]; u8 rts2rts_lag_tx_port_affinity[0x1]; - u8 dma_mmo[0x1]; + u8 dma_mmo_sq[0x1]; u8 compress_min_block_size[0x4]; - u8 compress[0x1]; - u8 decompress[0x1]; + u8 compress_mmo_sq[0x1]; + u8 decompress_mmo_sq[0x1]; u8 log_max_ra_res_qp[0x6]; u8 end_pad[0x1]; u8 cc_query_allowed[0x1]; @@ -1519,7 +1519,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 num_lag_ports[0x4]; u8 reserved_at_280[0x10]; u8 max_wqe_sz_sq[0x10]; - u8 reserved_at_2a0[0x10]; + u8 reserved_at_2a0[0xc]; + u8 regexp_mmo_sq[0x1]; + u8 reserved_at_2b0[0x3]; u8 max_wqe_sz_rq[0x10]; u8 max_flow_counter_31_16[0x10]; u8 max_wqe_sz_sq_dc[0x10]; @@ -1632,7 +1634,12 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 num_vhca_ports[0x8]; u8 reserved_at_618[0x6]; u8 sw_owner_id[0x1]; - u8 reserved_at_61f[0x1e1]; + u8 reserved_at_61f[0x109]; + u8 dma_mmo_qp[0x1]; + u8 regexp_mmo_qp[0x1]; + u8 compress_mmo_qp[0x1]; + u8 decompress_mmo_qp[0x1]; + u8 reserved_at_624[0xd4]; }; struct mlx5_ifc_qos_cap_bits { @@ -3244,7 +3251,8 @@ struct mlx5_ifc_create_qp_in_bits { u8 uid[0x10]; u8 reserved_at_20[0x10]; u8 op_mod[0x10]; - u8 reserved_at_40[0x40]; + u8 qpc_ext[0x1]; + u8 reserved_at_41[0x3f]; u8 opt_param_mask[0x20]; u8 reserved_at_a0[0x20]; struct mlx5_ifc_qpc_bits qpc; diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index c5e0a83a8c..1e03030510 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -813,8 +813,8 @@ mlx5_compress_dev_probe(struct rte_device *dev) return -rte_errno; } if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 || - att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 || - att.mmo_dma_en == 0) { + att.mmo_compress_sq_en == 0 || att.mmo_decompress_sq_en == 0 || + att.mmo_dma_sq_en == 0) { DRV_LOG(ERR, "Not enough capabilities to support compress " "operations, maybe old FW/OFED version?"); claim_zero(mlx5_glue->close_device(ctx)); From patchwork Thu Sep 30 05:44:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raja Zidane X-Patchwork-Id: 100049 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9CB3DA0C41; Thu, 30 Sep 2021 07:45:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 297CE4111B; Thu, 30 Sep 2021 07:45:06 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2066.outbound.protection.outlook.com [40.107.244.66]) by mails.dpdk.org (Postfix) with ESMTP id AB1F3410FA for ; Thu, 30 Sep 2021 07:45:00 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HobcyZ/Wu7842nAvn2nofcvToIOLBAy0hXUdodgWB12VzYo9xq86cumAZdd8gLkXTYv/57cWBd/4Tq55kulKxJN88xbjG92A6AFO4rEBDOfW7G/6ErtdUsS+dj8ku+m2eHwnLNkaifwrvz70Z94JKb7SmTDo9fJO8FQ+HjfoeO9z4ZJCK3oCsZQJK2dJ1YWtLpUjSIK0bMlGVxaSl1sTemvgtsomNqWAMsu4Ky9CQ+yU+fq+hP4i0TEY+NLOc3UhVqNUWX2TH6ar/OlCmaJAXB1BAX5SUU1ONMrDK2yZ/4NoRsPaOEszKiEoPBvffFY1zGHwusaYtni0gixiVz08Xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=MMMg1CkI0qg/4MAQcpsNawjn09EqBXQUOD/7/ufuI1E=; b=HV6Ejj1CPD27UUITU7QRdXpUSvGaMn5IQlTG/BZc4/2Bn1jbLI70SkXUjax4ds3TNlzmdGoUJPKT1EhdlICScPfJ5UmBlok4uViK8xMaZCTV1fniW8e5TpsQpwUnSVQW7sKX5wfslEsKTQ0ovyR1wce/u9uAkq4DllIvlAFJjG+TOogReGjTLd6suRuZJX5upKbGSOp0KdwQmOba2uy+NiJtuGBCXzgiHqPp5nwAIIB9qeXOP3Q/ce0lsD3CZf3geu91bHrwgQcSMPIuGwsOI4GQM/pkX+hcs3RzKrsHsw8Q2PPnU97gjkULmqJn5Wjcc738/dANW/5gEHrqe7gi5g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MMMg1CkI0qg/4MAQcpsNawjn09EqBXQUOD/7/ufuI1E=; b=TceWSOOyfPrMkKIMmJA6guVmABsmb9jxppMHv5+Z6m4ofkLmfZTEAc/h7DDTKPZ027yGDA4AAxhVg18V7ukIblJzMM4yrbq8gSTaqLv2E25U97HVb5OwzfhAXT1/JK6PZnf5faIwuVNfRs3wsgZwsLEYfsselMRflFqdDwxNh2lMCIr1kODI4bnoElO1TG2mb5+nfVjqCJGsxwEw/kR5kONdujsvOETiTXTSkjRTpkpiTwZkU65H7hCw8l5JeCjmA1BIvitCCet0PooEGBmlEjZkoiLw2VX9LoBSFwrn9NePlUSXtiwxVTiYGNj7Aj7asmQIjD4K4oDGRhlrPCTmjw== Received: from CO2PR06CA0067.namprd06.prod.outlook.com (2603:10b6:104:3::25) by BL1PR12MB5175.namprd12.prod.outlook.com (2603:10b6:208:318::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4544.15; Thu, 30 Sep 2021 05:44:59 +0000 Received: from CO1NAM11FT060.eop-nam11.prod.protection.outlook.com (2603:10b6:104:3:cafe::9b) by CO2PR06CA0067.outlook.office365.com (2603:10b6:104:3::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 05:44:58 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT060.mail.protection.outlook.com (10.13.175.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 05:44:58 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 05:44:56 +0000 From: Raja Zidane To: Date: Thu, 30 Sep 2021 05:44:35 +0000 Message-ID: <20210930054438.5960-3-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210930054438.5960-1-rzidane@nvidia.com> References: <20210928121650.40181-1-rzidane@nvidia.com> <20210930054438.5960-1-rzidane@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ccd34d64-d406-479b-6168-08d983d57059 X-MS-TrafficTypeDiagnostic: BL1PR12MB5175: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:792; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: R9Tv8wLRmOIYd4yWjT92mgHNOjvj8JfoxYdTp3T7Mb1BN48SH+RS0uA2FsTaBFYkUS3D5qZjC+E5Ob0rycXkBr3t0+qtCp1dIox2g0REaE2IpMg6zfgEaqExRBM+GpMsJz8OaUYapWy7cHMsyyeDFV6w6OU6Uz9/xQjox52TiuNa9jpWGFWHKYmCVQItkNJT6OpNlE6NYW7EZRxAgdqam67PXZjzpl9NwJMdL27aZm4qwHBZM6P7t80InGWatCOBIgMe5Uz4dq/bV4csxfXHR3dymDWZJwMHDeNErDO7kkrrg3nsGEVjMq3H7L3G84d81STavKz0gq9BK+xauAkHffm347EPv3yJwDiPzF+5emqpoMFfwXlkzsV0MBZvsQRiLmEOK6w4q1PetqWNBCpd/MTZnCfpWvbt0b6QOzBy6FxNmuDZ4P3secR5rmNvQMX6Tr/0iljUwx31EGwHV+i+XI0vpq83/vw3bvgRzuHyTrLR3+zbbE4mM4TOy9F2xLFHEsYEmHEpYhqnaBMY8hE2m7BFU2aT28IlzvOiIDKG31521+EbTY3+qhy4aeQfH4ZyUHMnggfLZ54e8h+fKn7hH1rsHdA6j6U4ATG5RaJaeto84whzNFspjAj1R2SK9ehuQxt5GHV7OOcIu9wlVeVXabuPVzlwljBjgo5TKxaGp574RLLShvR2FFbfOanZX9cy//hDO/EPi2yVQ9a3qYkJuw== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(336012)(6666004)(426003)(7696005)(186003)(508600001)(55016002)(6286002)(70206006)(47076005)(26005)(316002)(16526019)(70586007)(36860700001)(5660300002)(86362001)(356005)(6916009)(36756003)(83380400001)(8936002)(7636003)(2616005)(8676002)(1076003)(82310400003)(2906002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2021 05:44:58.3415 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ccd34d64-d406-479b-6168-08d983d57059 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5175 Subject: [dpdk-dev] [PATCH V5 2/5] common/mlx5: add MMO configuration for the DevX QP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" A new configuration MMO was added to QP Context. If set, MMO WQEs are supported on this QP. For DMA MMO, supported only when dma_mmo_qp==1. For REGEXP MMO, supported only when regexp_mmo_qp==1. For COMPRESS MMO, supported only when compress_mmo_qp==1. For DECOMPRESS MMO, supported only when decompress_mmo_qp==1. Add support to DevX interface to set MMO bit. Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 7 +++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/common/mlx5/mlx5_prm.h | 28 +++++++++++++++++++++++++++- 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 00c78b1288..eefb869b7d 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -2032,6 +2032,13 @@ mlx5_devx_cmd_create_qp(void *ctx, MLX5_SET(qpc, qpc, ts_format, attr->ts_format); MLX5_SET(qpc, qpc, user_index, attr->user_index); if (attr->uar_index) { + if (attr->mmo) { + void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, + in, qpc_extension_and_pas_list); + void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, + qpc_ext_and_pas_list, qpc_data_extension); + MLX5_SET(qpc_extension, qpc_ext, mmo, 1); + } MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); MLX5_SET(qpc, qpc, uar_page, attr->uar_index); if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index b21df0fd9b..e149f8b4f5 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -403,6 +403,7 @@ struct mlx5_devx_qp_attr { uint32_t wq_umem_id; uint64_t wq_umem_offset; uint32_t user_index:24; + uint32_t mmo:1; }; struct mlx5_devx_virtio_q_couners_attr { diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index ec5f871c61..54e62aa153 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3243,6 +3243,28 @@ struct mlx5_ifc_create_qp_out_bits { u8 reserved_at_60[0x20]; }; +struct mlx5_ifc_qpc_extension_bits { + u8 reserved_at_0[0x2]; + u8 mmo[0x1]; + u8 reserved_at_3[0x5fd]; +}; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif +struct mlx5_ifc_qpc_pas_list_bits { + u8 pas[0][0x40]; +}; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif +struct mlx5_ifc_qpc_extension_and_pas_list_bits { + struct mlx5_ifc_qpc_extension_bits qpc_data_extension; + u8 pas[0][0x40]; +}; + + #ifdef PEDANTIC #pragma GCC diagnostic ignored "-Wpedantic" #endif @@ -3260,7 +3282,11 @@ struct mlx5_ifc_create_qp_in_bits { u8 wq_umem_id[0x20]; u8 wq_umem_valid[0x1]; u8 reserved_at_861[0x1f]; - u8 pas[0][0x40]; + union { + struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list; + struct mlx5_ifc_qpc_extension_and_pas_list_bits + qpc_extension_and_pas_list; + }; }; #ifdef PEDANTIC #pragma GCC diagnostic error "-Wpedantic" From patchwork Thu Sep 30 05:44:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raja Zidane X-Patchwork-Id: 100050 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5826CA0C41; Thu, 30 Sep 2021 07:45:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 44BF641123; Thu, 30 Sep 2021 07:45:07 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2083.outbound.protection.outlook.com [40.107.220.83]) by mails.dpdk.org (Postfix) with ESMTP id 8207F410FA for ; Thu, 30 Sep 2021 07:45:02 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=m+x5VOPUxHAtbfuo+jWtOFn+YLARH/CTSjlL+/3fuBChVs2H8YVMuT2NCoYO4+9TaweQnCUhoHUdLz60arYmPP2LIR/709E1lcSx4SfS26kE62h8wy5zVsmnvu4MchgwZXM0PcJXWCHm+wIJ59iTxAhL2OW+l7S3oz4Co4+l15vyeTgoyb8B9bAxC0SGd5On4Hhm/QAbciWRT2/1lTnLLJAnCO03q61lfM2GRnwuBNWHM5US6OAT0eQXRNIQHD/SRCbS+yBFdh3rfXtq1r4+cvLcIie0G2bw7arhxH8RJLc+ixIj/72yjOGzHjYYoJpwQNnqkC9qrb1RC1DPIc9ADA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=Gs2TSgND6mZH27n9ByLODRl5rTlv1Fi36nfZqwTpycA=; b=CdMu/WHP0sw1s7TONeiy7Y2Khl0659oQZDUhNmQ8WHiYObebVk+zNtNMAd9JEgDUWfsDUzuz6ouGMTX2w6H0O0t1uGS8FUjtsSaHCboEVuN5kedB6XqiwAcoEqAgpXptJ4k9WqmIWN4/qRfGs95a+KAKRPoxLuh0tnVhehUb6R1RX7Gi9ZLgSXYydwxJXT6EarOGR63f9u06tj9t4rbiVJzsc17CP8uOUOVUD5ju83zOiDnuIKwrhEZ1hJckpJ8ESoANZrUsiuDa7oqyVyKSaefUPge20eiX3241fbnwkCsnB64guNALbai9D+cS02wW10G/BWsVLmAaP/FyRjY4Rg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Gs2TSgND6mZH27n9ByLODRl5rTlv1Fi36nfZqwTpycA=; b=QpzqITAb9RFLVBdlV6kFeDwRc24f0I79BQ5VzjOj5ULldoHZ1Tl2RIAf6gkg1HRU0Ffel6awSanfNnZMaqGO6dBM3T8tX2BP49ayG3wFRMWqQUKnBWY+6Y3/pgLfgaEviK/zIXmZ85lcA33scOLwlG9n+8nYz4+I8S8YE5pL41SKv1lpDQu2B6+8CI2giZ7OhLmDad60Scd4NLxEqmVLUmdVWMYz0jOnXUh+dE9txhbaqhHQJpiQoxDCuFEOtf1y8SgcnFZJtBwtz5GpU8O+1HxdfU9LGmKBwls9ZIO5npfPnm8zxRDXup6DcNMInVD8x65P+julSScWnog06dGLeg== Received: from CO2PR06CA0065.namprd06.prod.outlook.com (2603:10b6:104:3::23) by BL0PR12MB4755.namprd12.prod.outlook.com (2603:10b6:208:82::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4544.18; Thu, 30 Sep 2021 05:45:00 +0000 Received: from CO1NAM11FT060.eop-nam11.prod.protection.outlook.com (2603:10b6:104:3:cafe::a2) by CO2PR06CA0065.outlook.office365.com (2603:10b6:104:3::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 05:45:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT060.mail.protection.outlook.com (10.13.175.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 05:45:00 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 05:44:57 +0000 From: Raja Zidane To: Date: Thu, 30 Sep 2021 05:44:36 +0000 Message-ID: <20210930054438.5960-4-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210930054438.5960-1-rzidane@nvidia.com> References: <20210928121650.40181-1-rzidane@nvidia.com> <20210930054438.5960-1-rzidane@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5232338b-f45e-4d87-9f51-08d983d5714c X-MS-TrafficTypeDiagnostic: BL0PR12MB4755: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2089; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DfUPDK4eIK3ve/s7wL/qjI/Jc6udIVj8mWGAIonHWqfyueeLACEKdjBCgoB1P50eQYTerM+zOg+OEn9LSpVLRhT1qQzrtfgZgdZTGacvulM0SCX5S+DTIpTqnZAfe3qPB0JfesCf8ojj8QXb8QZUarqsvSJQ3L10vdPCbhie2AKTbOHifXSu6oNiVVaN2LTt7MCY+OLzizgwG8F/lN/iwa/5zgtsOyDxJyk0P3/z/f1Bst74Lkhqo+tJggzMmpzrNmfWQ51BTg+Uvi6brlTIzmqDidBELlshLD5+j+PKb7399qfblPaOeWlqacR2hu80ODkQy1V2oRnohD/ltdQIyDtouJX7vsus75/3AHqmi4Co/pqhpXFjeap5DL8ZsiNZW6W/3H6FBPAikqPYLkB3v3xmYgnAIqpIiRVFTZBxRSDByVF5y83VRxcQPJYmJcwQGW+iABQTLn6PkjdM65YsvK2feYBjjzO0s7A49DGbpA9BBowMhCmlT33nbuPIzT+myMY8PdxhHdctI9ncg4B+NlKUSeTr1cWd6TDppfnKdBcAGnUQo+0DBGF538iUoMsnljhIbseZ7SdXYLyJ3Z5jDdwIJullQfD4SGTE5+SteMWUFxzXDOblMLNyu7RGB3n/HjSG4D6J+wEzhbffZJpUf7AoeWAhIhMV7RupQ8/8xMMIMZ43c/zEeeE/WY2N58sO28jHpEXFIKvfdeIUmXY7Wg== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(55016002)(6286002)(86362001)(70586007)(508600001)(2616005)(316002)(2906002)(70206006)(1076003)(83380400001)(36860700001)(47076005)(7696005)(8676002)(8936002)(6666004)(36756003)(426003)(6916009)(16526019)(186003)(7636003)(26005)(356005)(82310400003)(336012)(5660300002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2021 05:45:00.0196 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5232338b-f45e-4d87-9f51-08d983d5714c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4755 Subject: [dpdk-dev] [PATCH V5 3/5] compress/mlx5: refactor queue HW object X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The mlx5 PMD for compress class uses an MMO WQE operated by the GGA engine in BF devices. Currently, all the MMO WQEs are managed by the SQ object. Starting from BF3, the queue of the MMO WQEs should be connected to the GGA engine using a new configuration, MMO, that will be supported only in the QP object. The FW introduced new capabilities to define whether the MMO configuration should be configured for the GGA queue. Replace all the GGA queue objects to QP, set MMO configuration according to the new FW capabilities. Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/compress/mlx5/mlx5_compress.c | 73 +++++++++++++++------------ 1 file changed, 42 insertions(+), 31 deletions(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 1e03030510..5c5aa87a18 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -40,7 +40,7 @@ struct mlx5_compress_priv { void *uar; uint32_t pdn; /* Protection Domain number. */ uint8_t min_block_size; - uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */ + uint8_t qp_ts_format; /* Whether SQ supports timestamp formats. */ /* Minimum huffman block size supported by the device. */ struct ibv_pd *pd; struct rte_compressdev_config dev_config; @@ -48,6 +48,13 @@ struct mlx5_compress_priv { rte_spinlock_t xform_sl; struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ volatile uint64_t *uar_addr; + /* HCA caps*/ + uint32_t mmo_decomp_sq:1; + uint32_t mmo_decomp_qp:1; + uint32_t mmo_comp_sq:1; + uint32_t mmo_comp_qp:1; + uint32_t mmo_dma_sq:1; + uint32_t mmo_dma_qp:1; #ifndef RTE_ARCH_64 rte_spinlock_t uar32_sl; #endif /* RTE_ARCH_64 */ @@ -61,7 +68,7 @@ struct mlx5_compress_qp { struct mlx5_mr_ctrl mr_ctrl; int socket_id; struct mlx5_devx_cq cq; - struct mlx5_devx_sq sq; + struct mlx5_devx_qp qp; struct mlx5_pmd_mr opaque_mr; struct rte_comp_op **ops; struct mlx5_compress_priv *priv; @@ -134,8 +141,8 @@ mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id) { struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; - if (qp->sq.sq != NULL) - mlx5_devx_sq_destroy(&qp->sq); + if (qp->qp.qp != NULL) + mlx5_devx_qp_destroy(&qp->qp); if (qp->cq.cq != NULL) mlx5_devx_cq_destroy(&qp->cq); if (qp->opaque_mr.obj != NULL) { @@ -152,12 +159,12 @@ mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id) } static void -mlx5_compress_init_sq(struct mlx5_compress_qp *qp) +mlx5_compress_init_qp(struct mlx5_compress_qp *qp) { volatile struct mlx5_gga_wqe *restrict wqe = - (volatile struct mlx5_gga_wqe *)qp->sq.wqes; + (volatile struct mlx5_gga_wqe *)qp->qp.wqes; volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; - const uint32_t sq_ds = rte_cpu_to_be_32((qp->sq.sq->id << 8) | 4u); + const uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u); const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS << MLX5_COMP_MODE_OFFSET); const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey); @@ -182,15 +189,10 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, struct mlx5_devx_cq_attr cq_attr = { .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar), }; - struct mlx5_devx_create_sq_attr sq_attr = { + struct mlx5_devx_qp_attr qp_attr = { + .pd = priv->pdn, + .uar_index = mlx5_os_get_devx_uar_page_id(priv->uar), .user_index = qp_id, - .wq_attr = (struct mlx5_devx_wq_attr){ - .pd = priv->pdn, - .uar_page = mlx5_os_get_devx_uar_page_id(priv->uar), - }, - }; - struct mlx5_devx_modify_sq_attr modify_attr = { - .state = MLX5_SQC_STATE_RDY, }; uint32_t log_ops_n = rte_log2_u32(max_inflight_ops); uint32_t alloc_size = sizeof(*qp); @@ -242,24 +244,26 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, DRV_LOG(ERR, "Failed to create CQ."); goto err; } - sq_attr.cqn = qp->cq.cq->id; - sq_attr.ts_format = mlx5_ts_format_conv(priv->sq_ts_format); - ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr, + qp_attr.cqn = qp->cq.cq->id; + qp_attr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format); + qp_attr.rq_size = 0; + qp_attr.sq_size = RTE_BIT32(log_ops_n); + qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp + && priv->mmo_dma_qp; + ret = mlx5_devx_qp_create(priv->ctx, &qp->qp, log_ops_n, &qp_attr, socket_id); if (ret != 0) { - DRV_LOG(ERR, "Failed to create SQ."); + DRV_LOG(ERR, "Failed to create QP."); goto err; } - mlx5_compress_init_sq(qp); - ret = mlx5_devx_cmd_modify_sq(qp->sq.sq, &modify_attr); - if (ret != 0) { - DRV_LOG(ERR, "Can't change SQ state to ready."); + mlx5_compress_init_qp(qp); + ret = mlx5_devx_qp2rts(&qp->qp, 0); + if (ret) goto err; - } /* Save pointer of global generation number to check memory event. */ qp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen; DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u", - (uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n); + (uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n); return 0; err: mlx5_compress_qp_release(dev, qp_id); @@ -508,7 +512,7 @@ mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops, { struct mlx5_compress_qp *qp = queue_pair; volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) - qp->sq.wqes, *wqe; + qp->qp.wqes, *wqe; struct mlx5_compress_xform *xform; struct rte_comp_op *op; uint16_t mask = qp->entries_n - 1; @@ -563,7 +567,7 @@ mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops, } while (--remain); qp->stats.enqueued_count += nb_ops; rte_io_wmb(); - qp->sq.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi); + qp->qp.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi); rte_wmb(); mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv); rte_wmb(); @@ -598,7 +602,7 @@ mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp, volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *) &qp->cq.cqes[idx]; volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) - qp->sq.wqes; + qp->qp.wqes; volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; op->status = RTE_COMP_OP_STATUS_ERROR; @@ -813,8 +817,9 @@ mlx5_compress_dev_probe(struct rte_device *dev) return -rte_errno; } if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 || - att.mmo_compress_sq_en == 0 || att.mmo_decompress_sq_en == 0 || - att.mmo_dma_sq_en == 0) { + ((att.mmo_compress_sq_en == 0 || att.mmo_decompress_sq_en == 0 || + att.mmo_dma_sq_en == 0) && (att.mmo_compress_qp_en == 0 || + att.mmo_decompress_qp_en == 0 || att.mmo_dma_qp_en == 0))) { DRV_LOG(ERR, "Not enough capabilities to support compress " "operations, maybe old FW/OFED version?"); claim_zero(mlx5_glue->close_device(ctx)); @@ -835,10 +840,16 @@ mlx5_compress_dev_probe(struct rte_device *dev) cdev->enqueue_burst = mlx5_compress_enqueue_burst; cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; priv = cdev->data->dev_private; + priv->mmo_decomp_sq = att.mmo_decompress_sq_en; + priv->mmo_decomp_qp = att.mmo_decompress_qp_en; + priv->mmo_comp_sq = att.mmo_compress_sq_en; + priv->mmo_comp_qp = att.mmo_compress_qp_en; + priv->mmo_dma_sq = att.mmo_dma_sq_en; + priv->mmo_dma_qp = att.mmo_dma_qp_en; priv->ctx = ctx; priv->cdev = cdev; priv->min_block_size = att.compress_min_block_size; - priv->sq_ts_format = att.sq_ts_format; + priv->qp_ts_format = att.qp_ts_format; if (mlx5_compress_hw_global_prepare(priv) != 0) { rte_compressdev_pmd_destroy(priv->cdev); claim_zero(mlx5_glue->close_device(priv->ctx)); From patchwork Thu Sep 30 05:44:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raja Zidane X-Patchwork-Id: 100051 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 75B35A0C41; Thu, 30 Sep 2021 07:45:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 643C541135; Thu, 30 Sep 2021 07:45:08 +0200 (CEST) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2084.outbound.protection.outlook.com [40.107.93.84]) by mails.dpdk.org (Postfix) with ESMTP id 6E67A410FA for ; Thu, 30 Sep 2021 07:45:03 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Vvpc+ZBGxKPC8sfOdh37/YKRPs0G/pcXB+Kpii3iripImAs2jce8GU62KjbaHEeoqKwW8uW3VMs7xvVs7TNiL7wh5l+oXxvDyBeFSM/Ox6Y5E/yTRWcxq3qqJjoKb3f+5GG1u2TblTOLx7t7inkzw8uwsX72SKkZR9AHVZXrM1pDNoopsRXh4Je12XFy7QmOeAfZHBu865vV+caxLEDWoDGxyvhI6KffB0hz8wYEHBEj6wv4RskMyA4jIIwyJLJurJ4OdeHtnDsgvx4ws02JOHVjQtRAv61C8PPWaFRKl9ITfKREEHiYKGhGfbcrhrGL8br0NO5b2sNfDeMtSZPB0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=P72rfGZuaoau5SBa7y6KyFxgKPGL8nWTD4tXCHiRT6M=; b=b2SIU1mZE82e2ts86lpeJsbcvJ55ei66hgctaRVtz13dphk4/zzl+QJLzav06+5KE7KFcaRv2ep5amphOhyJEvQgxXpbOUqWTAshaHM28JnTIDTcPJbnBpMYZ/1E6NvRP3gVRqwyU4qq9FbM1T6vRh0a55SqWG/5Z8dlneGVntd7dL37LLdwfKMbf+OzOh/tAJiWGq3tjpLKkFoqzIF7TP17NaQW1/17cpc8u+aVQAtO+1jhksO8N/q45mZfgltNWCLDuwA6u79UQy0P8PdK1m9jngMAgyiuod7E6AN+tyMV/AyOXVXHwAqgPDgY5sWnT+YwqmYpV5ovf+FDrYc1wQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=P72rfGZuaoau5SBa7y6KyFxgKPGL8nWTD4tXCHiRT6M=; b=UbA46Bhjlt8t9am/HH7bq8vlOdWL2Jn4lXLzpjLtOIu401R7Y3zsjv5Hok7/Fb1PDpDmWTB/FOdZKS/JHHMYGuk5Nemj+5WLp+kfPn22Nht7zs90W1B0OrJ+LNPadLAg/1yQd/+/r/zt+9Se2CuASRKYNXMwcNJFCdTOewViVzLp4IowZ3VRarcXV4ibdGZQIM31O8RQg5aIlFA56PLDAqclyoxvR8zJhXf5PkxMbP5JgWAUpI4Lk4k/GOCQcgmYkJm9bWq0cysrfDxjyGOBVuBFre5i4eqbC2n+1XBwsxxuzGoEtAwiw33f6nS4XvMYNxzrxtTb0kqstQsmH+nNEg== Received: from CO2PR06CA0055.namprd06.prod.outlook.com (2603:10b6:104:3::13) by BN8PR12MB3107.namprd12.prod.outlook.com (2603:10b6:408:46::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4544.14; Thu, 30 Sep 2021 05:45:01 +0000 Received: from CO1NAM11FT060.eop-nam11.prod.protection.outlook.com (2603:10b6:104:3:cafe::ba) by CO2PR06CA0055.outlook.office365.com (2603:10b6:104:3::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 05:45:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT060.mail.protection.outlook.com (10.13.175.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 05:45:01 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 05:44:58 +0000 From: Raja Zidane To: Date: Thu, 30 Sep 2021 05:44:37 +0000 Message-ID: <20210930054438.5960-5-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210930054438.5960-1-rzidane@nvidia.com> References: <20210928121650.40181-1-rzidane@nvidia.com> <20210930054438.5960-1-rzidane@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c62ba1f0-259e-488b-2012-08d983d571e5 X-MS-TrafficTypeDiagnostic: BN8PR12MB3107: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:167; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: h26sPYvqoLHWeNP6CEDyLaexIwlFmIpU2VWEkCXcHQR+7UWRlHI8wZ/noW+lPcdvcQAZfg1QuRbmPqoiYPZ+N8fiBVAbL0LX9HrZ8Ab1cC9MzYFGzk5VELiJ6cuuFKHaiC1Macio4ldX/yVCEH2dGi4DTbVknvQXMFdkXduxcna6rhCrRs4vD17UgtsS8YWpvBuptvJgsvIChXatxby+CpOvX0Cz7GeQ2oziVYa9tNb50B6dAoQJUeKTqH9ZIG79xvBt6MqFxBcH/VIitTXUAPmapggYrMMLKi8TxX+vd4ka81Ez+0mk5g2izoQrwadBzkMFsNALhf5rJNqmmQYDVNvP7jAeswlCCaW/WpMwnr2LHVI4nEAeasM67+Cpe03scpybx7XvlKVuILKccDiRrui2zDMa8/ZZi3jqFct7I6kjL3rgc67/44e+XfMkqo92+z+imLYh7zmZ1jprTgg2bJpjRsYS3LAN3+S8IP/FgiEQIqDbQW/Mxk9Na3DX4CX/MaiRflZIextap8UpdSR9n3VMU8PQQWnATwA8rlRHuG1ePeZDYWwi8bf7FbJqQUP5YdH77TQBbg7Xas9KB93AF8XjqS3YsgL3HVbgrj1VH5986xhPQIzgaODU2YCR5B+ALGEQGcMQB8MnCsRyn0yoaI8Q37KGKv12nK4EJ8L7Z/wbhTbEjEsSzbwI6cUpik/rdYy47YmyedE5YIbGmVVq5Q== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(7696005)(83380400001)(186003)(47076005)(1076003)(70586007)(8676002)(26005)(70206006)(426003)(336012)(6286002)(8936002)(2616005)(5660300002)(6916009)(16526019)(30864003)(82310400003)(55016002)(6666004)(36756003)(36860700001)(7636003)(316002)(356005)(508600001)(86362001)(2906002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2021 05:45:01.0440 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c62ba1f0-259e-488b-2012-08d983d571e5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3107 Subject: [dpdk-dev] [PATCH V5 4/5] regex/mlx5: refactor HW queue objects X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The mlx5 PMD for regex class uses an MMO WQE operated by the GGA engine in BF devices. Currently, all the MMO WQEs are managed by the SQ object. Starting from BF3, the queue of the MMO WQEs should be connected to the GGA engine using a new configuration, MMO, that will be supported only in the QP object. The FW introduced new capabilities to define whether the MMO configuration should be configured for the GGA queue. Replace all the GGA queue objects to QP, set MMO configuration according to the new FW capabilities. Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/regex/mlx5/mlx5_regex.c | 7 +- drivers/regex/mlx5/mlx5_regex.h | 16 ++- drivers/regex/mlx5/mlx5_regex_control.c | 65 +++++---- drivers/regex/mlx5/mlx5_regex_fastpath.c | 170 ++++++++++++----------- 4 files changed, 133 insertions(+), 125 deletions(-) diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index 8866a4d0c6..5aa988be6d 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -146,7 +146,8 @@ mlx5_regex_dev_probe(struct rte_device *rte_dev) DRV_LOG(ERR, "Unable to read HCA capabilities."); rte_errno = ENOTSUP; goto dev_error; - } else if (!attr.regex || attr.regexp_num_of_engines == 0) { + } else if (((!attr.regex) && (!attr.mmo_regex_sq_en) && + (!attr.mmo_regex_qp_en)) || attr.regexp_num_of_engines == 0) { DRV_LOG(ERR, "Not enough capabilities to support RegEx, maybe " "old FW/OFED version?"); rte_errno = ENOTSUP; @@ -164,7 +165,9 @@ mlx5_regex_dev_probe(struct rte_device *rte_dev) rte_errno = ENOMEM; goto dev_error; } - priv->sq_ts_format = attr.sq_ts_format; + priv->mmo_regex_qp_cap = attr.mmo_regex_qp_en; + priv->mmo_regex_sq_cap = attr.mmo_regex_sq_en; + priv->qp_ts_format = attr.qp_ts_format; priv->ctx = ctx; priv->nb_engines = 2; /* attr.regexp_num_of_engines */ ret = mlx5_devx_regex_register_read(priv->ctx, 0, diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h index 514f3408f9..2242d250a3 100644 --- a/drivers/regex/mlx5/mlx5_regex.h +++ b/drivers/regex/mlx5/mlx5_regex.h @@ -17,12 +17,12 @@ #include "mlx5_rxp.h" #include "mlx5_regex_utils.h" -struct mlx5_regex_sq { +struct mlx5_regex_hw_qp { uint16_t log_nb_desc; /* Log 2 number of desc for this object. */ - struct mlx5_devx_sq sq_obj; /* The SQ DevX object. */ + struct mlx5_devx_qp qp_obj; /* The QP DevX object. */ size_t pi, db_pi; size_t ci; - uint32_t sqn; + uint32_t qpn; }; struct mlx5_regex_cq { @@ -34,10 +34,10 @@ struct mlx5_regex_cq { struct mlx5_regex_qp { uint32_t flags; /* QP user flags. */ uint32_t nb_desc; /* Total number of desc for this qp. */ - struct mlx5_regex_sq *sqs; /* Pointer to sq array. */ - uint16_t nb_obj; /* Number of sq objects. */ + struct mlx5_regex_hw_qp *qps; /* Pointer to qp array. */ + uint16_t nb_obj; /* Number of qp objects. */ struct mlx5_regex_cq cq; /* CQ struct. */ - uint32_t free_sqs; + uint32_t free_qps; struct mlx5_regex_job *jobs; struct ibv_mr *metadata; struct ibv_mr *outputs; @@ -73,8 +73,10 @@ struct mlx5_regex_priv { /**< Called by memory event callback. */ struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ uint8_t is_bf2; /* The device is BF2 device. */ - uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */ + uint8_t qp_ts_format; /* Whether SQ supports timestamp formats. */ uint8_t has_umr; /* The device supports UMR. */ + uint32_t mmo_regex_qp_cap:1; + uint32_t mmo_regex_sq_cap:1; }; #ifdef HAVE_IBV_FLOW_DV_SUPPORT diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c index 8ce2dabb55..572ecc6d86 100644 --- a/drivers/regex/mlx5/mlx5_regex_control.c +++ b/drivers/regex/mlx5/mlx5_regex_control.c @@ -106,12 +106,12 @@ regex_ctrl_create_cq(struct mlx5_regex_priv *priv, struct mlx5_regex_cq *cq) * 0 on success, a negative errno value otherwise and rte_errno is set. */ static int -regex_ctrl_destroy_sq(struct mlx5_regex_qp *qp, uint16_t q_ind) +regex_ctrl_destroy_hw_qp(struct mlx5_regex_qp *qp, uint16_t q_ind) { - struct mlx5_regex_sq *sq = &qp->sqs[q_ind]; + struct mlx5_regex_hw_qp *qp_obj = &qp->qps[q_ind]; - mlx5_devx_sq_destroy(&sq->sq_obj); - memset(sq, 0, sizeof(*sq)); + mlx5_devx_qp_destroy(&qp_obj->qp_obj); + memset(qp, 0, sizeof(*qp)); return 0; } @@ -131,45 +131,44 @@ regex_ctrl_destroy_sq(struct mlx5_regex_qp *qp, uint16_t q_ind) * 0 on success, a negative errno value otherwise and rte_errno is set. */ static int -regex_ctrl_create_sq(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, +regex_ctrl_create_hw_qp(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, uint16_t q_ind, uint16_t log_nb_desc) { #ifdef HAVE_IBV_FLOW_DV_SUPPORT - struct mlx5_devx_create_sq_attr attr = { - .user_index = q_ind, + struct mlx5_devx_qp_attr attr = { .cqn = qp->cq.cq_obj.cq->id, - .wq_attr = (struct mlx5_devx_wq_attr){ - .uar_page = priv->uar->page_id, - }, - .ts_format = mlx5_ts_format_conv(priv->sq_ts_format), - }; - struct mlx5_devx_modify_sq_attr modify_attr = { - .state = MLX5_SQC_STATE_RDY, + .uar_index = priv->uar->page_id, + .ts_format = mlx5_ts_format_conv(priv->qp_ts_format), + .user_index = q_ind, }; - struct mlx5_regex_sq *sq = &qp->sqs[q_ind]; + struct mlx5_regex_hw_qp *qp_obj = &qp->qps[q_ind]; uint32_t pd_num = 0; int ret; - sq->log_nb_desc = log_nb_desc; - sq->sqn = q_ind; - sq->ci = 0; - sq->pi = 0; + qp_obj->log_nb_desc = log_nb_desc; + qp_obj->qpn = q_ind; + qp_obj->ci = 0; + qp_obj->pi = 0; ret = regex_get_pdn(priv->pd, &pd_num); if (ret) return ret; - attr.wq_attr.pd = pd_num; - ret = mlx5_devx_sq_create(priv->ctx, &sq->sq_obj, + attr.pd = pd_num; + attr.rq_size = 0; + attr.sq_size = RTE_BIT32(MLX5_REGEX_WQE_LOG_NUM(priv->has_umr, + log_nb_desc)); + attr.mmo = priv->mmo_regex_qp_cap; + ret = mlx5_devx_qp_create(priv->ctx, &qp_obj->qp_obj, MLX5_REGEX_WQE_LOG_NUM(priv->has_umr, log_nb_desc), &attr, SOCKET_ID_ANY); if (ret) { - DRV_LOG(ERR, "Can't create SQ object."); + DRV_LOG(ERR, "Can't create QP object."); rte_errno = ENOMEM; return -rte_errno; } - ret = mlx5_devx_cmd_modify_sq(sq->sq_obj.sq, &modify_attr); + ret = mlx5_devx_qp2rts(&qp_obj->qp_obj, 0); if (ret) { - DRV_LOG(ERR, "Can't change SQ state to ready."); - regex_ctrl_destroy_sq(qp, q_ind); + DRV_LOG(ERR, "Can't change QP state to RTS."); + regex_ctrl_destroy_hw_qp(qp, q_ind); rte_errno = ENOMEM; return -rte_errno; } @@ -224,10 +223,10 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind, (1 << MLX5_REGEX_WQE_LOG_NUM(priv->has_umr, log_desc)); else qp->nb_obj = 1; - qp->sqs = rte_malloc(NULL, - qp->nb_obj * sizeof(struct mlx5_regex_sq), 64); - if (!qp->sqs) { - DRV_LOG(ERR, "Can't allocate sq array memory."); + qp->qps = rte_malloc(NULL, + qp->nb_obj * sizeof(struct mlx5_regex_hw_qp), 64); + if (!qp->qps) { + DRV_LOG(ERR, "Can't allocate qp array memory."); rte_errno = ENOMEM; return -rte_errno; } @@ -238,9 +237,9 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind, goto err_cq; } for (i = 0; i < qp->nb_obj; i++) { - ret = regex_ctrl_create_sq(priv, qp, i, log_desc); + ret = regex_ctrl_create_hw_qp(priv, qp, i, log_desc); if (ret) { - DRV_LOG(ERR, "Can't create sq."); + DRV_LOG(ERR, "Can't create qp object."); goto err_btree; } nb_sq_config++; @@ -266,9 +265,9 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind, mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh); err_btree: for (i = 0; i < nb_sq_config; i++) - regex_ctrl_destroy_sq(qp, i); + regex_ctrl_destroy_hw_qp(qp, i); regex_ctrl_destroy_cq(&qp->cq); err_cq: - rte_free(qp->sqs); + rte_free(qp->qps); return ret; } diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c index c79445ce7d..0833b2817e 100644 --- a/drivers/regex/mlx5/mlx5_regex_fastpath.c +++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c @@ -39,13 +39,13 @@ #define MLX5_REGEX_KLMS_SIZE \ ((MLX5_REGEX_MAX_KLM_NUM) * sizeof(struct mlx5_klm)) /* In WQE set mode, the pi should be quarter of the MLX5_REGEX_MAX_WQE_INDEX. */ -#define MLX5_REGEX_UMR_SQ_PI_IDX(pi, ops) \ +#define MLX5_REGEX_UMR_QP_PI_IDX(pi, ops) \ (((pi) + (ops)) & (MLX5_REGEX_MAX_WQE_INDEX >> 2)) static inline uint32_t -sq_size_get(struct mlx5_regex_sq *sq) +qp_size_get(struct mlx5_regex_hw_qp *qp) { - return (1U << sq->log_nb_desc); + return (1U << qp->log_nb_desc); } static inline uint32_t @@ -144,11 +144,11 @@ mlx5_regex_addr2mr(struct mlx5_regex_priv *priv, struct mlx5_mr_ctrl *mr_ctrl, static inline void -__prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq, +__prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_hw_qp *qp_obj, struct rte_regex_ops *op, struct mlx5_regex_job *job, size_t pi, struct mlx5_klm *klm) { - size_t wqe_offset = (pi & (sq_size_get(sq) - 1)) * + size_t wqe_offset = (pi & (qp_size_get(qp_obj) - 1)) * (MLX5_SEND_WQE_BB << (priv->has_umr ? 2 : 0)) + (priv->has_umr ? MLX5_REGEX_UMR_WQE_SIZE : 0); uint16_t group0 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID0_VALID_F ? @@ -168,13 +168,13 @@ __prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq, RTE_REGEX_OPS_REQ_GROUP_ID2_VALID_F | RTE_REGEX_OPS_REQ_GROUP_ID3_VALID_F))) group0 = op->group_id0; - uint8_t *wqe = (uint8_t *)(uintptr_t)sq->sq_obj.wqes + wqe_offset; + uint8_t *wqe = (uint8_t *)(uintptr_t)qp_obj->qp_obj.wqes + wqe_offset; int ds = 4; /* ctrl + meta + input + output */ set_wqe_ctrl_seg((struct mlx5_wqe_ctrl_seg *)wqe, (priv->has_umr ? (pi * 4 + 3) : pi), MLX5_OPCODE_MMO, MLX5_OPC_MOD_MMO_REGEX, - sq->sq_obj.sq->id, 0, ds, 0, 0); + qp_obj->qp_obj.qp->id, 0, ds, 0, 0); set_regex_ctrl_seg(wqe + 12, 0, group0, group1, group2, group3, control); struct mlx5_wqe_data_seg *input_seg = @@ -188,7 +188,7 @@ __prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq, static inline void prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, - struct mlx5_regex_sq *sq, struct rte_regex_ops *op, + struct mlx5_regex_hw_qp *qp_obj, struct rte_regex_ops *op, struct mlx5_regex_job *job) { struct mlx5_klm klm; @@ -196,42 +196,42 @@ prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, klm.byte_count = rte_pktmbuf_data_len(op->mbuf); klm.mkey = mlx5_regex_addr2mr(priv, &qp->mr_ctrl, op->mbuf); klm.address = rte_pktmbuf_mtod(op->mbuf, uintptr_t); - __prep_one(priv, sq, op, job, sq->pi, &klm); - sq->db_pi = sq->pi; - sq->pi = (sq->pi + 1) & MLX5_REGEX_MAX_WQE_INDEX; + __prep_one(priv, qp_obj, op, job, qp_obj->pi, &klm); + qp_obj->db_pi = qp_obj->pi; + qp_obj->pi = (qp_obj->pi + 1) & MLX5_REGEX_MAX_WQE_INDEX; } static inline void -send_doorbell(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq) +send_doorbell(struct mlx5_regex_priv *priv, struct mlx5_regex_hw_qp *qp_obj) { struct mlx5dv_devx_uar *uar = priv->uar; - size_t wqe_offset = (sq->db_pi & (sq_size_get(sq) - 1)) * + size_t wqe_offset = (qp_obj->db_pi & (qp_size_get(qp_obj) - 1)) * (MLX5_SEND_WQE_BB << (priv->has_umr ? 2 : 0)) + (priv->has_umr ? MLX5_REGEX_UMR_WQE_SIZE : 0); - uint8_t *wqe = (uint8_t *)(uintptr_t)sq->sq_obj.wqes + wqe_offset; + uint8_t *wqe = (uint8_t *)(uintptr_t)qp_obj->qp_obj.wqes + wqe_offset; /* Or the fm_ce_se instead of set, avoid the fence be cleared. */ ((struct mlx5_wqe_ctrl_seg *)wqe)->fm_ce_se |= MLX5_WQE_CTRL_CQ_UPDATE; uint64_t *doorbell_addr = (uint64_t *)((uint8_t *)uar->base_addr + 0x800); rte_io_wmb(); - sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32((priv->has_umr ? - (sq->db_pi * 4 + 3) : sq->db_pi) & - MLX5_REGEX_MAX_WQE_INDEX); + qp_obj->qp_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32((priv->has_umr ? + (qp_obj->db_pi * 4 + 3) : qp_obj->db_pi) + & MLX5_REGEX_MAX_WQE_INDEX); rte_wmb(); *doorbell_addr = *(volatile uint64_t *)wqe; rte_wmb(); } static inline int -get_free(struct mlx5_regex_sq *sq, uint8_t has_umr) { - return (sq_size_get(sq) - ((sq->pi - sq->ci) & +get_free(struct mlx5_regex_hw_qp *qp, uint8_t has_umr) { + return (qp_size_get(qp) - ((qp->pi - qp->ci) & (has_umr ? (MLX5_REGEX_MAX_WQE_INDEX >> 2) : MLX5_REGEX_MAX_WQE_INDEX))); } static inline uint32_t -job_id_get(uint32_t qid, size_t sq_size, size_t index) { - return qid * sq_size + (index & (sq_size - 1)); +job_id_get(uint32_t qid, size_t qp_size, size_t index) { + return qid * qp_size + (index & (qp_size - 1)); } #ifdef HAVE_MLX5_UMR_IMKEY @@ -242,14 +242,14 @@ mkey_klm_available(struct mlx5_klm *klm, uint32_t pos, uint32_t new) } static inline void -complete_umr_wqe(struct mlx5_regex_qp *qp, struct mlx5_regex_sq *sq, +complete_umr_wqe(struct mlx5_regex_qp *qp, struct mlx5_regex_hw_qp *qp_obj, struct mlx5_regex_job *mkey_job, size_t umr_index, uint32_t klm_size, uint32_t total_len) { - size_t wqe_offset = (umr_index & (sq_size_get(sq) - 1)) * + size_t wqe_offset = (umr_index & (qp_size_get(qp_obj) - 1)) * (MLX5_SEND_WQE_BB * 4); struct mlx5_wqe_ctrl_seg *wqe = (struct mlx5_wqe_ctrl_seg *)((uint8_t *) - (uintptr_t)sq->sq_obj.wqes + wqe_offset); + (uintptr_t)qp_obj->qp_obj.wqes + wqe_offset); struct mlx5_wqe_umr_ctrl_seg *ucseg = (struct mlx5_wqe_umr_ctrl_seg *)(wqe + 1); struct mlx5_wqe_mkey_context_seg *mkc = @@ -260,7 +260,7 @@ complete_umr_wqe(struct mlx5_regex_qp *qp, struct mlx5_regex_sq *sq, memset(wqe, 0, MLX5_REGEX_UMR_WQE_SIZE); /* Set WQE control seg. Non-inline KLM UMR WQE size must be 9 WQE_DS. */ set_wqe_ctrl_seg(wqe, (umr_index * 4), MLX5_OPCODE_UMR, - 0, sq->sq_obj.sq->id, 0, 9, 0, + 0, qp_obj->qp_obj.qp->id, 0, 9, 0, rte_cpu_to_be_32(mkey_job->imkey->id)); /* Set UMR WQE control seg. */ ucseg->mkey_mask |= rte_cpu_to_be_64(MLX5_WQE_UMR_CTRL_MKEY_MASK_LEN | @@ -287,37 +287,37 @@ complete_umr_wqe(struct mlx5_regex_qp *qp, struct mlx5_regex_sq *sq, } static inline void -prep_nop_regex_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq, - struct rte_regex_ops *op, struct mlx5_regex_job *job, - size_t pi, struct mlx5_klm *klm) +prep_nop_regex_wqe_set(struct mlx5_regex_priv *priv, + struct mlx5_regex_hw_qp *qp, struct rte_regex_ops *op, + struct mlx5_regex_job *job, size_t pi, struct mlx5_klm *klm) { - size_t wqe_offset = (pi & (sq_size_get(sq) - 1)) * + size_t wqe_offset = (pi & (qp_size_get(qp) - 1)) * (MLX5_SEND_WQE_BB << 2); struct mlx5_wqe_ctrl_seg *wqe = (struct mlx5_wqe_ctrl_seg *)((uint8_t *) - (uintptr_t)sq->sq_obj.wqes + wqe_offset); + (uintptr_t)qp->qp_obj.wqes + wqe_offset); /* Clear the WQE memory used as UMR WQE previously. */ if ((rte_be_to_cpu_32(wqe->opmod_idx_opcode) & 0xff) != MLX5_OPCODE_NOP) memset(wqe, 0, MLX5_REGEX_UMR_WQE_SIZE); /* UMR WQE size is 9 DS, align nop WQE to 3 WQEBBS(12 DS). */ - set_wqe_ctrl_seg(wqe, pi * 4, MLX5_OPCODE_NOP, 0, sq->sq_obj.sq->id, + set_wqe_ctrl_seg(wqe, pi * 4, MLX5_OPCODE_NOP, 0, qp->qp_obj.qp->id, 0, 12, 0, 0); - __prep_one(priv, sq, op, job, pi, klm); + __prep_one(priv, qp, op, job, pi, klm); } static inline void prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, - struct mlx5_regex_sq *sq, struct rte_regex_ops **op, size_t nb_ops) + struct mlx5_regex_hw_qp *qp_obj, struct rte_regex_ops **op, + size_t nb_ops) { struct mlx5_regex_job *job = NULL; - size_t sqid = sq->sqn, mkey_job_id = 0; + size_t hw_qpid = qp_obj->qpn, mkey_job_id = 0; size_t left_ops = nb_ops; uint32_t klm_num = 0; uint32_t len = 0; struct mlx5_klm *mkey_klm = NULL; struct mlx5_klm klm; - sqid = sq->sqn; while (left_ops--) rte_prefetch0(op[left_ops]); left_ops = nb_ops; @@ -329,7 +329,7 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, */ while (left_ops--) { struct rte_mbuf *mbuf = op[left_ops]->mbuf; - size_t pi = MLX5_REGEX_UMR_SQ_PI_IDX(sq->pi, left_ops); + size_t pi = MLX5_REGEX_UMR_QP_PI_IDX(qp_obj->pi, left_ops); if (mbuf->nb_segs > 1) { size_t scatter_size = 0; @@ -341,16 +341,16 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, * WQE in the next WQE set. */ if (mkey_klm) - complete_umr_wqe(qp, sq, + complete_umr_wqe(qp, qp_obj, &qp->jobs[mkey_job_id], - MLX5_REGEX_UMR_SQ_PI_IDX(pi, 1), + MLX5_REGEX_UMR_QP_PI_IDX(pi, 1), klm_num, len); /* * Get the indircet mkey and KLM array index * from the last WQE set. */ - mkey_job_id = job_id_get(sqid, - sq_size_get(sq), pi); + mkey_job_id = job_id_get(hw_qpid, + qp_size_get(qp_obj), pi); mkey_klm = qp->jobs[mkey_job_id].imkey_array; klm_num = 0; len = 0; @@ -384,22 +384,23 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, klm.address = rte_pktmbuf_mtod(mbuf, uintptr_t); klm.byte_count = rte_pktmbuf_data_len(mbuf); } - job = &qp->jobs[job_id_get(sqid, sq_size_get(sq), pi)]; + job = &qp->jobs[job_id_get(hw_qpid, qp_size_get(qp_obj), pi)]; /* * Build the nop + RegEx WQE set by default. The fist nop WQE * will be updated later as UMR WQE if scattered mubf exist. */ - prep_nop_regex_wqe_set(priv, sq, op[left_ops], job, pi, &klm); + prep_nop_regex_wqe_set(priv, qp_obj, op[left_ops], job, pi, + &klm); } /* * Scattered mbuf have been added to the KLM array. Complete the build * of UMR WQE, update the first nop WQE as UMR WQE. */ if (mkey_klm) - complete_umr_wqe(qp, sq, &qp->jobs[mkey_job_id], sq->pi, + complete_umr_wqe(qp, qp_obj, &qp->jobs[mkey_job_id], qp_obj->pi, klm_num, len); - sq->db_pi = MLX5_REGEX_UMR_SQ_PI_IDX(sq->pi, nb_ops - 1); - sq->pi = MLX5_REGEX_UMR_SQ_PI_IDX(sq->pi, nb_ops); + qp_obj->db_pi = MLX5_REGEX_UMR_QP_PI_IDX(qp_obj->pi, nb_ops - 1); + qp_obj->pi = MLX5_REGEX_UMR_QP_PI_IDX(qp_obj->pi, nb_ops); } uint16_t @@ -408,21 +409,22 @@ mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id, { struct mlx5_regex_priv *priv = dev->data->dev_private; struct mlx5_regex_qp *queue = &priv->qps[qp_id]; - struct mlx5_regex_sq *sq; - size_t sqid, nb_left = nb_ops, nb_desc; + struct mlx5_regex_hw_qp *qp_obj; + size_t hw_qpid, nb_left = nb_ops, nb_desc; - while ((sqid = ffs(queue->free_sqs))) { - sqid--; /* ffs returns 1 for bit 0 */ - sq = &queue->sqs[sqid]; - nb_desc = get_free(sq, priv->has_umr); + while ((hw_qpid = ffs(queue->free_qps))) { + hw_qpid--; /* ffs returns 1 for bit 0 */ + qp_obj = &queue->qps[hw_qpid]; + nb_desc = get_free(qp_obj, priv->has_umr); if (nb_desc) { /* The ops be handled can't exceed nb_ops. */ if (nb_desc > nb_left) nb_desc = nb_left; else - queue->free_sqs &= ~(1 << sqid); - prep_regex_umr_wqe_set(priv, queue, sq, ops, nb_desc); - send_doorbell(priv, sq); + queue->free_qps &= ~(1 << hw_qpid); + prep_regex_umr_wqe_set(priv, queue, qp_obj, ops, + nb_desc); + send_doorbell(priv, qp_obj); nb_left -= nb_desc; } if (!nb_left) @@ -441,23 +443,25 @@ mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, { struct mlx5_regex_priv *priv = dev->data->dev_private; struct mlx5_regex_qp *queue = &priv->qps[qp_id]; - struct mlx5_regex_sq *sq; - size_t sqid, job_id, i = 0; - - while ((sqid = ffs(queue->free_sqs))) { - sqid--; /* ffs returns 1 for bit 0 */ - sq = &queue->sqs[sqid]; - while (get_free(sq, priv->has_umr)) { - job_id = job_id_get(sqid, sq_size_get(sq), sq->pi); - prep_one(priv, queue, sq, ops[i], &queue->jobs[job_id]); + struct mlx5_regex_hw_qp *qp_obj; + size_t hw_qpid, job_id, i = 0; + + while ((hw_qpid = ffs(queue->free_qps))) { + hw_qpid--; /* ffs returns 1 for bit 0 */ + qp_obj = &queue->qps[hw_qpid]; + while (get_free(qp_obj, priv->has_umr)) { + job_id = job_id_get(hw_qpid, qp_size_get(qp_obj), + qp_obj->pi); + prep_one(priv, queue, qp_obj, ops[i], + &queue->jobs[job_id]); i++; if (unlikely(i == nb_ops)) { - send_doorbell(priv, sq); + send_doorbell(priv, qp_obj); goto out; } } - queue->free_sqs &= ~(1 << sqid); - send_doorbell(priv, sq); + queue->free_qps &= ~(1 << hw_qpid); + send_doorbell(priv, qp_obj); } out: @@ -567,21 +571,21 @@ mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, uint16_t wq_counter = (rte_be_to_cpu_16(cqe->wqe_counter) + 1) & MLX5_REGEX_MAX_WQE_INDEX; - size_t sqid = cqe->rsvd3[2]; - struct mlx5_regex_sq *sq = &queue->sqs[sqid]; + size_t hw_qpid = cqe->rsvd3[2]; + struct mlx5_regex_hw_qp *qp_obj = &queue->qps[hw_qpid]; /* UMR mode WQE counter move as WQE set(4 WQEBBS).*/ if (priv->has_umr) wq_counter >>= 2; - while (sq->ci != wq_counter) { + while (qp_obj->ci != wq_counter) { if (unlikely(i == nb_ops)) { /* Return without updating cq->ci */ goto out; } - uint32_t job_id = job_id_get(sqid, sq_size_get(sq), - sq->ci); + uint32_t job_id = job_id_get(hw_qpid, + qp_size_get(qp_obj), qp_obj->ci); extract_result(ops[i], &queue->jobs[job_id]); - sq->ci = (sq->ci + 1) & (priv->has_umr ? + qp_obj->ci = (qp_obj->ci + 1) & (priv->has_umr ? (MLX5_REGEX_MAX_WQE_INDEX >> 2) : MLX5_REGEX_MAX_WQE_INDEX); i++; @@ -589,7 +593,7 @@ mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, cq->ci = (cq->ci + 1) & 0xffffff; rte_wmb(); cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->ci); - queue->free_sqs |= (1 << sqid); + queue->free_qps |= (1 << hw_qpid); } out: @@ -598,15 +602,15 @@ mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, } static void -setup_sqs(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *queue) +setup_qps(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *queue) { - size_t sqid, entry; + size_t hw_qpid, entry; uint32_t job_id; - for (sqid = 0; sqid < queue->nb_obj; sqid++) { - struct mlx5_regex_sq *sq = &queue->sqs[sqid]; - uint8_t *wqe = (uint8_t *)(uintptr_t)sq->sq_obj.wqes; - for (entry = 0 ; entry < sq_size_get(sq); entry++) { - job_id = sqid * sq_size_get(sq) + entry; + for (hw_qpid = 0; hw_qpid < queue->nb_obj; hw_qpid++) { + struct mlx5_regex_hw_qp *qp_obj = &queue->qps[hw_qpid]; + uint8_t *wqe = (uint8_t *)(uintptr_t)qp_obj->qp_obj.wqes; + for (entry = 0 ; entry < qp_size_get(qp_obj); entry++) { + job_id = hw_qpid * qp_size_get(qp_obj) + entry; struct mlx5_regex_job *job = &queue->jobs[job_id]; /* Fill UMR WQE with NOP in advanced. */ @@ -614,7 +618,7 @@ setup_sqs(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *queue) set_wqe_ctrl_seg ((struct mlx5_wqe_ctrl_seg *)wqe, entry * 2, MLX5_OPCODE_NOP, 0, - sq->sq_obj.sq->id, 0, 12, 0, 0); + qp_obj->qp_obj.qp->id, 0, 12, 0, 0); wqe += MLX5_REGEX_UMR_WQE_SIZE; } set_metadata_seg((struct mlx5_wqe_metadata_seg *) @@ -628,7 +632,7 @@ setup_sqs(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *queue) (uintptr_t)job->output); wqe += 64; } - queue->free_sqs |= 1 << sqid; + queue->free_qps |= 1 << hw_qpid; } } @@ -738,7 +742,7 @@ mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) return err; } - setup_sqs(priv, qp); + setup_qps(priv, qp); if (priv->has_umr) { #ifdef HAVE_IBV_FLOW_DV_SUPPORT From patchwork Thu Sep 30 05:44:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raja Zidane X-Patchwork-Id: 100052 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5016BA0C41; Thu, 30 Sep 2021 07:45:33 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4F59F41145; Thu, 30 Sep 2021 07:45:23 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2063.outbound.protection.outlook.com [40.107.94.63]) by mails.dpdk.org (Postfix) with ESMTP id CC025410FA for ; Thu, 30 Sep 2021 07:45:04 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=cSp++tqmv9eIlZRILUmv3HRQ6GlTdgMDv5w4aOxsAOcf4Y4QxIBCKJQMMVHRPg2QmqGHiviR0xNLAihz8f2Yp/A1PBTLZDARXT6GJV25xWUwoXiyRFrWNV4UAZvAVutL6vVUsqN6LEL9l3znMBa+pxTuHqmqyE5tNt8ImNNRaMEYHT8Y7wnAKelFj0lwmrfxuRZk8DmYwPr8zFbxC3Q+RyiK0nxCQe2Jva8Puooj8yB2Bu+RcnBVPrRxgN0B1RfUaFybXM51m8ti1gkOEKVyyH5TpOu3deWB+Lt+TzdTOp1nA59W2Fhm4n8Mo1Ob6KuS4c0EES51fdqosogWUSvaow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=RiYHv+HV0dZ/CNej3wrfO6f38NTGvUZZ9wqcf5cGNMU=; b=hNtgJsgobUqKJQOY7CrIB3DB4S3wuXaiYQ/4W7Coh/u2dK+8yANBZTAxWXdfin7PXUZaVON7hdheBPQlypyWlCxi4A7rseURz/TNRB2Y1Dr123oD8iZodCxCvRwHjrviWl+o74/KofSdYT9qS0OMnAdlNh/ReMf8vMfacehePiW0vzX9XQav4MOJRqalhrVpwRns6GL3AzsW8js01h0KeYQcF6EFaY7tq3OGLVxIDAbFojK0/q36UieVHNOkG3+RtwciAwAOtVfEcFSOxH6x+QMy/dkabzZndIv8hkiNVH2/fPkNknUDcdSEjdowh4UsLYmsRDzh5d8PmfXmav5oRA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RiYHv+HV0dZ/CNej3wrfO6f38NTGvUZZ9wqcf5cGNMU=; b=IXNMHhbakQANoeyaGXKfjJtbfS62bB0iii7rz6d4eeYgC1sv/i3piv1LeI848PBPeg7xVs4XWtLbTkU+5lYbi/ALlUfRqBao/7HXSW9J2gxbzm6pZs1/2UvVDCu3O5oVy1ar60TpZ5+6SETn7KMsJ/wuPK7bD9LUAvCtlpn63PsnuZZyl23qBWIWhGgga1y96Mac/LWsjNuubrXvs+ppvV2rUjuIsXE02DWBJKWhdR0d0tG9XwTAX14hBSewXAygTPORq9mLgtKzP1p9SQFwK5npBxhptFrPWQIvHH9b7X0RUK6IpR4oaIgd43cLUeMc069VFav7XQM82oxnRG1Y2A== Received: from CO2PR06CA0061.namprd06.prod.outlook.com (2603:10b6:104:3::19) by MWHPR12MB1199.namprd12.prod.outlook.com (2603:10b6:300:10::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.14; Thu, 30 Sep 2021 05:45:02 +0000 Received: from CO1NAM11FT060.eop-nam11.prod.protection.outlook.com (2603:10b6:104:3:cafe::7b) by CO2PR06CA0061.outlook.office365.com (2603:10b6:104:3::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 05:45:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT060.mail.protection.outlook.com (10.13.175.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 05:45:02 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 05:44:59 +0000 From: Raja Zidane To: Date: Thu, 30 Sep 2021 05:44:38 +0000 Message-ID: <20210930054438.5960-6-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210930054438.5960-1-rzidane@nvidia.com> References: <20210928121650.40181-1-rzidane@nvidia.com> <20210930054438.5960-1-rzidane@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b535c710-4a2a-4846-0d85-08d983d57279 X-MS-TrafficTypeDiagnostic: MWHPR12MB1199: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3044; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HFAxJ1CsFke+ixtkT0HOoZqUrgUanc86oAAFUln5Yslg8GMQ/mEwKknuvfnF6QbeTEQ2/ik+U4RUv+S19+BZ2urLVWd2IOEenoM2DDxh246UoppANFB1zYfhLMIU5FjEl+CRJns+Q2uv8HiblHDXmVzncVjaftaK9dzLHQowEQUC/STr3gz8P5mnnCFUNcMSgtFQMBfbD8boVeNBE9xbiuMFBfMBl3CqsktpRGQvUDc8Jz0td+uyhNfcoE782TrsnOyhRdnK31b6jqOne4nrNvI09NR3gI3iLQ9uJqM28LsQTkgngbxWpM7JahZeWkvBtumdIvWblkRyt4JfN9X9itEhqN3Jg/cfyI8Pw3nOh1CAMY3wFoR/QAa2xEvt54JenwMzLaqh0TYLVoxTo8tSm2kuRIei33Eco0dElEiLxN00EW/QuKA4pRitJNyWh+eTX2MBQMJWN4muovKvQSUwKFY6VMdhZb4CUt4sxj5fB7b2bN0vI8FkZVjhMgaJUi3AmMTybhRV0N2zF08w+lrIqz3d2xu1opxWVURdhiwX0baXabxdYuruiG9KWUmYSY4wvfdFbPzwyKiSyx7Fdl1GcRIA0Oe2VNjujdGJjrvIqzPOASxOeTGdUz6MX0+hmCoNuZ0HerKuhJF4UB6ZvamFqIUY6aZoYIV68rad6UUhZyquaRIAW+UpekyIvESpYNtKyB5Y9sBwojhMK1ePh7yrjw== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(47076005)(1076003)(6286002)(316002)(336012)(8676002)(36860700001)(8936002)(70586007)(7696005)(2616005)(70206006)(83380400001)(5660300002)(26005)(2906002)(508600001)(82310400003)(86362001)(7636003)(6666004)(426003)(186003)(16526019)(36756003)(356005)(55016002)(6916009); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2021 05:45:02.0425 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b535c710-4a2a-4846-0d85-08d983d57279 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1199 Subject: [dpdk-dev] [PATCH V5 5/5] compress/mlx5: allow partial transformations support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently compress, decompress and dma are allowed only when all 3 capabilities are on. A case where the user wants decompress offload, if decompress capability is on but one of compress, dma is off, is not allowed. Split compress/decompress/dma support check to allow partial transformations. Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/compress/mlx5/mlx5_compress.c | 61 ++++++++++++++++++++------- 1 file changed, 46 insertions(+), 15 deletions(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 5c5aa87a18..e94e8fb0c6 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -291,17 +291,44 @@ mlx5_compress_xform_create(struct rte_compressdev *dev, struct mlx5_compress_xform *xfrm; uint32_t size; - if (xform->type == RTE_COMP_COMPRESS && xform->compress.level == - RTE_COMP_LEVEL_NONE) { - DRV_LOG(ERR, "Non-compressed block is not supported."); - return -ENOTSUP; - } - if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo != - RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS && - xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) { - DRV_LOG(ERR, "SHA is not supported."); + switch (xform->type) { + case RTE_COMP_COMPRESS: + if (xform->compress.algo == RTE_COMP_ALGO_NULL && + !priv->mmo_dma_qp && !priv->mmo_dma_sq) { + DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?"); + return -ENOTSUP; + } else if (!priv->mmo_comp_qp && !priv->mmo_comp_sq) { + DRV_LOG(ERR, "Not enough capabilities to support compress operation, maybe old FW/OFED version?"); + return -ENOTSUP; + } + if (xform->compress.level == RTE_COMP_LEVEL_NONE) { + DRV_LOG(ERR, "Non-compressed block is not supported."); + return -ENOTSUP; + } + if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) { + DRV_LOG(ERR, "SHA is not supported."); + return -ENOTSUP; + } + break; + case RTE_COMP_DECOMPRESS: + if (xform->decompress.algo == RTE_COMP_ALGO_NULL && + !priv->mmo_dma_qp && !priv->mmo_dma_sq) { + DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?"); + return -ENOTSUP; + } else if (!priv->mmo_decomp_qp && !priv->mmo_decomp_sq) { + DRV_LOG(ERR, "Not enough capabilities to support decompress operation, maybe old FW/OFED version?"); + return -ENOTSUP; + } + if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) { + DRV_LOG(ERR, "SHA is not supported."); + return -ENOTSUP; + } + break; + default: + DRV_LOG(ERR, "Xform type should be compress/decompress"); return -ENOTSUP; } + xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0, priv->dev_config.socket_id); if (xfrm == NULL) @@ -816,12 +843,16 @@ mlx5_compress_dev_probe(struct rte_device *dev) rte_errno = ENODEV; return -rte_errno; } - if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 || - ((att.mmo_compress_sq_en == 0 || att.mmo_decompress_sq_en == 0 || - att.mmo_dma_sq_en == 0) && (att.mmo_compress_qp_en == 0 || - att.mmo_decompress_qp_en == 0 || att.mmo_dma_qp_en == 0))) { - DRV_LOG(ERR, "Not enough capabilities to support compress " - "operations, maybe old FW/OFED version?"); + if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0) { + DRV_LOG(ERR, "Failed to query device capabilities"); + claim_zero(mlx5_glue->close_device(ctx)); + rte_errno = ENOTSUP; + return -ENOTSUP; + } + if (!att.mmo_decompress_qp_en && !att.mmo_decompress_sq_en + && !att.mmo_compress_qp_en && !att.mmo_compress_sq_en + && !att.mmo_dma_qp_en && !att.mmo_dma_sq_en) { + DRV_LOG(ERR, "Not enough capabilities to support compress operations, maybe old FW/OFED version?"); claim_zero(mlx5_glue->close_device(ctx)); rte_errno = ENOTSUP; return -ENOTSUP;