From patchwork Mon Oct 11 12:43:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 101028 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 015E5A034F; Mon, 11 Oct 2021 14:43:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DB367410E0; Mon, 11 Oct 2021 14:43:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 66FC4410E0 for ; Mon, 11 Oct 2021 14:43:35 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19BCYKZP002406; Mon, 11 Oct 2021 05:43:28 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=/svIw+bhLdxGjSGF3I4JUsbFhlndO2vigSjNHJliUH8=; b=bLRk1Td7U27bjvtaRwR2Z1n8+exvaKwV6qmJQTMqoSjjYYyLOV0iJm+HztDeMmB5454B yeCjmJi2ve760UsT4Im9GmRKIEfTPh+dtSfxsU9OZ5c4TFuSmkM1MWjDhqzYA2xdCMsa WW3IgnGziCiQwoheNjmsLSH6DOlbMXLfOFW4DucEZ3VTDQf8jToNorL8xhN8Engf5yq+ Q5OVzJx8fZLd+dyPgamcJ/iF/E5F1b1+nd7ZNE8WyQh2qarImw5qO9i9f7JB0hw9xKay G2oI5eCGx9HT/HOTcXmhxXdU1zBcZeJxMYC3l0zbhLyH5Zdwy8DQA1rf6nECd+C/GRIW Ow== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 3bmaa5tayx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 11 Oct 2021 05:43:28 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 11 Oct 2021 05:43:27 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 11 Oct 2021 05:43:26 -0700 Received: from localhost.localdomain (unknown [10.28.36.185]) by maili.marvell.com (Postfix) with ESMTP id AD6C03F707E; Mon, 11 Oct 2021 05:43:21 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , , , , , , , , , , , , , , Akhil Goyal Date: Mon, 11 Oct 2021 18:13:05 +0530 Message-ID: <20211011124309.4066491-2-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011124309.4066491-1-gakhil@marvell.com> References: <20210829125139.2173235-1-gakhil@marvell.com> <20211011124309.4066491-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 2gxL2vojCqdrC4yeBqK8_WWjsW2Ze95N X-Proofpoint-ORIG-GUID: 2gxL2vojCqdrC4yeBqK8_WWjsW2Ze95N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-11_04,2021-10-07_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 1/5] cryptodev: separate out internal structures X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" A new header file rte_cryptodev_core.h is added and all internal data structures which need not be exposed directly to application are moved to this file. These structures are mostly used by drivers, but they need to be in the public header file as they are accessed by datapath inline functions for performance reasons. Signed-off-by: Akhil Goyal Acked-by: Fan Zhang --- lib/cryptodev/cryptodev_pmd.h | 6 - lib/cryptodev/meson.build | 4 +- lib/cryptodev/rte_cryptodev.h | 360 ++++++++++++----------------- lib/cryptodev/rte_cryptodev_core.h | 100 ++++++++ 4 files changed, 245 insertions(+), 225 deletions(-) create mode 100644 lib/cryptodev/rte_cryptodev_core.h diff --git a/lib/cryptodev/cryptodev_pmd.h b/lib/cryptodev/cryptodev_pmd.h index 8cc9051e09..36606dd10b 100644 --- a/lib/cryptodev/cryptodev_pmd.h +++ b/lib/cryptodev/cryptodev_pmd.h @@ -92,12 +92,6 @@ __rte_internal struct rte_cryptodev * rte_cryptodev_pmd_get_named_dev(const char *name); -/** - * The pool of rte_cryptodev structures. - */ -extern struct rte_cryptodev *rte_cryptodevs; - - /** * Definitions of all functions exported by a driver through the * the generic structure of type *crypto_dev_ops* supplied in the diff --git a/lib/cryptodev/meson.build b/lib/cryptodev/meson.build index 51371c3aa2..289b66ab76 100644 --- a/lib/cryptodev/meson.build +++ b/lib/cryptodev/meson.build @@ -14,7 +14,9 @@ headers = files( 'rte_crypto_sym.h', 'rte_crypto_asym.h', ) - +indirect_headers += files( + 'rte_cryptodev_core.h', +) driver_sdk_headers += files( 'cryptodev_pmd.h', ) diff --git a/lib/cryptodev/rte_cryptodev.h b/lib/cryptodev/rte_cryptodev.h index cdd7168fba..ce0dca72be 100644 --- a/lib/cryptodev/rte_cryptodev.h +++ b/lib/cryptodev/rte_cryptodev.h @@ -867,17 +867,6 @@ rte_cryptodev_callback_unregister(uint8_t dev_id, enum rte_cryptodev_event_type event, rte_cryptodev_cb_fn cb_fn, void *cb_arg); -typedef uint16_t (*dequeue_pkt_burst_t)(void *qp, - struct rte_crypto_op **ops, uint16_t nb_ops); -/**< Dequeue processed packets from queue pair of a device. */ - -typedef uint16_t (*enqueue_pkt_burst_t)(void *qp, - struct rte_crypto_op **ops, uint16_t nb_ops); -/**< Enqueue packets for processing on queue pair of a device. */ - - - - struct rte_cryptodev_callback; /** Structure to keep track of registered callbacks */ @@ -907,216 +896,9 @@ struct rte_cryptodev_cb_rcu { /**< RCU QSBR variable per queue pair */ }; -/** The data structure associated with each crypto device. */ -struct rte_cryptodev { - dequeue_pkt_burst_t dequeue_burst; - /**< Pointer to PMD receive function. */ - enqueue_pkt_burst_t enqueue_burst; - /**< Pointer to PMD transmit function. */ - - struct rte_cryptodev_data *data; - /**< Pointer to device data */ - struct rte_cryptodev_ops *dev_ops; - /**< Functions exported by PMD */ - uint64_t feature_flags; - /**< Feature flags exposes HW/SW features for the given device */ - struct rte_device *device; - /**< Backing device */ - - uint8_t driver_id; - /**< Crypto driver identifier*/ - - struct rte_cryptodev_cb_list link_intr_cbs; - /**< User application callback for interrupts if present */ - - void *security_ctx; - /**< Context for security ops */ - - __extension__ - uint8_t attached : 1; - /**< Flag indicating the device is attached */ - - struct rte_cryptodev_cb_rcu *enq_cbs; - /**< User application callback for pre enqueue processing */ - - struct rte_cryptodev_cb_rcu *deq_cbs; - /**< User application callback for post dequeue processing */ -} __rte_cache_aligned; - void * rte_cryptodev_get_sec_ctx(uint8_t dev_id); -/** - * - * The data part, with no function pointers, associated with each device. - * - * This structure is safe to place in shared memory to be common among - * different processes in a multi-process configuration. - */ -struct rte_cryptodev_data { - uint8_t dev_id; - /**< Device ID for this instance */ - uint8_t socket_id; - /**< Socket ID where memory is allocated */ - char name[RTE_CRYPTODEV_NAME_MAX_LEN]; - /**< Unique identifier name */ - - __extension__ - uint8_t dev_started : 1; - /**< Device state: STARTED(1)/STOPPED(0) */ - - struct rte_mempool *session_pool; - /**< Session memory pool */ - void **queue_pairs; - /**< Array of pointers to queue pairs. */ - uint16_t nb_queue_pairs; - /**< Number of device queue pairs. */ - - void *dev_private; - /**< PMD-specific private data */ -} __rte_cache_aligned; - -extern struct rte_cryptodev *rte_cryptodevs; -/** - * - * Dequeue a burst of processed crypto operations from a queue on the crypto - * device. The dequeued operation are stored in *rte_crypto_op* structures - * whose pointers are supplied in the *ops* array. - * - * The rte_cryptodev_dequeue_burst() function returns the number of ops - * actually dequeued, which is the number of *rte_crypto_op* data structures - * effectively supplied into the *ops* array. - * - * A return value equal to *nb_ops* indicates that the queue contained - * at least *nb_ops* operations, and this is likely to signify that other - * processed operations remain in the devices output queue. Applications - * implementing a "retrieve as many processed operations as possible" policy - * can check this specific case and keep invoking the - * rte_cryptodev_dequeue_burst() function until a value less than - * *nb_ops* is returned. - * - * The rte_cryptodev_dequeue_burst() function does not provide any error - * notification to avoid the corresponding overhead. - * - * @param dev_id The symmetric crypto device identifier - * @param qp_id The index of the queue pair from which to - * retrieve processed packets. The value must be - * in the range [0, nb_queue_pair - 1] previously - * supplied to rte_cryptodev_configure(). - * @param ops The address of an array of pointers to - * *rte_crypto_op* structures that must be - * large enough to store *nb_ops* pointers in it. - * @param nb_ops The maximum number of operations to dequeue. - * - * @return - * - The number of operations actually dequeued, which is the number - * of pointers to *rte_crypto_op* structures effectively supplied to the - * *ops* array. - */ -static inline uint16_t -rte_cryptodev_dequeue_burst(uint8_t dev_id, uint16_t qp_id, - struct rte_crypto_op **ops, uint16_t nb_ops) -{ - struct rte_cryptodev *dev = &rte_cryptodevs[dev_id]; - - rte_cryptodev_trace_dequeue_burst(dev_id, qp_id, (void **)ops, nb_ops); - nb_ops = (*dev->dequeue_burst) - (dev->data->queue_pairs[qp_id], ops, nb_ops); -#ifdef RTE_CRYPTO_CALLBACKS - if (unlikely(dev->deq_cbs != NULL)) { - struct rte_cryptodev_cb_rcu *list; - struct rte_cryptodev_cb *cb; - - /* __ATOMIC_RELEASE memory order was used when the - * call back was inserted into the list. - * Since there is a clear dependency between loading - * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is - * not required. - */ - list = &dev->deq_cbs[qp_id]; - rte_rcu_qsbr_thread_online(list->qsbr, 0); - cb = __atomic_load_n(&list->next, __ATOMIC_RELAXED); - - while (cb != NULL) { - nb_ops = cb->fn(dev_id, qp_id, ops, nb_ops, - cb->arg); - cb = cb->next; - }; - - rte_rcu_qsbr_thread_offline(list->qsbr, 0); - } -#endif - return nb_ops; -} - -/** - * Enqueue a burst of operations for processing on a crypto device. - * - * The rte_cryptodev_enqueue_burst() function is invoked to place - * crypto operations on the queue *qp_id* of the device designated by - * its *dev_id*. - * - * The *nb_ops* parameter is the number of operations to process which are - * supplied in the *ops* array of *rte_crypto_op* structures. - * - * The rte_cryptodev_enqueue_burst() function returns the number of - * operations it actually enqueued for processing. A return value equal to - * *nb_ops* means that all packets have been enqueued. - * - * @param dev_id The identifier of the device. - * @param qp_id The index of the queue pair which packets are - * to be enqueued for processing. The value - * must be in the range [0, nb_queue_pairs - 1] - * previously supplied to - * *rte_cryptodev_configure*. - * @param ops The address of an array of *nb_ops* pointers - * to *rte_crypto_op* structures which contain - * the crypto operations to be processed. - * @param nb_ops The number of operations to process. - * - * @return - * The number of operations actually enqueued on the crypto device. The return - * value can be less than the value of the *nb_ops* parameter when the - * crypto devices queue is full or if invalid parameters are specified in - * a *rte_crypto_op*. - */ -static inline uint16_t -rte_cryptodev_enqueue_burst(uint8_t dev_id, uint16_t qp_id, - struct rte_crypto_op **ops, uint16_t nb_ops) -{ - struct rte_cryptodev *dev = &rte_cryptodevs[dev_id]; - -#ifdef RTE_CRYPTO_CALLBACKS - if (unlikely(dev->enq_cbs != NULL)) { - struct rte_cryptodev_cb_rcu *list; - struct rte_cryptodev_cb *cb; - - /* __ATOMIC_RELEASE memory order was used when the - * call back was inserted into the list. - * Since there is a clear dependency between loading - * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is - * not required. - */ - list = &dev->enq_cbs[qp_id]; - rte_rcu_qsbr_thread_online(list->qsbr, 0); - cb = __atomic_load_n(&list->next, __ATOMIC_RELAXED); - - while (cb != NULL) { - nb_ops = cb->fn(dev_id, qp_id, ops, nb_ops, - cb->arg); - cb = cb->next; - }; - - rte_rcu_qsbr_thread_offline(list->qsbr, 0); - } -#endif - - rte_cryptodev_trace_enqueue_burst(dev_id, qp_id, (void **)ops, nb_ops); - return (*dev->enqueue_burst)( - dev->data->queue_pairs[qp_id], ops, nb_ops); -} - - /** Cryptodev symmetric crypto session * Each session is derived from a fixed xform chain. Therefore each session * has a fixed algo, key, op-type, digest_len etc. @@ -2009,6 +1791,148 @@ int rte_cryptodev_remove_deq_callback(uint8_t dev_id, uint16_t qp_id, struct rte_cryptodev_cb *cb); +#include +/** + * + * Dequeue a burst of processed crypto operations from a queue on the crypto + * device. The dequeued operation are stored in *rte_crypto_op* structures + * whose pointers are supplied in the *ops* array. + * + * The rte_cryptodev_dequeue_burst() function returns the number of ops + * actually dequeued, which is the number of *rte_crypto_op* data structures + * effectively supplied into the *ops* array. + * + * A return value equal to *nb_ops* indicates that the queue contained + * at least *nb_ops* operations, and this is likely to signify that other + * processed operations remain in the devices output queue. Applications + * implementing a "retrieve as many processed operations as possible" policy + * can check this specific case and keep invoking the + * rte_cryptodev_dequeue_burst() function until a value less than + * *nb_ops* is returned. + * + * The rte_cryptodev_dequeue_burst() function does not provide any error + * notification to avoid the corresponding overhead. + * + * @param dev_id The symmetric crypto device identifier + * @param qp_id The index of the queue pair from which to + * retrieve processed packets. The value must be + * in the range [0, nb_queue_pair - 1] previously + * supplied to rte_cryptodev_configure(). + * @param ops The address of an array of pointers to + * *rte_crypto_op* structures that must be + * large enough to store *nb_ops* pointers in it. + * @param nb_ops The maximum number of operations to dequeue. + * + * @return + * - The number of operations actually dequeued, which is the number + * of pointers to *rte_crypto_op* structures effectively supplied to the + * *ops* array. + */ +static inline uint16_t +rte_cryptodev_dequeue_burst(uint8_t dev_id, uint16_t qp_id, + struct rte_crypto_op **ops, uint16_t nb_ops) +{ + struct rte_cryptodev *dev = &rte_cryptodevs[dev_id]; + + rte_cryptodev_trace_dequeue_burst(dev_id, qp_id, (void **)ops, nb_ops); + nb_ops = (*dev->dequeue_burst) + (dev->data->queue_pairs[qp_id], ops, nb_ops); +#ifdef RTE_CRYPTO_CALLBACKS + if (unlikely(dev->deq_cbs != NULL)) { + struct rte_cryptodev_cb_rcu *list; + struct rte_cryptodev_cb *cb; + + /* __ATOMIC_RELEASE memory order was used when the + * call back was inserted into the list. + * Since there is a clear dependency between loading + * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is + * not required. + */ + list = &dev->deq_cbs[qp_id]; + rte_rcu_qsbr_thread_online(list->qsbr, 0); + cb = __atomic_load_n(&list->next, __ATOMIC_RELAXED); + + while (cb != NULL) { + nb_ops = cb->fn(dev_id, qp_id, ops, nb_ops, + cb->arg); + cb = cb->next; + }; + + rte_rcu_qsbr_thread_offline(list->qsbr, 0); + } +#endif + return nb_ops; +} + +/** + * Enqueue a burst of operations for processing on a crypto device. + * + * The rte_cryptodev_enqueue_burst() function is invoked to place + * crypto operations on the queue *qp_id* of the device designated by + * its *dev_id*. + * + * The *nb_ops* parameter is the number of operations to process which are + * supplied in the *ops* array of *rte_crypto_op* structures. + * + * The rte_cryptodev_enqueue_burst() function returns the number of + * operations it actually enqueued for processing. A return value equal to + * *nb_ops* means that all packets have been enqueued. + * + * @param dev_id The identifier of the device. + * @param qp_id The index of the queue pair which packets are + * to be enqueued for processing. The value + * must be in the range [0, nb_queue_pairs - 1] + * previously supplied to + * *rte_cryptodev_configure*. + * @param ops The address of an array of *nb_ops* pointers + * to *rte_crypto_op* structures which contain + * the crypto operations to be processed. + * @param nb_ops The number of operations to process. + * + * @return + * The number of operations actually enqueued on the crypto device. The return + * value can be less than the value of the *nb_ops* parameter when the + * crypto devices queue is full or if invalid parameters are specified in + * a *rte_crypto_op*. + */ +static inline uint16_t +rte_cryptodev_enqueue_burst(uint8_t dev_id, uint16_t qp_id, + struct rte_crypto_op **ops, uint16_t nb_ops) +{ + struct rte_cryptodev *dev = &rte_cryptodevs[dev_id]; + +#ifdef RTE_CRYPTO_CALLBACKS + if (unlikely(dev->enq_cbs != NULL)) { + struct rte_cryptodev_cb_rcu *list; + struct rte_cryptodev_cb *cb; + + /* __ATOMIC_RELEASE memory order was used when the + * call back was inserted into the list. + * Since there is a clear dependency between loading + * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is + * not required. + */ + list = &dev->enq_cbs[qp_id]; + rte_rcu_qsbr_thread_online(list->qsbr, 0); + cb = __atomic_load_n(&list->next, __ATOMIC_RELAXED); + + while (cb != NULL) { + nb_ops = cb->fn(dev_id, qp_id, ops, nb_ops, + cb->arg); + cb = cb->next; + }; + + rte_rcu_qsbr_thread_offline(list->qsbr, 0); + } +#endif + + rte_cryptodev_trace_enqueue_burst(dev_id, qp_id, (void **)ops, nb_ops); + return (*dev->enqueue_burst)( + dev->data->queue_pairs[qp_id], ops, nb_ops); +} + + + #ifdef __cplusplus } #endif diff --git a/lib/cryptodev/rte_cryptodev_core.h b/lib/cryptodev/rte_cryptodev_core.h new file mode 100644 index 0000000000..1633e55889 --- /dev/null +++ b/lib/cryptodev/rte_cryptodev_core.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _RTE_CRYPTODEV_CORE_H_ +#define _RTE_CRYPTODEV_CORE_H_ + +/** + * @file + * + * RTE Crypto Device internal header. + * + * This header contains internal data types. But they are still part of the + * public API because they are used by inline functions in the published API. + * + * Applications should not use these directly. + * + */ + +typedef uint16_t (*dequeue_pkt_burst_t)(void *qp, + struct rte_crypto_op **ops, uint16_t nb_ops); +/**< Dequeue processed packets from queue pair of a device. */ + +typedef uint16_t (*enqueue_pkt_burst_t)(void *qp, + struct rte_crypto_op **ops, uint16_t nb_ops); +/**< Enqueue packets for processing on queue pair of a device. */ + +/** + * @internal + * The data part, with no function pointers, associated with each device. + * + * This structure is safe to place in shared memory to be common among + * different processes in a multi-process configuration. + */ +struct rte_cryptodev_data { + uint8_t dev_id; + /**< Device ID for this instance */ + uint8_t socket_id; + /**< Socket ID where memory is allocated */ + char name[RTE_CRYPTODEV_NAME_MAX_LEN]; + /**< Unique identifier name */ + + __extension__ + uint8_t dev_started : 1; + /**< Device state: STARTED(1)/STOPPED(0) */ + + struct rte_mempool *session_pool; + /**< Session memory pool */ + void **queue_pairs; + /**< Array of pointers to queue pairs. */ + uint16_t nb_queue_pairs; + /**< Number of device queue pairs. */ + + void *dev_private; + /**< PMD-specific private data */ +} __rte_cache_aligned; + + +/** @internal The data structure associated with each crypto device. */ +struct rte_cryptodev { + dequeue_pkt_burst_t dequeue_burst; + /**< Pointer to PMD receive function. */ + enqueue_pkt_burst_t enqueue_burst; + /**< Pointer to PMD transmit function. */ + + struct rte_cryptodev_data *data; + /**< Pointer to device data */ + struct rte_cryptodev_ops *dev_ops; + /**< Functions exported by PMD */ + uint64_t feature_flags; + /**< Feature flags exposes HW/SW features for the given device */ + struct rte_device *device; + /**< Backing device */ + + uint8_t driver_id; + /**< Crypto driver identifier*/ + + struct rte_cryptodev_cb_list link_intr_cbs; + /**< User application callback for interrupts if present */ + + void *security_ctx; + /**< Context for security ops */ + + __extension__ + uint8_t attached : 1; + /**< Flag indicating the device is attached */ + + struct rte_cryptodev_cb_rcu *enq_cbs; + /**< User application callback for pre enqueue processing */ + + struct rte_cryptodev_cb_rcu *deq_cbs; + /**< User application callback for post dequeue processing */ +} __rte_cache_aligned; + +/** + * The pool of rte_cryptodev structures. + */ +extern struct rte_cryptodev *rte_cryptodevs; + +#endif /* _RTE_CRYPTODEV_CORE_H_ */ From patchwork Mon Oct 11 12:43:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 101029 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6F463A034F; Mon, 11 Oct 2021 14:43:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 56233410E8; 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Mon, 11 Oct 2021 05:43:34 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 11 Oct 2021 05:43:33 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 11 Oct 2021 05:43:33 -0700 Received: from localhost.localdomain (unknown [10.28.36.185]) by maili.marvell.com (Postfix) with ESMTP id AAF373F7079; Mon, 11 Oct 2021 05:43:27 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , , , , , , , , , , , , , , Akhil Goyal Date: Mon, 11 Oct 2021 18:13:06 +0530 Message-ID: <20211011124309.4066491-3-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011124309.4066491-1-gakhil@marvell.com> References: <20210829125139.2173235-1-gakhil@marvell.com> <20211011124309.4066491-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: rsHjd6yyINIwwZOZr7qxQEHpTDVfx8w_ X-Proofpoint-ORIG-GUID: rsHjd6yyINIwwZOZr7qxQEHpTDVfx8w_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-11_04,2021-10-07_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 2/5] cryptodev: allocate max space for internal qp array X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" At queue_pair config stage, allocate memory for maximum number of queue pair pointers that a device can support. This will allow fast path APIs(enqueue_burst/dequeue_burst) to refer pointer to internal QP data without checking for currently configured QPs. This is required to hide the rte_cryptodev and rte_cryptodev_data structure from user. Signed-off-by: Akhil Goyal Acked-by: Fan Zhang --- lib/cryptodev/rte_cryptodev.c | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-) diff --git a/lib/cryptodev/rte_cryptodev.c b/lib/cryptodev/rte_cryptodev.c index b913c434c5..eb86e629aa 100644 --- a/lib/cryptodev/rte_cryptodev.c +++ b/lib/cryptodev/rte_cryptodev.c @@ -978,7 +978,8 @@ rte_cryptodev_queue_pairs_config(struct rte_cryptodev *dev, uint16_t nb_qpairs, if (dev->data->queue_pairs == NULL) { /* first time configuration */ dev->data->queue_pairs = rte_zmalloc_socket( "cryptodev->queue_pairs", - sizeof(dev->data->queue_pairs[0]) * nb_qpairs, + sizeof(dev->data->queue_pairs[0]) * + dev_info.max_nb_queue_pairs, RTE_CACHE_LINE_SIZE, socket_id); if (dev->data->queue_pairs == NULL) { @@ -1001,25 +1002,9 @@ rte_cryptodev_queue_pairs_config(struct rte_cryptodev *dev, uint16_t nb_qpairs, ret = (*dev->dev_ops->queue_pair_release)(dev, i); if (ret < 0) return ret; + qp[i] = NULL; } - qp = rte_realloc(qp, sizeof(qp[0]) * nb_qpairs, - RTE_CACHE_LINE_SIZE); - if (qp == NULL) { - CDEV_LOG_ERR("failed to realloc qp meta data," - " nb_queues %u", nb_qpairs); - return -(ENOMEM); - } - - if (nb_qpairs > old_nb_queues) { - uint16_t new_qs = nb_qpairs - old_nb_queues; - - memset(qp + old_nb_queues, 0, - sizeof(qp[0]) * new_qs); - } - - dev->data->queue_pairs = qp; - } dev->data->nb_queue_pairs = nb_qpairs; return 0; From patchwork Mon Oct 11 12:43:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 101030 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0577CA034F; Mon, 11 Oct 2021 14:43:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5751A410EA; Mon, 11 Oct 2021 14:43:48 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 6085D410DA for ; Mon, 11 Oct 2021 14:43:46 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19BC3CAW004117; Mon, 11 Oct 2021 05:43:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=5hpWvSEx4bqmTaqixe4Wi3FOgaoVWt5L3ED84iyYtv0=; b=gn62qDX4JUI8i8kqhMo1l9tWldik1leoFXSdtd6ng03qbevoo70zIskiJvSh//fk4eWh 4FuFNuuaZHK1ldI5TuiAGbaTvVnI/zPS63dSV4f9zXeIfzNSoqgmxKaDHWgLat6j7evz sByxHM4jYgjdQt3pN2aqsswJI0WizStFel6YEz1jfqQRZKpiT74s/ZIOf7e/EdFlZm9K 7TbKT6dmU7G/PmZZG/pfe95VSpj63m7CrFHz1D/UOFKV+j38nGGZgK/FWqL5Ueg4d50s IWhcReqW2Vxy8xD/GWJIVx6Jp25axUFMtoXP/zntF0GzAiZXzucUikLORQZHtLSHJXIp Jw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 3bmaa5tb18-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 11 Oct 2021 05:43:40 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 11 Oct 2021 05:43:39 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 11 Oct 2021 05:43:38 -0700 Received: from localhost.localdomain (unknown [10.28.36.185]) by maili.marvell.com (Postfix) with ESMTP id BA0B93F7080; Mon, 11 Oct 2021 05:43:33 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , , , , , , , , , , , , , , Akhil Goyal Date: Mon, 11 Oct 2021 18:13:07 +0530 Message-ID: <20211011124309.4066491-4-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011124309.4066491-1-gakhil@marvell.com> References: <20210829125139.2173235-1-gakhil@marvell.com> <20211011124309.4066491-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: z9RXoDsm5HY0326XhI-QYp5z2rJP2ES4 X-Proofpoint-ORIG-GUID: z9RXoDsm5HY0326XhI-QYp5z2rJP2ES4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-11_04,2021-10-07_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 3/5] cryptodev: move inline APIs into separate structure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Move fastpath inline function pointers from rte_cryptodev into a separate structure accessed via a flat array. The intension is to make rte_cryptodev and related structures private to avoid future API/ABI breakages. Signed-off-by: Akhil Goyal --- lib/cryptodev/cryptodev_pmd.c | 51 ++++++++++++++++++++++++++++++ lib/cryptodev/cryptodev_pmd.h | 11 +++++++ lib/cryptodev/rte_cryptodev.c | 29 +++++++++++++++++ lib/cryptodev/rte_cryptodev_core.h | 29 +++++++++++++++++ lib/cryptodev/version.map | 5 +++ 5 files changed, 125 insertions(+) diff --git a/lib/cryptodev/cryptodev_pmd.c b/lib/cryptodev/cryptodev_pmd.c index 44a70ecb35..4646708045 100644 --- a/lib/cryptodev/cryptodev_pmd.c +++ b/lib/cryptodev/cryptodev_pmd.c @@ -4,6 +4,7 @@ #include +#include #include #include @@ -160,3 +161,53 @@ rte_cryptodev_pmd_destroy(struct rte_cryptodev *cryptodev) return 0; } + +static uint16_t +dummy_crypto_enqueue_burst(__rte_unused void *qp, + __rte_unused struct rte_crypto_op **ops, + __rte_unused uint16_t nb_ops) +{ + CDEV_LOG_ERR( + "crypto enqueue burst requested for unconfigured device"); + rte_errno = ENOTSUP; + return 0; +} + +static uint16_t +dummy_crypto_dequeue_burst(__rte_unused void *qp, + __rte_unused struct rte_crypto_op **ops, + __rte_unused uint16_t nb_ops) +{ + CDEV_LOG_ERR( + "crypto dequeue burst requested for unconfigured device"); + rte_errno = ENOTSUP; + return 0; +} + +void +cryptodev_fp_ops_reset(struct rte_crypto_fp_ops *fp_ops) +{ + static void *dummy_data[RTE_MAX_QUEUES_PER_PORT]; + static const struct rte_crypto_fp_ops dummy = { + .enqueue_burst = dummy_crypto_enqueue_burst, + .dequeue_burst = dummy_crypto_dequeue_burst, + .qp = { + .data = dummy_data, + .enq_cb = dummy_data, + .deq_cb = dummy_data, + }, + }; + + *fp_ops = dummy; +} + +void +cryptodev_fp_ops_set(struct rte_crypto_fp_ops *fp_ops, + const struct rte_cryptodev *dev) +{ + fp_ops->enqueue_burst = dev->enqueue_burst; + fp_ops->dequeue_burst = dev->dequeue_burst; + fp_ops->qp.data = dev->data->queue_pairs; + fp_ops->qp.enq_cb = (void **)(uintptr_t)dev->enq_cbs; + fp_ops->qp.deq_cb = (void **)(uintptr_t)dev->deq_cbs; +} diff --git a/lib/cryptodev/cryptodev_pmd.h b/lib/cryptodev/cryptodev_pmd.h index 36606dd10b..a71edbb991 100644 --- a/lib/cryptodev/cryptodev_pmd.h +++ b/lib/cryptodev/cryptodev_pmd.h @@ -516,6 +516,17 @@ RTE_INIT(init_ ##driver_id)\ driver_id = rte_cryptodev_allocate_driver(&crypto_drv, &(drv));\ } +/* Reset crypto device fastpath APIs to dummy values. */ +__rte_internal +void +cryptodev_fp_ops_reset(struct rte_crypto_fp_ops *fp_ops); + +/* Setup crypto device fastpath APIs. */ +__rte_internal +void +cryptodev_fp_ops_set(struct rte_crypto_fp_ops *fp_ops, + const struct rte_cryptodev *dev); + static inline void * get_sym_session_private_data(const struct rte_cryptodev_sym_session *sess, uint8_t driver_id) { diff --git a/lib/cryptodev/rte_cryptodev.c b/lib/cryptodev/rte_cryptodev.c index eb86e629aa..2378892d40 100644 --- a/lib/cryptodev/rte_cryptodev.c +++ b/lib/cryptodev/rte_cryptodev.c @@ -53,6 +53,9 @@ static struct rte_cryptodev_global cryptodev_globals = { .nb_devs = 0 }; +/* Public fastpath APIs. */ +struct rte_crypto_fp_ops rte_crypto_fp_ops[RTE_CRYPTO_MAX_DEVS]; + /* spinlock for crypto device callbacks */ static rte_spinlock_t rte_cryptodev_cb_lock = RTE_SPINLOCK_INITIALIZER; @@ -903,6 +906,16 @@ rte_cryptodev_pmd_allocate(const char *name, int socket_id) cryptodev_globals.nb_devs++; } + /* + * for secondary process, at that point we expect device + * to be already 'usable', so shared data and all function + * pointers for fast-path devops have to be setup properly + * inside rte_cryptodev. + */ + if (rte_eal_process_type() == RTE_PROC_SECONDARY) + cryptodev_fp_ops_set(rte_crypto_fp_ops + + cryptodev->data->dev_id, cryptodev); + return cryptodev; } @@ -917,6 +930,8 @@ rte_cryptodev_pmd_release_device(struct rte_cryptodev *cryptodev) dev_id = cryptodev->data->dev_id; + cryptodev_fp_ops_reset(rte_crypto_fp_ops + dev_id); + /* Close device only if device operations have been set */ if (cryptodev->dev_ops) { ret = rte_cryptodev_close(dev_id); @@ -1080,6 +1095,9 @@ rte_cryptodev_start(uint8_t dev_id) } diag = (*dev->dev_ops->dev_start)(dev); + /* expose selection of PMD fast-path functions */ + cryptodev_fp_ops_set(rte_crypto_fp_ops + dev_id, dev); + rte_cryptodev_trace_start(dev_id, diag); if (diag == 0) dev->data->dev_started = 1; @@ -1109,6 +1127,9 @@ rte_cryptodev_stop(uint8_t dev_id) return; } + /* point fast-path functions to dummy ones */ + cryptodev_fp_ops_reset(rte_crypto_fp_ops + dev_id); + (*dev->dev_ops->dev_stop)(dev); rte_cryptodev_trace_stop(dev_id); dev->data->dev_started = 0; @@ -2411,3 +2432,11 @@ rte_cryptodev_allocate_driver(struct cryptodev_driver *crypto_drv, return nb_drivers++; } + +RTE_INIT(cryptodev_init_fp_ops) +{ + uint32_t i; + + for (i = 0; i != RTE_DIM(rte_crypto_fp_ops); i++) + cryptodev_fp_ops_reset(rte_crypto_fp_ops + i); +} diff --git a/lib/cryptodev/rte_cryptodev_core.h b/lib/cryptodev/rte_cryptodev_core.h index 1633e55889..bac5f8d984 100644 --- a/lib/cryptodev/rte_cryptodev_core.h +++ b/lib/cryptodev/rte_cryptodev_core.h @@ -25,6 +25,35 @@ typedef uint16_t (*enqueue_pkt_burst_t)(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops); /**< Enqueue packets for processing on queue pair of a device. */ +/** + * @internal + * Structure used to hold opaque pointers to internal ethdev Rx/Tx + * queues data. + * The main purpose to expose these pointers at all - allow compiler + * to fetch this data for fast-path cryptodev inline functions in advance. + */ +struct rte_cryptodev_qpdata { + /** points to array of internal queue pair data pointers. */ + void **data; + /** points to array of enqueue callback data pointers */ + void **enq_cb; + /** points to array of dequeue callback data pointers */ + void **deq_cb; +}; + +struct rte_crypto_fp_ops { + /** PMD enqueue burst function. */ + enqueue_pkt_burst_t enqueue_burst; + /** PMD dequeue burst function. */ + dequeue_pkt_burst_t dequeue_burst; + /** Internal queue pair data pointers. */ + struct rte_cryptodev_qpdata qp; + /** Reserved for future ops. */ + uintptr_t reserved[4]; +} __rte_cache_aligned; + +extern struct rte_crypto_fp_ops rte_crypto_fp_ops[RTE_CRYPTO_MAX_DEVS]; + /** * @internal * The data part, with no function pointers, associated with each device. diff --git a/lib/cryptodev/version.map b/lib/cryptodev/version.map index 43cf937e40..ed62ced221 100644 --- a/lib/cryptodev/version.map +++ b/lib/cryptodev/version.map @@ -45,6 +45,9 @@ DPDK_22 { rte_cryptodev_sym_session_init; rte_cryptodevs; + #added in 21.11 + rte_crypto_fp_ops; + local: *; }; @@ -109,6 +112,8 @@ EXPERIMENTAL { INTERNAL { global: + cryptodev_fp_ops_reset; + cryptodev_fp_ops_set; rte_cryptodev_allocate_driver; rte_cryptodev_pmd_allocate; rte_cryptodev_pmd_callback_process; From patchwork Mon Oct 11 12:43:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 101031 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 25944A0C43; Mon, 11 Oct 2021 14:43:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7EBEC41109; Mon, 11 Oct 2021 14:43:53 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id E2AD8410FC for ; Mon, 11 Oct 2021 14:43:51 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19BBgP6Y002410; Mon, 11 Oct 2021 05:43:46 -0700 DKIM-Signature: v=1; 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Mon, 11 Oct 2021 05:43:44 -0700 Received: from localhost.localdomain (unknown [10.28.36.185]) by maili.marvell.com (Postfix) with ESMTP id B71463F707B; Mon, 11 Oct 2021 05:43:39 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , , , , , , , , , , , , , , Akhil Goyal Date: Mon, 11 Oct 2021 18:13:08 +0530 Message-ID: <20211011124309.4066491-5-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011124309.4066491-1-gakhil@marvell.com> References: <20210829125139.2173235-1-gakhil@marvell.com> <20211011124309.4066491-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: m0Ukl-VY-iF3ujA-mEFLaqFxVrmrfuuk X-Proofpoint-ORIG-GUID: m0Ukl-VY-iF3ujA-mEFLaqFxVrmrfuuk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-11_04,2021-10-07_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 4/5] cryptodev: update fast path APIs to use new flat array X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Rework fast-path cryptodev functions to use rte_crypto_fp_ops[]. While it is an API/ABI breakage, this change is intended to be transparent for both users (no changes in user app is required) and PMD developers (no changes in PMD is required). Signed-off-by: Akhil Goyal Acked-by: Fan Zhang --- lib/cryptodev/rte_cryptodev.h | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/lib/cryptodev/rte_cryptodev.h b/lib/cryptodev/rte_cryptodev.h index ce0dca72be..739ad529e5 100644 --- a/lib/cryptodev/rte_cryptodev.h +++ b/lib/cryptodev/rte_cryptodev.h @@ -1832,13 +1832,18 @@ static inline uint16_t rte_cryptodev_dequeue_burst(uint8_t dev_id, uint16_t qp_id, struct rte_crypto_op **ops, uint16_t nb_ops) { - struct rte_cryptodev *dev = &rte_cryptodevs[dev_id]; + struct rte_crypto_fp_ops *fp_ops; + void *qp; rte_cryptodev_trace_dequeue_burst(dev_id, qp_id, (void **)ops, nb_ops); - nb_ops = (*dev->dequeue_burst) - (dev->data->queue_pairs[qp_id], ops, nb_ops); + + fp_ops = &rte_crypto_fp_ops[dev_id]; + qp = fp_ops->qp.data[qp_id]; + + nb_ops = fp_ops->dequeue_burst(qp, ops, nb_ops); + #ifdef RTE_CRYPTO_CALLBACKS - if (unlikely(dev->deq_cbs != NULL)) { + if (unlikely(fp_ops->qp.deq_cb != NULL)) { struct rte_cryptodev_cb_rcu *list; struct rte_cryptodev_cb *cb; @@ -1848,7 +1853,7 @@ rte_cryptodev_dequeue_burst(uint8_t dev_id, uint16_t qp_id, * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is * not required. */ - list = &dev->deq_cbs[qp_id]; + list = (struct rte_cryptodev_cb_rcu *)&fp_ops->qp.deq_cb[qp_id]; rte_rcu_qsbr_thread_online(list->qsbr, 0); cb = __atomic_load_n(&list->next, __ATOMIC_RELAXED); @@ -1899,10 +1904,13 @@ static inline uint16_t rte_cryptodev_enqueue_burst(uint8_t dev_id, uint16_t qp_id, struct rte_crypto_op **ops, uint16_t nb_ops) { - struct rte_cryptodev *dev = &rte_cryptodevs[dev_id]; + struct rte_crypto_fp_ops *fp_ops; + void *qp; + fp_ops = &rte_crypto_fp_ops[dev_id]; + qp = fp_ops->qp.data[qp_id]; #ifdef RTE_CRYPTO_CALLBACKS - if (unlikely(dev->enq_cbs != NULL)) { + if (unlikely(fp_ops->qp.enq_cb != NULL)) { struct rte_cryptodev_cb_rcu *list; struct rte_cryptodev_cb *cb; @@ -1912,7 +1920,7 @@ rte_cryptodev_enqueue_burst(uint8_t dev_id, uint16_t qp_id, * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is * not required. */ - list = &dev->enq_cbs[qp_id]; + list = (struct rte_cryptodev_cb_rcu *)&fp_ops->qp.enq_cb[qp_id]; rte_rcu_qsbr_thread_online(list->qsbr, 0); cb = __atomic_load_n(&list->next, __ATOMIC_RELAXED); @@ -1927,8 +1935,7 @@ rte_cryptodev_enqueue_burst(uint8_t dev_id, uint16_t qp_id, #endif rte_cryptodev_trace_enqueue_burst(dev_id, qp_id, (void **)ops, nb_ops); - return (*dev->enqueue_burst)( - dev->data->queue_pairs[qp_id], ops, nb_ops); + return fp_ops->enqueue_burst(qp, ops, nb_ops); } From patchwork Mon Oct 11 12:43:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 101032 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D6922A034F; Mon, 11 Oct 2021 14:44:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 90254410DC; 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Mon, 11 Oct 2021 05:43:52 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 11 Oct 2021 05:43:50 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 11 Oct 2021 05:43:50 -0700 Received: from localhost.localdomain (unknown [10.28.36.185]) by maili.marvell.com (Postfix) with ESMTP id AEE493F7082; Mon, 11 Oct 2021 05:43:45 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , , , , , , , , , , , , , , Akhil Goyal Date: Mon, 11 Oct 2021 18:13:09 +0530 Message-ID: <20211011124309.4066491-6-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011124309.4066491-1-gakhil@marvell.com> References: <20210829125139.2173235-1-gakhil@marvell.com> <20211011124309.4066491-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ICxawj71fnyPj86r6DClDB1eAMRWkaDY X-Proofpoint-ORIG-GUID: ICxawj71fnyPj86r6DClDB1eAMRWkaDY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-11_04,2021-10-07_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 5/5] cryptodev: move device specific structures X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The device specific structures - rte_cryptodev and rte_cryptodev_data are moved to cryptodev_pmd.h to hide it from the applications. Signed-off-by: Akhil Goyal Acked-by: Fan Zhang --- drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 1 - drivers/crypto/ccp/ccp_dev.h | 2 +- drivers/crypto/cnxk/cn10k_ipsec.c | 2 +- drivers/crypto/cnxk/cn9k_ipsec.c | 2 +- .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 2 +- drivers/crypto/cnxk/cnxk_cryptodev_sec.c | 2 +- drivers/crypto/nitrox/nitrox_sym_reqmgr.c | 2 +- drivers/crypto/octeontx/otx_cryptodev.c | 1 - .../crypto/octeontx/otx_cryptodev_hw_access.c | 2 +- .../crypto/octeontx/otx_cryptodev_hw_access.h | 2 +- drivers/crypto/octeontx/otx_cryptodev_ops.h | 2 +- .../crypto/octeontx2/otx2_cryptodev_mbox.c | 2 +- drivers/crypto/scheduler/scheduler_failover.c | 2 +- .../crypto/scheduler/scheduler_multicore.c | 2 +- .../scheduler/scheduler_pkt_size_distr.c | 2 +- .../crypto/scheduler/scheduler_roundrobin.c | 2 +- drivers/event/cnxk/cnxk_eventdev.h | 2 +- drivers/event/dpaa/dpaa_eventdev.c | 2 +- drivers/event/dpaa2/dpaa2_eventdev.c | 2 +- drivers/event/octeontx/ssovf_evdev.c | 2 +- .../event/octeontx2/otx2_evdev_crypto_adptr.c | 2 +- lib/cryptodev/cryptodev_pmd.h | 65 ++++++++++++++++++ lib/cryptodev/rte_cryptodev_core.h | 67 ------------------- lib/cryptodev/version.map | 2 +- 24 files changed, 85 insertions(+), 89 deletions(-) diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c index 60963a8208..bbf310166e 100644 --- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c +++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include diff --git a/drivers/crypto/ccp/ccp_dev.h b/drivers/crypto/ccp/ccp_dev.h index ca5145c278..85c8fc47a2 100644 --- a/drivers/crypto/ccp/ccp_dev.h +++ b/drivers/crypto/ccp/ccp_dev.h @@ -17,7 +17,7 @@ #include #include #include -#include +#include /**< CCP sspecific */ #define MAX_HW_QUEUES 5 diff --git a/drivers/crypto/cnxk/cn10k_ipsec.c b/drivers/crypto/cnxk/cn10k_ipsec.c index defc792aa8..27df1dcd64 100644 --- a/drivers/crypto/cnxk/cn10k_ipsec.c +++ b/drivers/crypto/cnxk/cn10k_ipsec.c @@ -3,7 +3,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/crypto/cnxk/cn9k_ipsec.c b/drivers/crypto/cnxk/cn9k_ipsec.c index 9ca4d20c62..53fb793654 100644 --- a/drivers/crypto/cnxk/cn9k_ipsec.c +++ b/drivers/crypto/cnxk/cn9k_ipsec.c @@ -2,7 +2,7 @@ * Copyright(C) 2021 Marvell. */ -#include +#include #include #include #include diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c index a227e6981c..a53b489a04 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c @@ -2,7 +2,7 @@ * Copyright(C) 2021 Marvell. */ -#include +#include #include #include "roc_api.h" diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_sec.c b/drivers/crypto/cnxk/cnxk_cryptodev_sec.c index 8d04d4b575..2021d5c77e 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_sec.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_sec.c @@ -2,7 +2,7 @@ * Copyright(C) 2021 Marvell. */ -#include +#include #include #include #include diff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c index fe3ca25a0c..9edb0cc00f 100644 --- a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c +++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c @@ -3,7 +3,7 @@ */ #include -#include +#include #include #include diff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c index c294f86d79..d09a17bb80 100644 --- a/drivers/crypto/octeontx/otx_cryptodev.c +++ b/drivers/crypto/octeontx/otx_cryptodev.c @@ -4,7 +4,6 @@ #include #include -#include #include #include #include diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c index 7b89a62d81..20b288334a 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c +++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c @@ -7,7 +7,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h index 7c6b1e45b4..e48805fb09 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h +++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h @@ -7,7 +7,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h index f234f16970..83b82ea059 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_ops.h +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h @@ -5,7 +5,7 @@ #ifndef _OTX_CRYPTODEV_OPS_H_ #define _OTX_CRYPTODEV_OPS_H_ -#include +#include #define OTX_CPT_MIN_HEADROOM_REQ (24) #define OTX_CPT_MIN_TAILROOM_REQ (8) diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c index 1a8edae7eb..f9e7b0b474 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright (C) 2019 Marvell International Ltd. */ -#include +#include #include #include "otx2_cryptodev.h" diff --git a/drivers/crypto/scheduler/scheduler_failover.c b/drivers/crypto/scheduler/scheduler_failover.c index 844312dd1b..5023577ef8 100644 --- a/drivers/crypto/scheduler/scheduler_failover.c +++ b/drivers/crypto/scheduler/scheduler_failover.c @@ -2,7 +2,7 @@ * Copyright(c) 2017 Intel Corporation */ -#include +#include #include #include "rte_cryptodev_scheduler_operations.h" diff --git a/drivers/crypto/scheduler/scheduler_multicore.c b/drivers/crypto/scheduler/scheduler_multicore.c index 1e2e8dbf9f..900ab4049d 100644 --- a/drivers/crypto/scheduler/scheduler_multicore.c +++ b/drivers/crypto/scheduler/scheduler_multicore.c @@ -3,7 +3,7 @@ */ #include -#include +#include #include #include "rte_cryptodev_scheduler_operations.h" diff --git a/drivers/crypto/scheduler/scheduler_pkt_size_distr.c b/drivers/crypto/scheduler/scheduler_pkt_size_distr.c index 57e330a744..933a5c6978 100644 --- a/drivers/crypto/scheduler/scheduler_pkt_size_distr.c +++ b/drivers/crypto/scheduler/scheduler_pkt_size_distr.c @@ -2,7 +2,7 @@ * Copyright(c) 2017 Intel Corporation */ -#include +#include #include #include "rte_cryptodev_scheduler_operations.h" diff --git a/drivers/crypto/scheduler/scheduler_roundrobin.c b/drivers/crypto/scheduler/scheduler_roundrobin.c index bc4a632106..ace2dec2ec 100644 --- a/drivers/crypto/scheduler/scheduler_roundrobin.c +++ b/drivers/crypto/scheduler/scheduler_roundrobin.c @@ -2,7 +2,7 @@ * Copyright(c) 2017 Intel Corporation */ -#include +#include #include #include "rte_cryptodev_scheduler_operations.h" diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 8a5c737e4b..b57004c0dc 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -7,7 +7,7 @@ #include -#include +#include #include #include #include diff --git a/drivers/event/dpaa/dpaa_eventdev.c b/drivers/event/dpaa/dpaa_eventdev.c index ec74160325..1d7ddfe1d1 100644 --- a/drivers/event/dpaa/dpaa_eventdev.c +++ b/drivers/event/dpaa/dpaa_eventdev.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c index 5ccf22f77f..e03afb2958 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev.c +++ b/drivers/event/dpaa2/dpaa2_eventdev.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/event/octeontx/ssovf_evdev.c b/drivers/event/octeontx/ssovf_evdev.c index b93f6ec8c6..9846fce34b 100644 --- a/drivers/event/octeontx/ssovf_evdev.c +++ b/drivers/event/octeontx/ssovf_evdev.c @@ -5,7 +5,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c index d9a002625c..d59d6c53f6 100644 --- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c +++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c @@ -2,7 +2,7 @@ * Copyright (C) 2020-2021 Marvell. */ -#include +#include #include #include "otx2_cryptodev.h" diff --git a/lib/cryptodev/cryptodev_pmd.h b/lib/cryptodev/cryptodev_pmd.h index a71edbb991..0d1bef0e67 100644 --- a/lib/cryptodev/cryptodev_pmd.h +++ b/lib/cryptodev/cryptodev_pmd.h @@ -52,6 +52,71 @@ struct rte_cryptodev_pmd_init_params { unsigned int max_nb_queue_pairs; }; +/** + * @internal + * The data part, with no function pointers, associated with each device. + * + * This structure is safe to place in shared memory to be common among + * different processes in a multi-process configuration. + */ +struct rte_cryptodev_data { + /** Device ID for this instance */ + uint8_t dev_id; + /** Socket ID where memory is allocated */ + uint8_t socket_id; + /** Unique identifier name */ + char name[RTE_CRYPTODEV_NAME_MAX_LEN]; + + __extension__ + /** Device state: STARTED(1)/STOPPED(0) */ + uint8_t dev_started : 1; + + /** Session memory pool */ + struct rte_mempool *session_pool; + /** Array of pointers to queue pairs. */ + void **queue_pairs; + /** Number of device queue pairs. */ + uint16_t nb_queue_pairs; + + /** PMD-specific private data */ + void *dev_private; +} __rte_cache_aligned; + +/** @internal The data structure associated with each crypto device. */ +struct rte_cryptodev { + /** Pointer to PMD dequeue function. */ + dequeue_pkt_burst_t dequeue_burst; + /** Pointer to PMD enqueue function. */ + enqueue_pkt_burst_t enqueue_burst; + + /** Pointer to device data */ + struct rte_cryptodev_data *data; + /** Functions exported by PMD */ + struct rte_cryptodev_ops *dev_ops; + /** Feature flags exposes HW/SW features for the given device */ + uint64_t feature_flags; + /** Backing device */ + struct rte_device *device; + + /** Crypto driver identifier*/ + uint8_t driver_id; + + /** User application callback for interrupts if present */ + struct rte_cryptodev_cb_list link_intr_cbs; + + /** Context for security ops */ + void *security_ctx; + + __extension__ + /** Flag indicating the device is attached */ + uint8_t attached : 1; + + /** User application callback for pre enqueue processing */ + struct rte_cryptodev_cb_rcu *enq_cbs; + /** User application callback for post dequeue processing */ + struct rte_cryptodev_cb_rcu *deq_cbs; +} __rte_cache_aligned; + /** Global structure used for maintaining state of allocated crypto devices */ struct rte_cryptodev_global { struct rte_cryptodev *devs; /**< Device information array */ diff --git a/lib/cryptodev/rte_cryptodev_core.h b/lib/cryptodev/rte_cryptodev_core.h index bac5f8d984..47d3985c25 100644 --- a/lib/cryptodev/rte_cryptodev_core.h +++ b/lib/cryptodev/rte_cryptodev_core.h @@ -54,73 +54,6 @@ struct rte_crypto_fp_ops { extern struct rte_crypto_fp_ops rte_crypto_fp_ops[RTE_CRYPTO_MAX_DEVS]; -/** - * @internal - * The data part, with no function pointers, associated with each device. - * - * This structure is safe to place in shared memory to be common among - * different processes in a multi-process configuration. - */ -struct rte_cryptodev_data { - uint8_t dev_id; - /**< Device ID for this instance */ - uint8_t socket_id; - /**< Socket ID where memory is allocated */ - char name[RTE_CRYPTODEV_NAME_MAX_LEN]; - /**< Unique identifier name */ - - __extension__ - uint8_t dev_started : 1; - /**< Device state: STARTED(1)/STOPPED(0) */ - - struct rte_mempool *session_pool; - /**< Session memory pool */ - void **queue_pairs; - /**< Array of pointers to queue pairs. */ - uint16_t nb_queue_pairs; - /**< Number of device queue pairs. */ - - void *dev_private; - /**< PMD-specific private data */ -} __rte_cache_aligned; - - -/** @internal The data structure associated with each crypto device. */ -struct rte_cryptodev { - dequeue_pkt_burst_t dequeue_burst; - /**< Pointer to PMD receive function. */ - enqueue_pkt_burst_t enqueue_burst; - /**< Pointer to PMD transmit function. */ - - struct rte_cryptodev_data *data; - /**< Pointer to device data */ - struct rte_cryptodev_ops *dev_ops; - /**< Functions exported by PMD */ - uint64_t feature_flags; - /**< Feature flags exposes HW/SW features for the given device */ - struct rte_device *device; - /**< Backing device */ - - uint8_t driver_id; - /**< Crypto driver identifier*/ - - struct rte_cryptodev_cb_list link_intr_cbs; - /**< User application callback for interrupts if present */ - - void *security_ctx; - /**< Context for security ops */ - - __extension__ - uint8_t attached : 1; - /**< Flag indicating the device is attached */ - - struct rte_cryptodev_cb_rcu *enq_cbs; - /**< User application callback for pre enqueue processing */ - - struct rte_cryptodev_cb_rcu *deq_cbs; - /**< User application callback for post dequeue processing */ -} __rte_cache_aligned; - /** * The pool of rte_cryptodev structures. */ diff --git a/lib/cryptodev/version.map b/lib/cryptodev/version.map index ed62ced221..cd56ad52e2 100644 --- a/lib/cryptodev/version.map +++ b/lib/cryptodev/version.map @@ -43,7 +43,6 @@ DPDK_22 { rte_cryptodev_sym_session_create; rte_cryptodev_sym_session_free; rte_cryptodev_sym_session_init; - rte_cryptodevs; #added in 21.11 rte_crypto_fp_ops; @@ -124,4 +123,5 @@ INTERNAL { rte_cryptodev_pmd_get_named_dev; rte_cryptodev_pmd_parse_input_args; rte_cryptodev_pmd_release_device; + rte_cryptodevs; };