From patchwork Tue Oct 19 11:27:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gowrishankar Muthukrishnan X-Patchwork-Id: 102214 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DB29BA0C43; Tue, 19 Oct 2021 13:27:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E43574116A; Tue, 19 Oct 2021 13:27:49 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id C33FA4116A for ; Tue, 19 Oct 2021 13:27:47 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19JA0FfX009227 for ; Tue, 19 Oct 2021 04:27:46 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=TT2kqXiaHEwyPRpd1rQgECZn1AAz4V2gm+QozLyXT8w=; b=BtUOXl9NdNCBkJeTwcnauTzs63hXg5kCUx7mRABhhrUedq5r0dfdKL3xcacGXfwJZLM/ UU3KNe7B2gVQmjm8/EOJLw5VrUfwN0ZObf1nLdSrAW/KSANoTkwfYIUk//n4T5zodPG9 qWUovjqH5C7AHLbn9HUJxmxrObwPb9nEQq4uBn3zhFxLt69nOJjiel+HmLZwf7DF0oiv 3JbacaKjz0Uw3Psr0vvm7zSwP2dRskjd9+tAgIj9xGkaTMOWSVQRwRgx/nOLs3UMfXdW t2++LtrftNiru0YLzO+P59H/v+PfK8b8mMs5DN9uVw4adFnP9e5PuexnnMMp/nCZOQ/M Zw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 3bsnmq27ax-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 19 Oct 2021 04:27:46 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 04:27:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 19 Oct 2021 04:27:45 -0700 Received: from localhost.localdomain (unknown [10.28.34.38]) by maili.marvell.com (Postfix) with ESMTP id 5B22B3F7081; Tue, 19 Oct 2021 04:27:42 -0700 (PDT) From: Gowrishankar Muthukrishnan To: CC: , , , , , , , , Gowrishankar Muthukrishnan Date: Tue, 19 Oct 2021 16:57:24 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-GUID: 29CC86OhKN6Bx75pykp0xCsivGGCOOEI X-Proofpoint-ORIG-GUID: 29CC86OhKN6Bx75pykp0xCsivGGCOOEI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-19_01,2021-10-19_01,2020-04-07_01 Subject: [dpdk-dev] [v10 1/4] common/cnxk: add telemetry endpoints to npa X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add telemetry endpoints to npa. Signed-off-by: Gowrishankar Muthukrishnan --- drivers/common/cnxk/cnxk_telemetry.h | 26 +++ drivers/common/cnxk/cnxk_telemetry_npa.c | 260 +++++++++++++++++++++++ drivers/common/cnxk/meson.build | 5 + drivers/common/cnxk/roc_platform.h | 15 ++ 4 files changed, 306 insertions(+) create mode 100644 drivers/common/cnxk/cnxk_telemetry.h create mode 100644 drivers/common/cnxk/cnxk_telemetry_npa.c diff --git a/drivers/common/cnxk/cnxk_telemetry.h b/drivers/common/cnxk/cnxk_telemetry.h new file mode 100644 index 0000000000..1461fd893f --- /dev/null +++ b/drivers/common/cnxk/cnxk_telemetry.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021 Marvell. + */ + +#ifndef __CNXK_TELEMETRY_H_ +#define __CNXK_TELEMETRY_H_ + +#define CNXK_TEL_STR(s) #s +#define CNXK_TEL_STR_PREFIX(s, p) CNXK_TEL_STR(p##s) +#define CNXK_TEL_DICT_INT(d, p, s, ...) \ + plt_tel_data_add_dict_int(d, CNXK_TEL_STR_PREFIX(s, __VA_ARGS__), \ + (p)->s) +#define CNXK_TEL_DICT_PTR(d, p, s, ...) \ + plt_tel_data_add_dict_ptr(d, CNXK_TEL_STR_PREFIX(s, __VA_ARGS__), \ + (void *)(p)->s) +#define CNXK_TEL_DICT_BF_PTR(d, p, s, ...) \ + plt_tel_data_add_dict_ptr(d, CNXK_TEL_STR_PREFIX(s, __VA_ARGS__), \ + (void *)(uint64_t)(p)->s) +#define CNXK_TEL_DICT_U64(d, p, s, ...) \ + plt_tel_data_add_dict_u64(d, CNXK_TEL_STR_PREFIX(s, __VA_ARGS__), \ + (p)->s) +#define CNXK_TEL_DICT_STR(d, p, s, ...) \ + plt_tel_data_add_dict_string(d, CNXK_TEL_STR_PREFIX(s, __VA_ARGS__), \ + (p)->s) + +#endif /* __CNXK_TELEMETRY_H_ */ diff --git a/drivers/common/cnxk/cnxk_telemetry_npa.c b/drivers/common/cnxk/cnxk_telemetry_npa.c new file mode 100644 index 0000000000..ae515df84f --- /dev/null +++ b/drivers/common/cnxk/cnxk_telemetry_npa.c @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cnxk_telemetry.h" +#include "roc_api.h" +#include "roc_priv.h" + +static int +cnxk_tel_npa(struct plt_tel_data *d) +{ + struct npa_lf *lf; + int aura_cnt = 0; + uint32_t i; + + lf = idev_npa_obj_get(); + if (lf == NULL) + return NPA_ERR_DEVICE_NOT_BOUNDED; + + for (i = 0; i < lf->nr_pools; i++) { + if (plt_bitmap_get(lf->npa_bmp, i)) + continue; + aura_cnt++; + } + + plt_tel_data_add_dict_ptr(d, "npa", lf); + plt_tel_data_add_dict_int(d, "pf", dev_get_pf(lf->pf_func)); + plt_tel_data_add_dict_int(d, "vf", dev_get_vf(lf->pf_func)); + plt_tel_data_add_dict_int(d, "aura_cnt", aura_cnt); + + CNXK_TEL_DICT_STR(d, lf->pci_dev, name, pcidev_); + CNXK_TEL_DICT_PTR(d, lf, npa_bmp); + CNXK_TEL_DICT_PTR(d, lf, npa_bmp_mem); + CNXK_TEL_DICT_PTR(d, lf, npa_qint_mem); + CNXK_TEL_DICT_PTR(d, lf, mbox); + CNXK_TEL_DICT_PTR(d, lf, base); + CNXK_TEL_DICT_INT(d, lf, stack_pg_ptrs); + CNXK_TEL_DICT_INT(d, lf, stack_pg_bytes); + CNXK_TEL_DICT_INT(d, lf, npa_msixoff); + CNXK_TEL_DICT_INT(d, lf, nr_pools); + CNXK_TEL_DICT_INT(d, lf, pf_func); + CNXK_TEL_DICT_INT(d, lf, aura_sz); + CNXK_TEL_DICT_INT(d, lf, qints); + + return 0; +} + +static int +cnxk_tel_npa_aura(int aura_id, struct plt_tel_data *d) +{ + __io struct npa_aura_s *aura; + struct npa_aq_enq_req *req; + struct npa_aq_enq_rsp *rsp; + struct npa_lf *lf; + int rc; + + lf = idev_npa_obj_get(); + if (lf == NULL) + return NPA_ERR_DEVICE_NOT_BOUNDED; + + if (plt_bitmap_get(lf->npa_bmp, aura_id)) + return -1; + + req = mbox_alloc_msg_npa_aq_enq(lf->mbox); + if (!req) { + plt_err("Failed to alloc aq enq for npa"); + return -1; + } + + req->aura_id = aura_id; + req->ctype = NPA_AQ_CTYPE_AURA; + req->op = NPA_AQ_INSTOP_READ; + + rc = mbox_process_msg(lf->mbox, (void *)&rsp); + if (rc) { + plt_err("Failed to get pool(%d) context", aura_id); + return rc; + } + + aura = &rsp->aura; + CNXK_TEL_DICT_PTR(d, aura, pool_addr, w0_); + CNXK_TEL_DICT_INT(d, aura, ena, w1_); + CNXK_TEL_DICT_INT(d, aura, pool_caching, w1_); + CNXK_TEL_DICT_INT(d, aura, pool_way_mask, w1_); + CNXK_TEL_DICT_INT(d, aura, avg_con, w1_); + CNXK_TEL_DICT_INT(d, aura, pool_drop_ena, w1_); + CNXK_TEL_DICT_INT(d, aura, aura_drop_ena, w1_); + CNXK_TEL_DICT_INT(d, aura, bp_ena, w1_); + CNXK_TEL_DICT_INT(d, aura, aura_drop, w1_); + CNXK_TEL_DICT_INT(d, aura, avg_level, w1_); + CNXK_TEL_DICT_U64(d, aura, count, w2_); + CNXK_TEL_DICT_INT(d, aura, nix0_bpid, w2_); + CNXK_TEL_DICT_INT(d, aura, nix1_bpid, w2_); + CNXK_TEL_DICT_U64(d, aura, limit, w3_); + CNXK_TEL_DICT_INT(d, aura, bp, w3_); + CNXK_TEL_DICT_INT(d, aura, fc_ena, w3_); + CNXK_TEL_DICT_INT(d, aura, fc_up_crossing, w3_); + CNXK_TEL_DICT_INT(d, aura, fc_stype, w3_); + CNXK_TEL_DICT_INT(d, aura, fc_hyst_bits, w3_); + CNXK_TEL_DICT_INT(d, aura, fc_addr, w4_); + CNXK_TEL_DICT_INT(d, aura, pool_drop, w5_); + CNXK_TEL_DICT_INT(d, aura, update_time, w5_); + CNXK_TEL_DICT_INT(d, aura, err_int, w5_); + CNXK_TEL_DICT_INT(d, aura, err_int_ena, w5_); + CNXK_TEL_DICT_INT(d, aura, thresh_int, w5_); + CNXK_TEL_DICT_INT(d, aura, thresh_int_ena, w5_); + CNXK_TEL_DICT_INT(d, aura, thresh_up, w5_); + CNXK_TEL_DICT_INT(d, aura, thresh_qint_idx, w5_); + CNXK_TEL_DICT_INT(d, aura, err_qint_idx, w5_); + CNXK_TEL_DICT_U64(d, aura, thresh, w6_); + + return 0; +} + +static int +cnxk_tel_npa_pool(int pool_id, struct plt_tel_data *d) +{ + __io struct npa_pool_s *pool; + struct npa_aq_enq_req *req; + struct npa_aq_enq_rsp *rsp; + struct npa_lf *lf; + int rc; + + lf = idev_npa_obj_get(); + if (lf == NULL) + return NPA_ERR_DEVICE_NOT_BOUNDED; + + if (plt_bitmap_get(lf->npa_bmp, pool_id)) + return -1; + + req = mbox_alloc_msg_npa_aq_enq(lf->mbox); + if (!req) { + plt_err("Failed to alloc aq enq for npa"); + return -1; + } + + req->aura_id = pool_id; + req->ctype = NPA_AQ_CTYPE_POOL; + req->op = NPA_AQ_INSTOP_READ; + + rc = mbox_process_msg(lf->mbox, (void *)&rsp); + if (rc) { + plt_err("Failed to get pool(%d) context", pool_id); + return rc; + } + + pool = &rsp->pool; + CNXK_TEL_DICT_PTR(d, pool, stack_base, w0_); + CNXK_TEL_DICT_INT(d, pool, ena, w1_); + CNXK_TEL_DICT_INT(d, pool, nat_align, w1_); + CNXK_TEL_DICT_INT(d, pool, stack_caching, w1_); + CNXK_TEL_DICT_INT(d, pool, stack_way_mask, w1_); + CNXK_TEL_DICT_INT(d, pool, buf_offset, w1_); + CNXK_TEL_DICT_INT(d, pool, buf_size, w1_); + CNXK_TEL_DICT_INT(d, pool, stack_max_pages, w2_); + CNXK_TEL_DICT_INT(d, pool, stack_pages, w2_); + CNXK_TEL_DICT_INT(d, pool, op_pc, w3_); + CNXK_TEL_DICT_INT(d, pool, stack_offset, w4_); + CNXK_TEL_DICT_INT(d, pool, shift, w4_); + CNXK_TEL_DICT_INT(d, pool, avg_level, w4_); + CNXK_TEL_DICT_INT(d, pool, avg_con, w4_); + CNXK_TEL_DICT_INT(d, pool, fc_ena, w4_); + CNXK_TEL_DICT_INT(d, pool, fc_stype, w4_); + CNXK_TEL_DICT_INT(d, pool, fc_hyst_bits, w4_); + CNXK_TEL_DICT_INT(d, pool, fc_up_crossing, w4_); + CNXK_TEL_DICT_INT(d, pool, update_time, w4_); + CNXK_TEL_DICT_PTR(d, pool, fc_addr, w5_); + CNXK_TEL_DICT_PTR(d, pool, ptr_start, w6_); + CNXK_TEL_DICT_PTR(d, pool, ptr_end, w7_); + CNXK_TEL_DICT_INT(d, pool, err_int, w8_); + CNXK_TEL_DICT_INT(d, pool, err_int_ena, w8_); + CNXK_TEL_DICT_INT(d, pool, thresh_int, w8_); + CNXK_TEL_DICT_INT(d, pool, thresh_int_ena, w8_); + CNXK_TEL_DICT_INT(d, pool, thresh_up, w8_); + CNXK_TEL_DICT_INT(d, pool, thresh_qint_idx, w8_); + CNXK_TEL_DICT_INT(d, pool, err_qint_idx, w8_); + + return 0; +} + +static int +cnxk_npa_tel_handle_info(const char *cmd __plt_unused, + const char *params __plt_unused, + struct plt_tel_data *d) +{ + plt_tel_data_start_dict(d); + return cnxk_tel_npa(d); +} + +static int +cnxk_npa_tel_handle_aura_list(const char *cmd __plt_unused, + const char *params __plt_unused, + struct plt_tel_data *d) +{ + struct npa_lf *lf; + int i; + + lf = idev_npa_obj_get(); + if (lf == NULL) + return NPA_ERR_DEVICE_NOT_BOUNDED; + + plt_tel_data_start_array(d, PLT_TEL_INT_VAL); + + for (i = 0; i < (int)lf->nr_pools; i++) + if (!plt_bitmap_get(lf->npa_bmp, i)) + rte_tel_data_add_array_int(d, i); + + return 0; +} + +static int +cnxk_npa_tel_handle_pool_list(const char *cmd, const char *params, + struct plt_tel_data *d) +{ + /* In current implementation, aura and pool ID mapped 1:1 */ + return cnxk_npa_tel_handle_aura_list(cmd, params, d); +} + +static int +cnxk_npa_tel_handle_info_x(const char *cmd, const char *params, + struct plt_tel_data *d) +{ + int id, rc; + + if (params == NULL || strlen(params) == 0 || !isdigit(*params)) + return -1; + + id = strtol(params, NULL, 10); + plt_tel_data_start_dict(d); + + if (strstr(cmd, "aura/info")) + rc = cnxk_tel_npa_aura(id, d); + else + rc = cnxk_tel_npa_pool(id, d); + + return rc; +} + +PLT_INIT(cnxk_telemetry_npa_init) +{ + plt_telemetry_register_cmd( + "/cnxk/npa/info", cnxk_npa_tel_handle_info, + "Returns npa information. Takes no parameters"); + + plt_telemetry_register_cmd( + "/cnxk/npa/aura/list", cnxk_npa_tel_handle_aura_list, + "Returns list of npa aura id. Takes no parameters"); + + plt_telemetry_register_cmd( + "/cnxk/npa/aura/info", cnxk_npa_tel_handle_info_x, + "Returns npa aura information. Parameters: aura_id"); + + plt_telemetry_register_cmd( + "/cnxk/npa/pool/list", cnxk_npa_tel_handle_pool_list, + "Returns list of npa pool id. Takes no parameters"); + + plt_telemetry_register_cmd( + "/cnxk/npa/pool/info", cnxk_npa_tel_handle_info_x, + "Returns npa pool information. Parameters: pool_id"); +} diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 97db5f087b..d88cfbc7fa 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -71,3 +71,8 @@ includes += include_directories('../../bus/pci') includes += include_directories('../../../lib/net') includes += include_directories('../../../lib/ethdev') includes += include_directories('../../../lib/meter') + +# Telemetry common code +sources += files('cnxk_telemetry_npa.c') + +deps += ['bus_pci', 'net', 'telemetry'] diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 241655b334..59af6f4975 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -19,6 +19,7 @@ #include #include #include +#include #include "roc_bits.h" @@ -51,6 +52,7 @@ #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE #define BITMASK_ULL GENMASK_ULL #define PLT_ALIGN_CEIL RTE_ALIGN_CEIL +#define PLT_INIT RTE_INIT /** Divide ceil */ #define PLT_DIV_CEIL(x, y) \ @@ -63,6 +65,7 @@ #define __plt_cache_aligned __rte_cache_aligned #define __plt_always_inline __rte_always_inline #define __plt_packed __rte_packed +#define __plt_unused __rte_unused #define __roc_api __rte_internal #define plt_iova_t rte_iova_t @@ -142,6 +145,18 @@ #define plt_strlcpy rte_strlcpy +#define PLT_TEL_INT_VAL RTE_TEL_INT_VAL +#define plt_tel_data rte_tel_data +#define plt_tel_data_start_array rte_tel_data_start_array +#define plt_tel_data_add_array_int rte_tel_data_add_array_int +#define plt_tel_data_start_dict rte_tel_data_start_dict +#define plt_tel_data_add_dict_int rte_tel_data_add_dict_int +#define plt_tel_data_add_dict_ptr(d, n, v) \ + rte_tel_data_add_dict_u64(d, n, (uint64_t)v) +#define plt_tel_data_add_dict_string rte_tel_data_add_dict_string +#define plt_tel_data_add_dict_u64 rte_tel_data_add_dict_u64 +#define plt_telemetry_register_cmd rte_telemetry_register_cmd + /* Log */ extern int cnxk_logtype_base; extern int cnxk_logtype_mbox; From patchwork Tue Oct 19 11:27:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gowrishankar Muthukrishnan X-Patchwork-Id: 102215 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9C186A0C43; Tue, 19 Oct 2021 13:28:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9057F41174; Tue, 19 Oct 2021 13:27:54 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 846744117D for ; Tue, 19 Oct 2021 13:27:51 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19JA0FfY009227 for ; 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Tue, 19 Oct 2021 04:27:49 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 19 Oct 2021 04:27:49 -0700 Received: from localhost.localdomain (unknown [10.28.34.38]) by maili.marvell.com (Postfix) with ESMTP id E959E3F7085; Tue, 19 Oct 2021 04:27:45 -0700 (PDT) From: Gowrishankar Muthukrishnan To: CC: , , , , , , , , Gowrishankar Muthukrishnan Date: Tue, 19 Oct 2021 16:57:25 +0530 Message-ID: <8987f04c6f21e0b489e195b5a8fe9070795b83cb.1634642657.git.gmuthukrishn@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-GUID: 1nNGZ_lchzUe54mtcJbvYouI5jJNFdGq X-Proofpoint-ORIG-GUID: 1nNGZ_lchzUe54mtcJbvYouI5jJNFdGq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-19_01,2021-10-19_01,2020-04-07_01 Subject: [dpdk-dev] [v10 2/4] common/cnxk: add telemetry endpoints to nix X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add telemetry endpoints to nix. Signed-off-by: Gowrishankar Muthukrishnan Reviewed-by: Harman Kalra --- drivers/common/cnxk/cnxk_telemetry_nix.c | 849 +++++++++++++++++++++++ drivers/common/cnxk/meson.build | 3 +- drivers/common/cnxk/roc_nix.c | 3 + drivers/common/cnxk/roc_nix_priv.h | 9 + drivers/common/cnxk/roc_nix_queue.c | 15 +- drivers/common/cnxk/roc_platform.h | 2 + 6 files changed, 877 insertions(+), 4 deletions(-) create mode 100644 drivers/common/cnxk/cnxk_telemetry_nix.c diff --git a/drivers/common/cnxk/cnxk_telemetry_nix.c b/drivers/common/cnxk/cnxk_telemetry_nix.c new file mode 100644 index 0000000000..1175f68a51 --- /dev/null +++ b/drivers/common/cnxk/cnxk_telemetry_nix.c @@ -0,0 +1,849 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cnxk_telemetry.h" +#include "roc_api.h" +#include "roc_priv.h" + +struct nix_tel_node { + TAILQ_ENTRY(nix_tel_node) node; + struct roc_nix *nix; + uint16_t n_rq; + uint16_t n_cq; + uint16_t n_sq; + struct roc_nix_rq **rqs; + struct roc_nix_cq **cqs; + struct roc_nix_sq **sqs; +}; + +TAILQ_HEAD(nix_tel_node_list, nix_tel_node); +static struct nix_tel_node_list nix_list; + +static struct nix_tel_node * +nix_tel_node_get(struct roc_nix *roc_nix) +{ + struct nix_tel_node *node, *roc_node = NULL; + + TAILQ_FOREACH(node, &nix_list, node) { + if (node->nix == roc_nix) { + roc_node = node; + break; + } + } + + return roc_node; +} + +int +nix_tel_node_add(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct nix_tel_node *node; + + node = nix_tel_node_get(roc_nix); + if (node) { + if (nix->nb_rx_queues == node->n_rq && + nix->nb_tx_queues == node->n_sq) + return 0; + + nix_tel_node_del(roc_nix); + } + + node = plt_zmalloc(sizeof(struct nix_tel_node), 0); + if (!node) + return -1; + + node->nix = roc_nix; + node->rqs = + plt_zmalloc(nix->nb_rx_queues * sizeof(struct roc_nix_rq *), 0); + node->cqs = + plt_zmalloc(nix->nb_rx_queues * sizeof(struct roc_nix_cq *), 0); + node->sqs = + plt_zmalloc(nix->nb_tx_queues * sizeof(struct roc_nix_sq *), 0); + TAILQ_INSERT_TAIL(&nix_list, node, node); + + return 0; +} + +void +nix_tel_node_del(struct roc_nix *roc_nix) +{ + struct nix_tel_node *node; + + TAILQ_FOREACH(node, &nix_list, node) { + if (node->nix == roc_nix) { + plt_free(node->rqs); + plt_free(node->cqs); + plt_free(node->sqs); + TAILQ_REMOVE(&nix_list, node, node); + } + } + + plt_free(node); +} + +static struct nix_tel_node * +nix_tel_node_get_by_pcidev_name(const char *name) +{ + struct nix_tel_node *node, *roc_node = NULL; + + TAILQ_FOREACH(node, &nix_list, node) { + if (!strncmp(node->nix->pci_dev->name, name, + PCI_PRI_STR_SIZE)) { + roc_node = node; + break; + } + } + + return roc_node; +} + +int +nix_tel_node_add_rq(struct roc_nix_rq *rq) +{ + struct nix_tel_node *node; + + node = nix_tel_node_get(rq->roc_nix); + if (!node) + return -1; + + node->rqs[rq->qid] = rq; + node->n_rq++; + return 0; +} + +int +nix_tel_node_add_cq(struct roc_nix_cq *cq) +{ + struct nix_tel_node *node; + + node = nix_tel_node_get(cq->roc_nix); + if (!node) + return -1; + + node->cqs[cq->qid] = cq; + node->n_cq++; + return 0; +} + +int +nix_tel_node_add_sq(struct roc_nix_sq *sq) +{ + struct nix_tel_node *node; + + node = nix_tel_node_get(sq->roc_nix); + if (!node) + return -1; + + node->sqs[sq->qid] = sq; + node->n_sq++; + return 0; +} + +static int +cnxk_tel_nix(struct roc_nix *roc_nix, struct plt_tel_data *d) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + + struct dev *dev = &nix->dev; + + plt_tel_data_add_dict_ptr(d, "nix", nix); + plt_tel_data_add_dict_int(d, "pf_func", dev->pf_func); + plt_tel_data_add_dict_int(d, "pf", dev_get_pf(dev->pf_func)); + plt_tel_data_add_dict_int(d, "vf", dev_get_vf(dev->pf_func)); + + CNXK_TEL_DICT_PTR(d, dev, bar2); + CNXK_TEL_DICT_PTR(d, dev, bar4); + CNXK_TEL_DICT_INT(d, roc_nix, port_id); + CNXK_TEL_DICT_INT(d, roc_nix, rss_tag_as_xor); + CNXK_TEL_DICT_INT(d, roc_nix, max_sqb_count); + CNXK_TEL_DICT_PTR(d, nix, pci_dev); + CNXK_TEL_DICT_PTR(d, nix, base); + CNXK_TEL_DICT_PTR(d, nix, lmt_base); + CNXK_TEL_DICT_INT(d, nix, reta_sz); + CNXK_TEL_DICT_INT(d, nix, tx_chan_base); + CNXK_TEL_DICT_INT(d, nix, rx_chan_base); + CNXK_TEL_DICT_INT(d, nix, nb_tx_queues); + CNXK_TEL_DICT_INT(d, nix, nb_rx_queues); + CNXK_TEL_DICT_INT(d, nix, lso_tsov6_idx); + CNXK_TEL_DICT_INT(d, nix, lso_tsov4_idx); + + plt_tel_data_add_dict_int(d, "lso_udp_tun_v4v4", + nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V4]); + plt_tel_data_add_dict_int(d, "lso_udp_tun_v4v6", + nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V6]); + plt_tel_data_add_dict_int(d, "lso_udp_tun_v6v4", + nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V4]); + plt_tel_data_add_dict_int(d, "lso_udp_tun_v6v6", + nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V6]); + plt_tel_data_add_dict_int(d, "lso_tun_v4v4", + nix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V4]); + plt_tel_data_add_dict_int(d, "lso_tun_v4v6", + nix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V6]); + plt_tel_data_add_dict_int(d, "lso_tun_v6v4", + nix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V4]); + plt_tel_data_add_dict_int(d, "lso_tun_v6v6", + nix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V6]); + + CNXK_TEL_DICT_INT(d, nix, lf_tx_stats); + CNXK_TEL_DICT_INT(d, nix, lf_rx_stats); + CNXK_TEL_DICT_INT(d, nix, cgx_links); + CNXK_TEL_DICT_INT(d, nix, lbk_links); + CNXK_TEL_DICT_INT(d, nix, sdp_links); + CNXK_TEL_DICT_INT(d, nix, tx_link); + CNXK_TEL_DICT_INT(d, nix, sqb_size); + CNXK_TEL_DICT_INT(d, nix, msixoff); + CNXK_TEL_DICT_INT(d, nix, cints); + CNXK_TEL_DICT_INT(d, nix, qints); + CNXK_TEL_DICT_INT(d, nix, sdp_link); + CNXK_TEL_DICT_INT(d, nix, ptp_en); + CNXK_TEL_DICT_INT(d, nix, rss_alg_idx); + CNXK_TEL_DICT_INT(d, nix, tx_pause); + + return 0; +} + +static int +cnxk_tel_nix_rq(struct roc_nix_rq *rq, struct plt_tel_data *d) +{ + plt_tel_data_add_dict_ptr(d, "nix_rq", rq); + CNXK_TEL_DICT_INT(d, rq, qid); + CNXK_TEL_DICT_PTR(d, rq, aura_handle); + CNXK_TEL_DICT_INT(d, rq, ipsech_ena); + CNXK_TEL_DICT_INT(d, rq, first_skip); + CNXK_TEL_DICT_INT(d, rq, later_skip); + CNXK_TEL_DICT_INT(d, rq, lpb_size); + CNXK_TEL_DICT_INT(d, rq, sso_ena); + CNXK_TEL_DICT_INT(d, rq, tag_mask); + CNXK_TEL_DICT_INT(d, rq, flow_tag_width); + CNXK_TEL_DICT_INT(d, rq, tt); + CNXK_TEL_DICT_INT(d, rq, hwgrp); + CNXK_TEL_DICT_INT(d, rq, vwqe_ena); + CNXK_TEL_DICT_INT(d, rq, vwqe_first_skip); + CNXK_TEL_DICT_INT(d, rq, vwqe_max_sz_exp); + CNXK_TEL_DICT_INT(d, rq, vwqe_wait_tmo); + CNXK_TEL_DICT_INT(d, rq, vwqe_aura_handle); + CNXK_TEL_DICT_PTR(d, rq, roc_nix); + + return 0; +} + +static int +cnxk_tel_nix_cq(struct roc_nix_cq *cq, struct plt_tel_data *d) +{ + plt_tel_data_add_dict_ptr(d, "nix_cq", cq); + CNXK_TEL_DICT_INT(d, cq, qid); + CNXK_TEL_DICT_INT(d, cq, nb_desc); + CNXK_TEL_DICT_PTR(d, cq, roc_nix); + CNXK_TEL_DICT_PTR(d, cq, door); + CNXK_TEL_DICT_PTR(d, cq, status); + CNXK_TEL_DICT_PTR(d, cq, wdata); + CNXK_TEL_DICT_PTR(d, cq, desc_base); + CNXK_TEL_DICT_INT(d, cq, qmask); + + return 0; +} + +static int +cnxk_tel_nix_sq(struct roc_nix_sq *sq, struct plt_tel_data *d) +{ + plt_tel_data_add_dict_ptr(d, "nix_sq", sq); + CNXK_TEL_DICT_INT(d, sq, qid); + CNXK_TEL_DICT_INT(d, sq, max_sqe_sz); + CNXK_TEL_DICT_INT(d, sq, nb_desc); + CNXK_TEL_DICT_INT(d, sq, sqes_per_sqb_log2); + CNXK_TEL_DICT_PTR(d, sq, roc_nix); + CNXK_TEL_DICT_PTR(d, sq, aura_handle); + CNXK_TEL_DICT_INT(d, sq, nb_sqb_bufs_adj); + CNXK_TEL_DICT_INT(d, sq, nb_sqb_bufs); + CNXK_TEL_DICT_PTR(d, sq, io_addr); + CNXK_TEL_DICT_PTR(d, sq, lmt_addr); + CNXK_TEL_DICT_PTR(d, sq, sqe_mem); + CNXK_TEL_DICT_PTR(d, sq, fc); + + return 0; +} + +static void +nix_rq_ctx_cn9k(void *qctx, struct plt_tel_data *d) +{ + struct nix_rq_ctx_s *ctx = (struct nix_rq_ctx_s *)qctx; + + /* W0 */ + CNXK_TEL_DICT_INT(d, ctx, wqe_aura, w0_); + CNXK_TEL_DICT_BF_PTR(d, ctx, substream, w0_); + CNXK_TEL_DICT_INT(d, ctx, cq, w0_); + CNXK_TEL_DICT_INT(d, ctx, ena_wqwd, w0_); + CNXK_TEL_DICT_INT(d, ctx, ipsech_ena, w0_); + CNXK_TEL_DICT_INT(d, ctx, sso_ena, w0_); + CNXK_TEL_DICT_INT(d, ctx, ena, w0_); + + /* W1 */ + CNXK_TEL_DICT_INT(d, ctx, lpb_drop_ena, w1_); + CNXK_TEL_DICT_INT(d, ctx, spb_drop_ena, w1_); + CNXK_TEL_DICT_INT(d, ctx, xqe_drop_ena, w1_); + CNXK_TEL_DICT_INT(d, ctx, wqe_caching, w1_); + CNXK_TEL_DICT_INT(d, ctx, pb_caching, w1_); + CNXK_TEL_DICT_INT(d, ctx, sso_tt, w1_); + CNXK_TEL_DICT_INT(d, ctx, sso_grp, w1_); + CNXK_TEL_DICT_INT(d, ctx, lpb_aura, w1_); + CNXK_TEL_DICT_INT(d, ctx, spb_aura, w1_); + + /* W2 */ + CNXK_TEL_DICT_INT(d, ctx, xqe_hdr_split, w2_); + CNXK_TEL_DICT_INT(d, ctx, xqe_imm_copy, w2_); + CNXK_TEL_DICT_INT(d, ctx, xqe_imm_size, w2_); + CNXK_TEL_DICT_INT(d, ctx, later_skip, w2_); + CNXK_TEL_DICT_INT(d, ctx, first_skip, w2_); + CNXK_TEL_DICT_INT(d, ctx, lpb_sizem1, w2_); + CNXK_TEL_DICT_INT(d, ctx, spb_ena, w2_); + CNXK_TEL_DICT_INT(d, ctx, wqe_skip, w2_); + CNXK_TEL_DICT_INT(d, ctx, spb_sizem1, w2_); + + /* W3 */ + CNXK_TEL_DICT_INT(d, ctx, spb_pool_pass, w3_); + CNXK_TEL_DICT_INT(d, ctx, spb_pool_drop, w3_); + CNXK_TEL_DICT_INT(d, ctx, spb_aura_pass, w3_); + CNXK_TEL_DICT_INT(d, ctx, spb_aura_drop, w3_); + CNXK_TEL_DICT_INT(d, ctx, wqe_pool_pass, w3_); + CNXK_TEL_DICT_INT(d, ctx, wqe_pool_drop, w3_); + CNXK_TEL_DICT_INT(d, ctx, xqe_pass, w3_); + CNXK_TEL_DICT_INT(d, ctx, xqe_drop, w3_); + + /* W4 */ + CNXK_TEL_DICT_INT(d, ctx, qint_idx, w4_); + CNXK_TEL_DICT_INT(d, ctx, rq_int_ena, w4_); + CNXK_TEL_DICT_INT(d, ctx, rq_int, w4_); + CNXK_TEL_DICT_INT(d, ctx, lpb_pool_pass, w4_); + CNXK_TEL_DICT_INT(d, ctx, lpb_pool_drop, w4_); + CNXK_TEL_DICT_INT(d, ctx, lpb_aura_pass, w4_); + CNXK_TEL_DICT_INT(d, ctx, lpb_aura_drop, w4_); + + /* W5 */ + CNXK_TEL_DICT_INT(d, ctx, flow_tagw, w5_); + CNXK_TEL_DICT_INT(d, ctx, bad_utag, w5_); + CNXK_TEL_DICT_INT(d, ctx, good_utag, w5_); + CNXK_TEL_DICT_INT(d, ctx, ltag, w5_); + + /* W6 */ + CNXK_TEL_DICT_U64(d, ctx, octs, w6_); + + /* W7 */ + CNXK_TEL_DICT_U64(d, ctx, pkts, w7_); + + /* W8 */ + CNXK_TEL_DICT_U64(d, ctx, drop_octs, w8_); + + /* W9 */ + CNXK_TEL_DICT_U64(d, ctx, drop_pkts, w9_); + + /* W10 */ + CNXK_TEL_DICT_U64(d, ctx, re_pkts, w10_); +} + +static void +nix_rq_ctx(void *qctx, struct plt_tel_data *d) +{ + struct nix_cn10k_rq_ctx_s *ctx = (struct nix_cn10k_rq_ctx_s *)qctx; + + /* W0 */ + CNXK_TEL_DICT_INT(d, ctx, wqe_aura, w0_); + CNXK_TEL_DICT_INT(d, ctx, len_ol3_dis, w0_); + CNXK_TEL_DICT_INT(d, ctx, len_ol4_dis, w0_); + CNXK_TEL_DICT_INT(d, ctx, len_il3_dis, w0_); + CNXK_TEL_DICT_INT(d, ctx, len_il4_dis, w0_); + CNXK_TEL_DICT_INT(d, ctx, csum_ol4_dis, w0_); + CNXK_TEL_DICT_INT(d, ctx, lenerr_dis, w0_); + CNXK_TEL_DICT_INT(d, ctx, ena_wqwd, w0); + CNXK_TEL_DICT_INT(d, ctx, ipsech_ena, w0); + CNXK_TEL_DICT_INT(d, ctx, sso_ena, w0); + CNXK_TEL_DICT_INT(d, ctx, ena, w0); + + /* W1 */ + CNXK_TEL_DICT_INT(d, ctx, chi_ena, w1_); + CNXK_TEL_DICT_INT(d, ctx, ipsecd_drop_en, w1_); + CNXK_TEL_DICT_INT(d, ctx, pb_stashing, w1_); + CNXK_TEL_DICT_INT(d, ctx, lpb_drop_ena, w1_); + CNXK_TEL_DICT_INT(d, ctx, spb_drop_ena, w1_); + CNXK_TEL_DICT_INT(d, ctx, xqe_drop_ena, w1_); + CNXK_TEL_DICT_INT(d, ctx, wqe_caching, w1_); + CNXK_TEL_DICT_INT(d, ctx, pb_caching, w1_); + CNXK_TEL_DICT_INT(d, ctx, sso_tt, w1_); + CNXK_TEL_DICT_INT(d, ctx, sso_grp, w1_); + CNXK_TEL_DICT_INT(d, ctx, lpb_aura, w1_); + CNXK_TEL_DICT_INT(d, ctx, spb_aura, w1_); + + /* W2 */ + CNXK_TEL_DICT_INT(d, ctx, xqe_hdr_split, w2_); + CNXK_TEL_DICT_INT(d, ctx, xqe_imm_copy, w2_); + CNXK_TEL_DICT_INT(d, ctx, xqe_imm_size, w2_); + CNXK_TEL_DICT_INT(d, ctx, later_skip, w2_); + CNXK_TEL_DICT_INT(d, ctx, first_skip, w2_); + CNXK_TEL_DICT_INT(d, ctx, lpb_sizem1, w2_); + CNXK_TEL_DICT_INT(d, ctx, spb_ena, w2_); + CNXK_TEL_DICT_INT(d, ctx, wqe_skip, w2_); + CNXK_TEL_DICT_INT(d, ctx, spb_sizem1, w2_); + CNXK_TEL_DICT_INT(d, ctx, policer_ena, w2_); + CNXK_TEL_DICT_INT(d, ctx, band_prof_id, w2_); + + /* W3 */ + CNXK_TEL_DICT_INT(d, ctx, spb_pool_pass, w3_); + CNXK_TEL_DICT_INT(d, ctx, spb_pool_drop, w3_); + CNXK_TEL_DICT_INT(d, ctx, spb_aura_pass, w3_); + CNXK_TEL_DICT_INT(d, ctx, spb_aura_drop, w3_); + CNXK_TEL_DICT_INT(d, ctx, wqe_pool_pass, w3_); + CNXK_TEL_DICT_INT(d, ctx, wqe_pool_drop, w3_); + CNXK_TEL_DICT_INT(d, ctx, xqe_pass, w3_); + CNXK_TEL_DICT_INT(d, ctx, xqe_drop, w3_); + + /* W4 */ + CNXK_TEL_DICT_INT(d, ctx, qint_idx, w4_); + CNXK_TEL_DICT_INT(d, ctx, rq_int_ena, w4_); + CNXK_TEL_DICT_INT(d, ctx, rq_int, w4_); + CNXK_TEL_DICT_INT(d, ctx, lpb_pool_pass, w4_); + CNXK_TEL_DICT_INT(d, ctx, lpb_pool_drop, w4_); + CNXK_TEL_DICT_INT(d, ctx, lpb_aura_pass, w4_); + CNXK_TEL_DICT_INT(d, ctx, lpb_aura_drop, w4_); + + /* W5 */ + CNXK_TEL_DICT_INT(d, ctx, vwqe_skip, w5_); + CNXK_TEL_DICT_INT(d, ctx, max_vsize_exp, w5_); + CNXK_TEL_DICT_INT(d, ctx, vtime_wait, w5_); + CNXK_TEL_DICT_INT(d, ctx, vwqe_ena, w5_); + CNXK_TEL_DICT_INT(d, ctx, ipsec_vwqe, w5_); + CNXK_TEL_DICT_INT(d, ctx, flow_tagw, w5_); + CNXK_TEL_DICT_INT(d, ctx, bad_utag, w5_); + CNXK_TEL_DICT_INT(d, ctx, good_utag, w5_); + CNXK_TEL_DICT_INT(d, ctx, ltag, w5_); + + /* W6 */ + CNXK_TEL_DICT_U64(d, ctx, octs, w6_); + + /* W7 */ + CNXK_TEL_DICT_U64(d, ctx, pkts, w7_); + + /* W8 */ + CNXK_TEL_DICT_U64(d, ctx, drop_octs, w8_); + + /* W9 */ + CNXK_TEL_DICT_U64(d, ctx, drop_pkts, w9_); + + /* W10 */ + CNXK_TEL_DICT_U64(d, ctx, re_pkts, w10_); +} + +static int +cnxk_tel_nix_rq_ctx(struct roc_nix *roc_nix, uint8_t n, struct plt_tel_data *d) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct dev *dev = &nix->dev; + struct npa_lf *npa_lf; + volatile void *qctx; + int rc = -1; + + npa_lf = idev_npa_obj_get(); + if (npa_lf == NULL) + return NPA_ERR_DEVICE_NOT_BOUNDED; + + rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, n, &qctx); + if (rc) { + plt_err("Failed to get rq context"); + return rc; + } + + if (roc_model_is_cn9k()) + nix_rq_ctx_cn9k(&qctx, d); + else + nix_rq_ctx(&qctx, d); + + return 0; +} + +static int +cnxk_tel_nix_cq_ctx(struct roc_nix *roc_nix, uint8_t n, struct plt_tel_data *d) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct dev *dev = &nix->dev; + struct npa_lf *npa_lf; + volatile struct nix_cq_ctx_s *ctx; + int rc = -1; + + npa_lf = idev_npa_obj_get(); + if (npa_lf == NULL) + return NPA_ERR_DEVICE_NOT_BOUNDED; + + rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_CQ, n, (void *)&ctx); + if (rc) { + plt_err("Failed to get cq context"); + return rc; + } + + /* W0 */ + CNXK_TEL_DICT_PTR(d, ctx, base, w0_); + + /* W1 */ + CNXK_TEL_DICT_U64(d, ctx, wrptr, w1_); + CNXK_TEL_DICT_INT(d, ctx, avg_con, w1_); + CNXK_TEL_DICT_INT(d, ctx, cint_idx, w1_); + CNXK_TEL_DICT_INT(d, ctx, cq_err, w1_); + CNXK_TEL_DICT_INT(d, ctx, qint_idx, w1_); + CNXK_TEL_DICT_INT(d, ctx, bpid, w1_); + CNXK_TEL_DICT_INT(d, ctx, bp_ena, w1_); + + /* W2 */ + CNXK_TEL_DICT_INT(d, ctx, update_time, w2_); + CNXK_TEL_DICT_INT(d, ctx, avg_level, w2_); + CNXK_TEL_DICT_INT(d, ctx, head, w2_); + CNXK_TEL_DICT_INT(d, ctx, tail, w2_); + + /* W3 */ + CNXK_TEL_DICT_INT(d, ctx, cq_err_int_ena, w3_); + CNXK_TEL_DICT_INT(d, ctx, cq_err_int, w3_); + CNXK_TEL_DICT_INT(d, ctx, qsize, w3_); + CNXK_TEL_DICT_INT(d, ctx, caching, w3_); + CNXK_TEL_DICT_INT(d, ctx, substream, w3_); + CNXK_TEL_DICT_INT(d, ctx, ena, w3_); + CNXK_TEL_DICT_INT(d, ctx, drop_ena, w3_); + CNXK_TEL_DICT_INT(d, ctx, drop, w3_); + CNXK_TEL_DICT_INT(d, ctx, bp, w3_); + + return 0; +} + +static void +nix_sq_ctx_cn9k(void *qctx, struct plt_tel_data *d) +{ + struct nix_sq_ctx_s *ctx = (struct nix_sq_ctx_s *)qctx; + + /* W0 */ + CNXK_TEL_DICT_INT(d, ctx, sqe_way_mask, w0_); + CNXK_TEL_DICT_INT(d, ctx, cq, w0_); + CNXK_TEL_DICT_INT(d, ctx, sdp_mcast, w0_); + CNXK_TEL_DICT_INT(d, ctx, substream, w0_); + CNXK_TEL_DICT_INT(d, ctx, qint_idx, w0_); + CNXK_TEL_DICT_INT(d, ctx, ena, w0_); + + /* W1 */ + CNXK_TEL_DICT_INT(d, ctx, sqb_count, w1_); + CNXK_TEL_DICT_INT(d, ctx, default_chan, w1_); + CNXK_TEL_DICT_INT(d, ctx, smq_rr_quantum, w1_); + CNXK_TEL_DICT_INT(d, ctx, sso_ena, w1_); + CNXK_TEL_DICT_INT(d, ctx, xoff, w1_); + CNXK_TEL_DICT_INT(d, ctx, cq_ena, w1_); + CNXK_TEL_DICT_INT(d, ctx, smq, w1_); + + /* W2 */ + CNXK_TEL_DICT_INT(d, ctx, sqe_stype, w2_); + CNXK_TEL_DICT_INT(d, ctx, sq_int_ena, w2_); + CNXK_TEL_DICT_INT(d, ctx, sq_int, w2_); + CNXK_TEL_DICT_INT(d, ctx, sqb_aura, w2_); + CNXK_TEL_DICT_INT(d, ctx, smq_rr_count, w2_); + + /* W3 */ + CNXK_TEL_DICT_INT(d, ctx, smq_next_sq_vld, w3_); + CNXK_TEL_DICT_INT(d, ctx, smq_pend, w3_); + CNXK_TEL_DICT_INT(d, ctx, smenq_next_sqb_vld, w3_); + CNXK_TEL_DICT_INT(d, ctx, head_offset, w3_); + CNXK_TEL_DICT_INT(d, ctx, smenq_offset, w3_); + CNXK_TEL_DICT_INT(d, ctx, tail_offset, w3_); + CNXK_TEL_DICT_INT(d, ctx, smq_lso_segnum, w3_); + CNXK_TEL_DICT_INT(d, ctx, smq_next_sq, w3_); + CNXK_TEL_DICT_INT(d, ctx, mnq_dis, w3_); + CNXK_TEL_DICT_INT(d, ctx, lmt_dis, w3_); + CNXK_TEL_DICT_INT(d, ctx, cq_limit, w3_); + CNXK_TEL_DICT_INT(d, ctx, max_sqe_size, w3_); + + /* W4 */ + CNXK_TEL_DICT_PTR(d, ctx, next_sqb, w4_); + + /* W5 */ + CNXK_TEL_DICT_PTR(d, ctx, tail_sqb, w5_); + + /* W6 */ + CNXK_TEL_DICT_PTR(d, ctx, smenq_sqb, w6_); + + /* W7 */ + CNXK_TEL_DICT_PTR(d, ctx, smenq_next_sqb, w7_); + + /* W8 */ + CNXK_TEL_DICT_PTR(d, ctx, head_sqb, w8_); + + /* W9 */ + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_vld, w9_); + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_vlan1_ins_ena, w9_); + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_vlan0_ins_ena, w9_); + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_mps, w9_); + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_sb, w9_); + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_sizem1, w9_); + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_total, w9_); + + /* W10 */ + CNXK_TEL_DICT_BF_PTR(d, ctx, scm_lso_rem, w10_); + + /* W11 */ + CNXK_TEL_DICT_BF_PTR(d, ctx, octs, w11_); + + /* W12 */ + CNXK_TEL_DICT_BF_PTR(d, ctx, pkts, w12_); + + /* W14 */ + CNXK_TEL_DICT_BF_PTR(d, ctx, drop_octs, w14_); + + /* W15 */ + CNXK_TEL_DICT_BF_PTR(d, ctx, drop_pkts, w15_); +} + +static void +nix_sq_ctx(void *qctx, struct plt_tel_data *d) +{ + struct nix_cn10k_sq_ctx_s *ctx = (struct nix_cn10k_sq_ctx_s *)qctx; + + /* W0 */ + CNXK_TEL_DICT_INT(d, ctx, sqe_way_mask, w0_); + CNXK_TEL_DICT_INT(d, ctx, cq, w0_); + CNXK_TEL_DICT_INT(d, ctx, sdp_mcast, w0_); + CNXK_TEL_DICT_INT(d, ctx, substream, w0_); + CNXK_TEL_DICT_INT(d, ctx, qint_idx, w0_); + CNXK_TEL_DICT_INT(d, ctx, ena, w0_); + + /* W1 */ + CNXK_TEL_DICT_INT(d, ctx, sqb_count, w1_); + CNXK_TEL_DICT_INT(d, ctx, default_chan, w1_); + CNXK_TEL_DICT_INT(d, ctx, smq_rr_weight, w1_); + CNXK_TEL_DICT_INT(d, ctx, sso_ena, w1_); + CNXK_TEL_DICT_INT(d, ctx, xoff, w1_); + CNXK_TEL_DICT_INT(d, ctx, cq_ena, w1_); + CNXK_TEL_DICT_INT(d, ctx, smq, w1_); + + /* W2 */ + CNXK_TEL_DICT_INT(d, ctx, sqe_stype, w2_); + CNXK_TEL_DICT_INT(d, ctx, sq_int_ena, w2_); + CNXK_TEL_DICT_INT(d, ctx, sq_int, w2_); + CNXK_TEL_DICT_INT(d, ctx, sqb_aura, w2_); + CNXK_TEL_DICT_INT(d, ctx, smq_rr_count_ub, w2_); + CNXK_TEL_DICT_INT(d, ctx, smq_rr_count_lb, w2_); + + /* W3 */ + CNXK_TEL_DICT_INT(d, ctx, smq_next_sq_vld, w3_); + CNXK_TEL_DICT_INT(d, ctx, smq_pend, w3_); + CNXK_TEL_DICT_INT(d, ctx, smenq_next_sqb_vld, w3_); + CNXK_TEL_DICT_INT(d, ctx, head_offset, w3_); + CNXK_TEL_DICT_INT(d, ctx, smenq_offset, w3_); + CNXK_TEL_DICT_INT(d, ctx, tail_offset, w3_); + CNXK_TEL_DICT_INT(d, ctx, smq_lso_segnum, w3_); + CNXK_TEL_DICT_INT(d, ctx, smq_next_sq, w3_); + CNXK_TEL_DICT_INT(d, ctx, mnq_dis, w3_); + CNXK_TEL_DICT_INT(d, ctx, lmt_dis, w3_); + CNXK_TEL_DICT_INT(d, ctx, cq_limit, w3_); + CNXK_TEL_DICT_INT(d, ctx, max_sqe_size, w3_); + + /* W4 */ + CNXK_TEL_DICT_PTR(d, ctx, next_sqb, w4_); + + /* W5 */ + CNXK_TEL_DICT_PTR(d, ctx, tail_sqb, w5_); + + /* W6 */ + CNXK_TEL_DICT_PTR(d, ctx, smenq_sqb, w6_); + + /* W7 */ + CNXK_TEL_DICT_PTR(d, ctx, smenq_next_sqb, w7_); + + /* W8 */ + CNXK_TEL_DICT_PTR(d, ctx, head_sqb, w8_); + + /* W9 */ + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_vld, w9_); + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_vlan1_ins_ena, w9_); + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_vlan0_ins_ena, w9_); + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_mps, w9_); + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_sb, w9_); + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_sizem1, w9_); + CNXK_TEL_DICT_INT(d, ctx, vfi_lso_total, w9_); + + /* W10 */ + CNXK_TEL_DICT_BF_PTR(d, ctx, scm_lso_rem, w10_); + + /* W11 */ + CNXK_TEL_DICT_BF_PTR(d, ctx, octs, w11_); + + /* W12 */ + CNXK_TEL_DICT_BF_PTR(d, ctx, pkts, w12_); + + /* W14 */ + CNXK_TEL_DICT_BF_PTR(d, ctx, drop_octs, w14_); + + /* W15 */ + CNXK_TEL_DICT_BF_PTR(d, ctx, drop_pkts, w15_); +} + +static int +cnxk_tel_nix_sq_ctx(struct roc_nix *roc_nix, uint8_t n, struct plt_tel_data *d) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct dev *dev = &nix->dev; + struct npa_lf *npa_lf; + volatile void *qctx; + int rc = -1; + + npa_lf = idev_npa_obj_get(); + if (npa_lf == NULL) + return NPA_ERR_DEVICE_NOT_BOUNDED; + + rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_SQ, n, &qctx); + if (rc) { + plt_err("Failed to get rq context"); + return rc; + } + + if (roc_model_is_cn9k()) + nix_sq_ctx_cn9k(&qctx, d); + else + nix_sq_ctx(&qctx, d); + + return 0; +} + +static int +cnxk_nix_tel_handle_list(const char *cmd __plt_unused, + const char *params __plt_unused, + struct plt_tel_data *d) +{ + struct nix_tel_node *node; + struct roc_nix *roc_nix; + + plt_tel_data_start_array(d, PLT_TEL_STRING_VAL); + + TAILQ_FOREACH(node, &nix_list, node) { + roc_nix = node->nix; + plt_tel_data_add_array_string(d, roc_nix->pci_dev->name); + } + + return 0; +} + +static int +cnxk_nix_tel_handle_info(const char *cmd __plt_unused, const char *params, + struct plt_tel_data *d) +{ + char name[PCI_PRI_STR_SIZE]; + struct nix_tel_node *node; + + if (params == NULL || strlen(params) == 0 || !isdigit(*params)) + return -1; + + plt_strlcpy(name, params, PCI_PRI_STR_SIZE); + + node = nix_tel_node_get_by_pcidev_name(name); + if (!node) + return -1; + + plt_tel_data_start_dict(d); + return cnxk_tel_nix(node->nix, d); +} + +static int +cnxk_nix_tel_handle_info_x(const char *cmd, const char *params, + struct plt_tel_data *d) +{ + struct nix_tel_node *node; + char *name, *param; + char buf[1024]; + int rc = -1; + + if (params == NULL || strlen(params) == 0 || !isdigit(*params)) + goto exit; + + plt_strlcpy(buf, params, PCI_PRI_STR_SIZE + 1); + name = strtok(buf, ","); + param = strtok(NULL, "\0"); + + node = nix_tel_node_get_by_pcidev_name(name); + if (!node) + goto exit; + + plt_tel_data_start_dict(d); + + if (strstr(cmd, "rq")) { + char *tok = strtok(param, ","); + int rq; + + if (!tok) + goto exit; + + rq = strtol(tok, NULL, 10); + if ((node->n_rq <= rq) || (rq < 0)) + goto exit; + + if (strstr(cmd, "ctx")) + rc = cnxk_tel_nix_rq_ctx(node->nix, rq, d); + else + rc = cnxk_tel_nix_rq(node->rqs[rq], d); + + } else if (strstr(cmd, "cq")) { + char *tok = strtok(param, ","); + int cq; + + if (!tok) + goto exit; + + cq = strtol(tok, NULL, 10); + if ((node->n_cq <= cq) || (cq < 0)) + goto exit; + + if (strstr(cmd, "ctx")) + rc = cnxk_tel_nix_cq_ctx(node->nix, cq, d); + else + rc = cnxk_tel_nix_cq(node->cqs[cq], d); + + } else if (strstr(cmd, "sq")) { + char *tok = strtok(param, ","); + int sq; + + if (!tok) + goto exit; + + sq = strtol(tok, NULL, 10); + if ((node->n_sq <= sq) || (sq < 0)) + goto exit; + + if (strstr(cmd, "ctx")) + rc = cnxk_tel_nix_sq_ctx(node->nix, sq, d); + else + rc = cnxk_tel_nix_sq(node->sqs[sq], d); + } + +exit: + return rc; +} + +PLT_INIT(cnxk_telemetry_nix_init) +{ + TAILQ_INIT(&nix_list); + + plt_telemetry_register_cmd( + "/cnxk/nix/list", cnxk_nix_tel_handle_list, + "Returns list of available NIX devices. Takes no parameters"); + plt_telemetry_register_cmd( + "/cnxk/nix/info", cnxk_nix_tel_handle_info, + "Returns nix information. Parameters: pci id"); + plt_telemetry_register_cmd( + "/cnxk/nix/rq/info", cnxk_nix_tel_handle_info_x, + "Returns nix rq information. Parameters: pci id, rq id"); + plt_telemetry_register_cmd( + "/cnxk/nix/rq/ctx", cnxk_nix_tel_handle_info_x, + "Returns nix rq context. Parameters: pci id, rq id"); + plt_telemetry_register_cmd( + "/cnxk/nix/cq/info", cnxk_nix_tel_handle_info_x, + "Returns nix cq information. Parameters: pci id, cq id"); + plt_telemetry_register_cmd( + "/cnxk/nix/cq/ctx", cnxk_nix_tel_handle_info_x, + "Returns nix cq context. Parameters: pci id, cq id"); + plt_telemetry_register_cmd( + "/cnxk/nix/sq/info", cnxk_nix_tel_handle_info_x, + "Returns nix sq information. Parameters: pci id, sq id"); + plt_telemetry_register_cmd( + "/cnxk/nix/sq/ctx", cnxk_nix_tel_handle_info_x, + "Returns nix sq context. Parameters: pci id, sq id"); +} diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index d88cfbc7fa..7b8a4c6633 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -73,6 +73,7 @@ includes += include_directories('../../../lib/ethdev') includes += include_directories('../../../lib/meter') # Telemetry common code -sources += files('cnxk_telemetry_npa.c') +sources += files('cnxk_telemetry_npa.c', + 'cnxk_telemetry_nix.c') deps += ['bus_pci', 'net', 'telemetry'] diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index b7ef843b4b..64156ceb19 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -184,6 +184,8 @@ roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq, nix->sqs = plt_zmalloc(sizeof(struct roc_nix_sq *) * nb_txq, 0); if (!nix->sqs) return -ENOMEM; + + nix_tel_node_add(roc_nix); fail: return rc; } @@ -419,6 +421,7 @@ roc_nix_dev_init(struct roc_nix *roc_nix) dev_fini: rc |= dev_fini(dev, pci_dev); fail: + nix_tel_node_del(roc_nix); return rc; } diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 8beb5454b7..2f5eefd6ec 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -427,4 +427,13 @@ int nix_lf_int_reg_dump(uintptr_t nix_lf_base, uint64_t *data, uint16_t qints, int nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid, __io void **ctx_p); +/* + * Telemetry + */ +int nix_tel_node_add(struct roc_nix *roc_nix); +void nix_tel_node_del(struct roc_nix *roc_nix); +int nix_tel_node_add_rq(struct roc_nix_rq *rq); +int nix_tel_node_add_cq(struct roc_nix_cq *cq); +int nix_tel_node_add_sq(struct roc_nix_sq *sq); + #endif /* _ROC_NIX_PRIV_H_ */ diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 422eef124c..0510f9692e 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -387,7 +387,11 @@ roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena) if (rc) return rc; - return mbox_process(mbox); + rc = mbox_process(mbox); + if (rc) + return rc; + + return nix_tel_node_add_rq(rq); } int @@ -415,7 +419,11 @@ roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena) if (rc) return rc; - return mbox_process(mbox); + rc = mbox_process(mbox); + if (rc) + return rc; + + return nix_tel_node_add_rq(rq); } int @@ -504,7 +512,7 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq) if (rc) goto free_mem; - return 0; + return nix_tel_node_add_cq(cq); free_mem: plt_free(cq->desc_base); @@ -888,6 +896,7 @@ roc_nix_sq_init(struct roc_nix *roc_nix, struct roc_nix_sq *sq) ((qid & RVU_CN9K_LMT_SLOT_MASK) << 12)); } + rc = nix_tel_node_add_sq(sq); return rc; nomem: plt_free(sq->fc); diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 59af6f4975..731c5bc3b3 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -146,9 +146,11 @@ #define plt_strlcpy rte_strlcpy #define PLT_TEL_INT_VAL RTE_TEL_INT_VAL +#define PLT_TEL_STRING_VAL RTE_TEL_STRING_VAL #define plt_tel_data rte_tel_data #define plt_tel_data_start_array rte_tel_data_start_array #define plt_tel_data_add_array_int rte_tel_data_add_array_int +#define plt_tel_data_add_array_string rte_tel_data_add_array_string #define plt_tel_data_start_dict rte_tel_data_start_dict #define plt_tel_data_add_dict_int rte_tel_data_add_dict_int #define plt_tel_data_add_dict_ptr(d, n, v) \ From patchwork Tue Oct 19 11:27:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gowrishankar Muthukrishnan X-Patchwork-Id: 102216 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4026CA0C43; Tue, 19 Oct 2021 13:28:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D189B41185; Tue, 19 Oct 2021 13:27:56 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id E32E141185 for ; Tue, 19 Oct 2021 13:27:54 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19JAKgSW009140 for ; Tue, 19 Oct 2021 04:27:54 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; 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Tue, 19 Oct 2021 04:27:52 -0700 Received: from localhost.localdomain (unknown [10.28.34.38]) by maili.marvell.com (Postfix) with ESMTP id 88A523F7087; Tue, 19 Oct 2021 04:27:49 -0700 (PDT) From: Gowrishankar Muthukrishnan To: CC: , , , , , , , , Gowrishankar Muthukrishnan Date: Tue, 19 Oct 2021 16:57:26 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-GUID: 4TK8GQFs-1e2BPRyYTItPehsgrl_DG4q X-Proofpoint-ORIG-GUID: 4TK8GQFs-1e2BPRyYTItPehsgrl_DG4q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-19_01,2021-10-19_01,2020-04-07_01 Subject: [dpdk-dev] [v10 3/4] mempool/cnxk: add telemetry endpoints mempool X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Adding telemetry endpoints to cnxk mempool driver. Signed-off-by: Gowrishankar Muthukrishnan Reviewed-by: Harman Kalra --- drivers/mempool/cnxk/cnxk_mempool_telemetry.c | 57 +++++++++++++++++++ drivers/mempool/cnxk/meson.build | 1 + 2 files changed, 58 insertions(+) create mode 100644 drivers/mempool/cnxk/cnxk_mempool_telemetry.c diff --git a/drivers/mempool/cnxk/cnxk_mempool_telemetry.c b/drivers/mempool/cnxk/cnxk_mempool_telemetry.c new file mode 100644 index 0000000000..c71798d7fd --- /dev/null +++ b/drivers/mempool/cnxk/cnxk_mempool_telemetry.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include +#include +#include + +#include + +#include "cnxk_mempool.h" +#include "cnxk_telemetry.h" + +struct mempool_info_cb_arg { + char *pool_name; + struct rte_tel_data *d; +}; + +static void +mempool_info_cb(struct rte_mempool *mp, void *arg) +{ + struct mempool_info_cb_arg *info = (struct mempool_info_cb_arg *)arg; + int aura_id; + + if (strncmp(mp->name, info->pool_name, RTE_MEMZONE_NAMESIZE)) + return; + + aura_id = roc_npa_aura_handle_to_aura(mp->pool_id); + rte_tel_data_add_dict_int(info->d, "aura_id", aura_id); +} + +static int +mempool_tel_handle_info(const char *cmd __rte_unused, const char *params, + struct rte_tel_data *d) +{ + struct mempool_info_cb_arg mp_arg; + char name[RTE_MEMZONE_NAMESIZE]; + + if (params == NULL || strlen(params) == 0) + return -EINVAL; + + rte_strlcpy(name, params, RTE_MEMZONE_NAMESIZE); + + rte_tel_data_start_dict(d); + mp_arg.pool_name = name; + mp_arg.d = d; + rte_mempool_walk(mempool_info_cb, &mp_arg); + + return 0; +} + +RTE_INIT(cnxk_mempool_init_telemetry) +{ + rte_telemetry_register_cmd( + "/cnxk/mempool/info", mempool_tel_handle_info, + "Returns mempool info. Parameters: pool_name"); +} diff --git a/drivers/mempool/cnxk/meson.build b/drivers/mempool/cnxk/meson.build index e28a9e044d..d5d1978569 100644 --- a/drivers/mempool/cnxk/meson.build +++ b/drivers/mempool/cnxk/meson.build @@ -11,6 +11,7 @@ endif sources = files( 'cnxk_mempool.c', 'cnxk_mempool_ops.c', + 'cnxk_mempool_telemetry.c', 'cn9k_mempool_ops.c', 'cn10k_mempool_ops.c', ) From patchwork Tue Oct 19 11:27:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gowrishankar Muthukrishnan X-Patchwork-Id: 102217 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 22F94A0C43; Tue, 19 Oct 2021 13:28:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DDB124116C; Tue, 19 Oct 2021 13:27:59 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C33424118A for ; Tue, 19 Oct 2021 13:27:58 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J8S5Up032025 for ; Tue, 19 Oct 2021 04:27:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ef1bbLbF+FEreux/D9UHQqY3izQIn888Cbsyy8BXmXU=; b=LbFrmWSD4CJ4X+vu2FGotj8Wp8m18F1zK3nQDwaLurb31v1NrJcNC7cIZBdw4DMGVztu vM/dLANe6I0Ob07bxp1MSnCh+lQpMqDGZCQtBjRiIozo2Hss8uX2xDvKKBCweTTqrW4d 7iQytxfAFcgb3rEGW8YsXZd7mdhVaJ8WuuYFo9b9aTP+hu+AH91B/xm9D8Nvt9QFippC 0ZNAjRcYaychPHlRSYTrkYafnNufv66nRPzWObg9VcqCHhPrsXOgakBQbvE2N8WGoHU/ peFBtJ09K4J12I9tj0Q4R5zLS++PPHW/wGpwV9UlYMuNyxbEWiCMQ8FXqBhCJP6kwj8C yw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3bsfk4bevj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 19 Oct 2021 04:27:58 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 04:27:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 19 Oct 2021 04:27:56 -0700 Received: from localhost.localdomain (unknown [10.28.34.38]) by maili.marvell.com (Postfix) with ESMTP id 277473F7084; Tue, 19 Oct 2021 04:27:52 -0700 (PDT) From: Gowrishankar Muthukrishnan To: CC: , , , , , , , , Gowrishankar Muthukrishnan Date: Tue, 19 Oct 2021 16:57:27 +0530 Message-ID: <0a43869f429ee91ef0df81314d440aa4329fc1dd.1634642657.git.gmuthukrishn@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 3pliWqrFnd4s6hEeyRE55fUmJDgpCaBq X-Proofpoint-GUID: 3pliWqrFnd4s6hEeyRE55fUmJDgpCaBq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_10,2021-10-19_01,2020-04-07_01 Subject: [dpdk-dev] [v10 4/4] net/cnxk: add telemetry endpoints to ethdev X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add telemetry endpoints to ethdev. Signed-off-by: Gowrishankar Muthukrishnan Reviewed-by: Harman Kalra --- drivers/net/cnxk/cnxk_ethdev_telemetry.c | 93 ++++++++++++++++++++++++ drivers/net/cnxk/meson.build | 1 + 2 files changed, 94 insertions(+) create mode 100644 drivers/net/cnxk/cnxk_ethdev_telemetry.c diff --git a/drivers/net/cnxk/cnxk_ethdev_telemetry.c b/drivers/net/cnxk/cnxk_ethdev_telemetry.c new file mode 100644 index 0000000000..83bc65848c --- /dev/null +++ b/drivers/net/cnxk/cnxk_ethdev_telemetry.c @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ + +#include + +#include "cnxk_ethdev.h" + +/* Macro to count no of words in eth_info_s size */ +#define ETH_INFO_SZ \ + (RTE_ALIGN_CEIL(sizeof(struct eth_info_s), sizeof(uint64_t)) / \ + sizeof(uint64_t)) +#define MACADDR_LEN 18 + +static int +ethdev_tel_handle_info(const char *cmd __rte_unused, + const char *params __rte_unused, struct rte_tel_data *d) +{ + struct rte_eth_dev *eth_dev; + struct rte_tel_data *i_data; + struct cnxk_eth_dev *dev; + union eth_info_u { + struct eth_info_s { + /** PF/VF information */ + uint16_t pf_func; + uint8_t max_mac_entries; + bool dmac_filter_ena; + uint8_t dmac_filter_count; + uint8_t ptype_disable; + bool scalar_ena; + bool ptp_ena; + /* Platform specific offload flags */ + uint16_t rx_offload_flags; + uint16_t tx_offload_flags; + } info; + uint64_t val[ETH_INFO_SZ]; + } eth_info; + struct eth_info_s *info; + unsigned int i, j = 0; + int n_ports; + + n_ports = rte_eth_dev_count_avail(); + if (!n_ports) { + plt_err("No active ethernet ports found."); + return -1; + } + + rte_tel_data_start_dict(d); + rte_tel_data_add_dict_int(d, "n_ports", n_ports); + + i_data = rte_tel_data_alloc(); + rte_tel_data_start_array(i_data, RTE_TEL_U64_VAL); + + for (i = 0; i < RTE_MAX_ETHPORTS; i++) { + /* Skip if port is unused */ + if (!rte_eth_dev_is_valid_port(i)) + continue; + + eth_dev = &rte_eth_devices[i]; + if (eth_dev) { + memset(ð_info, 0, sizeof(eth_info)); + info = ð_info.info; + dev = cnxk_eth_pmd_priv(eth_dev); + if (dev) { + info->pf_func = roc_nix_get_pf_func(&dev->nix); + info->max_mac_entries = dev->max_mac_entries; + info->dmac_filter_ena = dev->dmac_filter_enable; + info->dmac_filter_count = + dev->dmac_filter_count; + info->ptype_disable = dev->ptype_disable; + info->scalar_ena = dev->scalar_ena; + info->ptp_ena = dev->ptp_en; + info->rx_offload_flags = dev->rx_offload_flags; + info->tx_offload_flags = dev->tx_offload_flags; + } + + for (j = 0; j < ETH_INFO_SZ; j++) + rte_tel_data_add_array_u64(i_data, + eth_info.val[j]); + + j++; + } + } + + rte_tel_data_add_dict_container(d, "info", i_data, 0); + return 0; +} + +RTE_INIT(cnxk_ethdev_init_telemetry) +{ + rte_telemetry_register_cmd("/cnxk/ethdev/info", ethdev_tel_handle_info, + "Returns ethdev device information"); +} diff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build index d86188fed7..341ac99771 100644 --- a/drivers/net/cnxk/meson.build +++ b/drivers/net/cnxk/meson.build @@ -13,6 +13,7 @@ sources = files( 'cnxk_ethdev_devargs.c', 'cnxk_ethdev_ops.c', 'cnxk_ethdev_sec.c', + 'cnxk_ethdev_telemetry.c', 'cnxk_link.c', 'cnxk_lookup.c', 'cnxk_ptp.c',