From patchwork Tue Oct 26 08:02:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 102871 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 622F6A0C47; Tue, 26 Oct 2021 10:02:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7E6F7410F8; Tue, 26 Oct 2021 10:02:22 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 6E036410E2 for ; Tue, 26 Oct 2021 10:02:19 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BEAE51FB; Tue, 26 Oct 2021 01:02:18 -0700 (PDT) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.103]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 317B53F70D; Tue, 26 Oct 2021 01:02:16 -0700 (PDT) From: Feifei Wang To: Ruifeng Wang Cc: dev@dpdk.org, nd@arm.com, Feifei Wang Date: Tue, 26 Oct 2021 16:02:00 +0800 Message-Id: <20211026080204.149550-2-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211026080204.149550-1-feifei.wang2@arm.com> References: <20210902053253.3017858-1-feifei.wang2@arm.com> <20211026080204.149550-1-feifei.wang2@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 1/5] eal: add new definitions for wait scheme X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Introduce macros as generic interface for address monitoring. For different size, encapsulate '__LOAD_EXC_16', '__LOAD_EXC_32' and '__LOAD_EXC_64' into a new macro '__LOAD_EXC'. Furthermore, to prevent compilation warning in arm: ---------------------------------------------- 'warning: implicit declaration of function ...' ---------------------------------------------- Delete 'undef' constructions for '__LOAD_EXC_xx', '__SEVL' and '__WFE'. This is because original macros are undefine at the end of the file. If new macro 'rte_wait_event' calls them in other files, they will be seen as 'not defined'. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang --- lib/eal/arm/include/rte_pause_64.h | 135 ++++++++++++++++------------ lib/eal/include/generic/rte_pause.h | 27 ++++++ 2 files changed, 105 insertions(+), 57 deletions(-) diff --git a/lib/eal/arm/include/rte_pause_64.h b/lib/eal/arm/include/rte_pause_64.h index e87d10b8cc..1fea0dec63 100644 --- a/lib/eal/arm/include/rte_pause_64.h +++ b/lib/eal/arm/include/rte_pause_64.h @@ -31,20 +31,12 @@ static inline void rte_pause(void) /* Put processor into low power WFE(Wait For Event) state. */ #define __WFE() { asm volatile("wfe" : : : "memory"); } -static __rte_always_inline void -rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, - int memorder) -{ - uint16_t value; - - assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); - - /* - * Atomic exclusive load from addr, it returns the 16-bit content of - * *addr while making it 'monitored',when it is written by someone - * else, the 'monitored' state is cleared and a event is generated - * implicitly to exit WFE. - */ +/* + * Atomic exclusive load from addr, it returns the 16-bit content of + * *addr while making it 'monitored', when it is written by someone + * else, the 'monitored' state is cleared and an event is generated + * implicitly to exit WFE. + */ #define __LOAD_EXC_16(src, dst, memorder) { \ if (memorder == __ATOMIC_RELAXED) { \ asm volatile("ldxrh %w[tmp], [%x[addr]]" \ @@ -58,6 +50,62 @@ rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, : "memory"); \ } } +/* + * Atomic exclusive load from addr, it returns the 32-bit content of + * *addr while making it 'monitored', when it is written by someone + * else, the 'monitored' state is cleared and an event is generated + * implicitly to exit WFE. + */ +#define __LOAD_EXC_32(src, dst, memorder) { \ + if (memorder == __ATOMIC_RELAXED) { \ + asm volatile("ldxr %w[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r"(src) \ + : "memory"); \ + } else { \ + asm volatile("ldaxr %w[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r"(src) \ + : "memory"); \ + } } + +/* + * Atomic exclusive load from addr, it returns the 64-bit content of + * *addr while making it 'monitored', when it is written by someone + * else, the 'monitored' state is cleared and an event is generated + * implicitly to exit WFE. + */ +#define __LOAD_EXC_64(src, dst, memorder) { \ + if (memorder == __ATOMIC_RELAXED) { \ + asm volatile("ldxr %x[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r"(src) \ + : "memory"); \ + } else { \ + asm volatile("ldaxr %x[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r"(src) \ + : "memory"); \ + } } + +#define __LOAD_EXC(src, dst, memorder, size) { \ + assert(size == 16 || size == 32 || size == 64); \ + if (size == 16) \ + __LOAD_EXC_16(src, dst, memorder) \ + else if (size == 32) \ + __LOAD_EXC_32(src, dst, memorder) \ + else if (size == 64) \ + __LOAD_EXC_64(src, dst, memorder) \ +} + +static __rte_always_inline void +rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, + int memorder) +{ + uint16_t value; + + assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); + __LOAD_EXC_16(addr, value, memorder) if (value != expected) { __SEVL() @@ -66,7 +114,6 @@ rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, __LOAD_EXC_16(addr, value, memorder) } while (value != expected); } -#undef __LOAD_EXC_16 } static __rte_always_inline void @@ -77,25 +124,6 @@ rte_wait_until_equal_32(volatile uint32_t *addr, uint32_t expected, assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); - /* - * Atomic exclusive load from addr, it returns the 32-bit content of - * *addr while making it 'monitored',when it is written by someone - * else, the 'monitored' state is cleared and a event is generated - * implicitly to exit WFE. - */ -#define __LOAD_EXC_32(src, dst, memorder) { \ - if (memorder == __ATOMIC_RELAXED) { \ - asm volatile("ldxr %w[tmp], [%x[addr]]" \ - : [tmp] "=&r" (dst) \ - : [addr] "r"(src) \ - : "memory"); \ - } else { \ - asm volatile("ldaxr %w[tmp], [%x[addr]]" \ - : [tmp] "=&r" (dst) \ - : [addr] "r"(src) \ - : "memory"); \ - } } - __LOAD_EXC_32(addr, value, memorder) if (value != expected) { __SEVL() @@ -104,7 +132,6 @@ rte_wait_until_equal_32(volatile uint32_t *addr, uint32_t expected, __LOAD_EXC_32(addr, value, memorder) } while (value != expected); } -#undef __LOAD_EXC_32 } static __rte_always_inline void @@ -115,25 +142,6 @@ rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected, assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); - /* - * Atomic exclusive load from addr, it returns the 64-bit content of - * *addr while making it 'monitored',when it is written by someone - * else, the 'monitored' state is cleared and a event is generated - * implicitly to exit WFE. - */ -#define __LOAD_EXC_64(src, dst, memorder) { \ - if (memorder == __ATOMIC_RELAXED) { \ - asm volatile("ldxr %x[tmp], [%x[addr]]" \ - : [tmp] "=&r" (dst) \ - : [addr] "r"(src) \ - : "memory"); \ - } else { \ - asm volatile("ldaxr %x[tmp], [%x[addr]]" \ - : [tmp] "=&r" (dst) \ - : [addr] "r"(src) \ - : "memory"); \ - } } - __LOAD_EXC_64(addr, value, memorder) if (value != expected) { __SEVL() @@ -143,10 +151,23 @@ rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected, } while (value != expected); } } -#undef __LOAD_EXC_64 -#undef __SEVL -#undef __WFE +#define rte_wait_event(addr, mask, cond, expected, memorder) \ +do { \ + RTE_BUILD_BUG_ON(!__builtin_constant_p(memorder)); \ + RTE_BUILD_BUG_ON(memorder != __ATOMIC_ACQUIRE && \ + memorder != __ATOMIC_RELAXED); \ + uint32_t size = sizeof(*(addr)) << 3; \ + typeof(*(addr)) value = 0; \ + __LOAD_EXC((addr), value, memorder, size) \ + if ((value & (mask)) cond expected) { \ + __SEVL() \ + do { \ + __WFE() \ + __LOAD_EXC((addr), value, memorder, size) \ + } while ((value & (mask)) cond expected); \ + } \ +} while (0) #endif diff --git a/lib/eal/include/generic/rte_pause.h b/lib/eal/include/generic/rte_pause.h index 668ee4a184..e31a006844 100644 --- a/lib/eal/include/generic/rte_pause.h +++ b/lib/eal/include/generic/rte_pause.h @@ -111,6 +111,33 @@ rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected, while (__atomic_load_n(addr, memorder) != expected) rte_pause(); } + +/* + * Wait until *addr breaks the condition, with a relaxed memory + * ordering model meaning the loads around this API can be reordered. + * + * @param addr + * A pointer to the memory location. + * @param mask + * A mask of value bits in interest. + * @param cond + * A symbol representing the condition. + * @param expected + * An expected value to be in the memory location. + * @param memorder + * Two different memory orders that can be specified: + * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to + * C++11 memory orders with the same names, see the C++11 standard or + * the GCC wiki on atomic synchronization for detailed definition. + */ +#define rte_wait_event(addr, mask, cond, expected, memorder) \ +do { \ + RTE_BUILD_BUG_ON(!__builtin_constant_p(memorder)); \ + RTE_BUILD_BUG_ON(memorder != __ATOMIC_ACQUIRE && \ + memorder != __ATOMIC_RELAXED); \ + while ((__atomic_load_n((addr), (memorder)) & (mask)) cond expected) \ + rte_pause(); \ +} while (0) #endif #endif /* _RTE_PAUSE_H_ */ From patchwork Tue Oct 26 08:02:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 102872 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BADC3A0C47; Tue, 26 Oct 2021 10:02:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E655341173; Tue, 26 Oct 2021 10:02:24 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 6FC44410EB for ; Tue, 26 Oct 2021 10:02:21 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EEE261FB; Tue, 26 Oct 2021 01:02:20 -0700 (PDT) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.103]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5B9073F70D; Tue, 26 Oct 2021 01:02:19 -0700 (PDT) From: Feifei Wang To: Cc: dev@dpdk.org, nd@arm.com, Feifei Wang , Ruifeng Wang Date: Tue, 26 Oct 2021 16:02:01 +0800 Message-Id: <20211026080204.149550-3-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211026080204.149550-1-feifei.wang2@arm.com> References: <20210902053253.3017858-1-feifei.wang2@arm.com> <20211026080204.149550-1-feifei.wang2@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 2/5] eal: use wait event for read pflock X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Instead of polling for read pflock update, use wait event scheme for this case. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang --- lib/eal/include/generic/rte_pflock.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/lib/eal/include/generic/rte_pflock.h b/lib/eal/include/generic/rte_pflock.h index e57c179ef2..7573b036bf 100644 --- a/lib/eal/include/generic/rte_pflock.h +++ b/lib/eal/include/generic/rte_pflock.h @@ -121,9 +121,7 @@ rte_pflock_read_lock(rte_pflock_t *pf) return; /* Wait for current write phase to complete. */ - while ((__atomic_load_n(&pf->rd.in, __ATOMIC_ACQUIRE) - & RTE_PFLOCK_WBITS) == w) - rte_pause(); + rte_wait_event(&pf->rd.in, RTE_PFLOCK_WBITS, ==, w, __ATOMIC_ACQUIRE); } /** From patchwork Tue Oct 26 08:02:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 102873 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 210A8A0C47; Tue, 26 Oct 2021 10:02:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 010D04117F; Tue, 26 Oct 2021 10:02:26 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id E7F5541165 for ; Tue, 26 Oct 2021 10:02:23 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 694891FB; Tue, 26 Oct 2021 01:02:23 -0700 (PDT) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.103]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8BD453F70D; Tue, 26 Oct 2021 01:02:21 -0700 (PDT) From: Feifei Wang To: Honnappa Nagarahalli Cc: dev@dpdk.org, nd@arm.com, Feifei Wang , Ruifeng Wang Date: Tue, 26 Oct 2021 16:02:02 +0800 Message-Id: <20211026080204.149550-4-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211026080204.149550-1-feifei.wang2@arm.com> References: <20210902053253.3017858-1-feifei.wang2@arm.com> <20211026080204.149550-1-feifei.wang2@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 3/5] eal: use wait event scheme for mcslock X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Instead of polling for mcslock to be updated, use wait event scheme for this case. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang --- lib/eal/include/generic/rte_mcslock.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/lib/eal/include/generic/rte_mcslock.h b/lib/eal/include/generic/rte_mcslock.h index 34f33c64a5..806a2b2c7e 100644 --- a/lib/eal/include/generic/rte_mcslock.h +++ b/lib/eal/include/generic/rte_mcslock.h @@ -116,8 +116,13 @@ rte_mcslock_unlock(rte_mcslock_t **msl, rte_mcslock_t *me) /* More nodes added to the queue by other CPUs. * Wait until the next pointer is set. */ - while (__atomic_load_n(&me->next, __ATOMIC_RELAXED) == NULL) - rte_pause(); +#ifdef RTE_ARCH_32 + rte_wait_event((uint32_t *)&me->next, UINT32_MAX, ==, 0, + __ATOMIC_RELAXED); +#else + rte_wait_event((uint64_t *)&me->next, UINT64_MAX, ==, 0, + __ATOMIC_RELAXED); +#endif } /* Pass lock to next waiter. */ From patchwork Tue Oct 26 08:02:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 102874 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3FA37A0C47; Tue, 26 Oct 2021 10:02:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F202D4118B; Tue, 26 Oct 2021 10:02:28 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 4F4804003E for ; Tue, 26 Oct 2021 10:02:26 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CE2191FB; Tue, 26 Oct 2021 01:02:25 -0700 (PDT) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.103]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 05EA83F70D; Tue, 26 Oct 2021 01:02:23 -0700 (PDT) From: Feifei Wang To: Konstantin Ananyev Cc: dev@dpdk.org, nd@arm.com, Feifei Wang , Ruifeng Wang Date: Tue, 26 Oct 2021 16:02:03 +0800 Message-Id: <20211026080204.149550-5-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211026080204.149550-1-feifei.wang2@arm.com> References: <20210902053253.3017858-1-feifei.wang2@arm.com> <20211026080204.149550-1-feifei.wang2@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 4/5] lib/bpf: use wait event scheme for Rx/Tx iteration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Instead of polling for cbi->use to be updated, use wait event scheme. Furthermore, delete 'const' for 'bpf_eth_cbi_wait'. This is because of a compilation error: ----------------------------------------------------------------------- ../lib/eal/include/rte_common.h:36:13: error: read-only variable ‘value’ used as ‘asm’ output 36 | #define asm __asm__ | ^~~~~~~ ../lib/eal/arm/include/rte_pause_64.h:66:3: note: in expansion of macro ‘asm’ 66 | asm volatile("ldaxr %w[tmp], [%x[addr]]" \ | ^~~ ../lib/eal/arm/include/rte_pause_64.h:96:3: note: in expansion of macro ‘__LOAD_EXC_32’ 96 | __LOAD_EXC_32((src), dst, memorder) \ | ^~~~~~~~~~~~~ ../lib/eal/arm/include/rte_pause_64.h:167:4: note: in expansion of macro ‘__LOAD_EXC’ 167 | __LOAD_EXC((addr), value, memorder, size) \ | ^~~~~~~~~~ ../lib/bpf/bpf_pkt.c:125:3: note: in expansion of macro ‘rte_wait_event’ 125 | rte_wait_event(&cbi->use, UINT32_MAX, ==, puse, ----------------------------------------------------------------------- Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang --- lib/bpf/bpf_pkt.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/lib/bpf/bpf_pkt.c b/lib/bpf/bpf_pkt.c index 6e8248f0d6..213d44a75a 100644 --- a/lib/bpf/bpf_pkt.c +++ b/lib/bpf/bpf_pkt.c @@ -111,9 +111,9 @@ bpf_eth_cbi_unuse(struct bpf_eth_cbi *cbi) * Waits till datapath finished using given callback. */ static void -bpf_eth_cbi_wait(const struct bpf_eth_cbi *cbi) +bpf_eth_cbi_wait(struct bpf_eth_cbi *cbi) { - uint32_t nuse, puse; + uint32_t puse; /* make sure all previous loads and stores are completed */ rte_smp_mb(); @@ -122,11 +122,8 @@ bpf_eth_cbi_wait(const struct bpf_eth_cbi *cbi) /* in use, busy wait till current RX/TX iteration is finished */ if ((puse & BPF_ETH_CBI_INUSE) != 0) { - do { - rte_pause(); - rte_compiler_barrier(); - nuse = cbi->use; - } while (nuse == puse); + rte_wait_event(&cbi->use, UINT32_MAX, ==, puse, + __ATOMIC_RELAXED); } } From patchwork Tue Oct 26 08:02:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 102875 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C038AA0C47; Tue, 26 Oct 2021 10:02:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 007A94116F; Tue, 26 Oct 2021 10:02:32 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id B8CD941167 for ; Tue, 26 Oct 2021 10:02:28 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 43FAF1FB; Tue, 26 Oct 2021 01:02:28 -0700 (PDT) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.103]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6DF093F70D; Tue, 26 Oct 2021 01:02:26 -0700 (PDT) From: Feifei Wang To: David Hunt Cc: dev@dpdk.org, nd@arm.com, Feifei Wang , Ruifeng Wang Date: Tue, 26 Oct 2021 16:02:04 +0800 Message-Id: <20211026080204.149550-6-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211026080204.149550-1-feifei.wang2@arm.com> References: <20210902053253.3017858-1-feifei.wang2@arm.com> <20211026080204.149550-1-feifei.wang2@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 5/5] lib/distributor: use wait event scheme X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Instead of polling for bufptr64 to be updated, use wait event for this case. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang --- lib/distributor/rte_distributor_single.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/lib/distributor/rte_distributor_single.c b/lib/distributor/rte_distributor_single.c index f4725b1d0b..d52b24a453 100644 --- a/lib/distributor/rte_distributor_single.c +++ b/lib/distributor/rte_distributor_single.c @@ -33,9 +33,8 @@ rte_distributor_request_pkt_single(struct rte_distributor_single *d, union rte_distributor_buffer_single *buf = &d->bufs[worker_id]; int64_t req = (((int64_t)(uintptr_t)oldpkt) << RTE_DISTRIB_FLAG_BITS) | RTE_DISTRIB_GET_BUF; - while (unlikely(__atomic_load_n(&buf->bufptr64, __ATOMIC_RELAXED) - & RTE_DISTRIB_FLAGS_MASK)) - rte_pause(); + rte_wait_event(&buf->bufptr64, RTE_DISTRIB_FLAGS_MASK, + !=, 0, __ATOMIC_RELAXED); /* Sync with distributor on GET_BUF flag. */ __atomic_store_n(&(buf->bufptr64), req, __ATOMIC_RELEASE); @@ -74,9 +73,8 @@ rte_distributor_return_pkt_single(struct rte_distributor_single *d, union rte_distributor_buffer_single *buf = &d->bufs[worker_id]; uint64_t req = (((int64_t)(uintptr_t)oldpkt) << RTE_DISTRIB_FLAG_BITS) | RTE_DISTRIB_RETURN_BUF; - while (unlikely(__atomic_load_n(&buf->bufptr64, __ATOMIC_RELAXED) - & RTE_DISTRIB_FLAGS_MASK)) - rte_pause(); + rte_wait_event(&buf->bufptr64, RTE_DISTRIB_FLAGS_MASK, + !=, 0, __ATOMIC_RELAXED); /* Sync with distributor on RETURN_BUF flag. */ __atomic_store_n(&(buf->bufptr64), req, __ATOMIC_RELEASE);