From patchwork Thu Jan 20 16:53:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 106144 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 11895A034E; Thu, 20 Jan 2022 17:53:28 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B1DC042719; Thu, 20 Jan 2022 17:53:26 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 0EEAA42710 for ; Thu, 20 Jan 2022 17:53:24 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20KCPIu7015675; Thu, 20 Jan 2022 08:53:24 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=GwPWpxP219KMxvHHVzox4ZLJSw5/DMDggYEZ3hUxNOA=; b=U6/0dTpD1UE1GBrzK4Crpa+98dMz7M5mPlP1UwSmbjDX3evtdJuENzyqPjRdrasEzpcg JVWjZlBKAZPEN2ajtPaCNUVbibf6/xbmFtRFcWJ2qj9e0C8wHeLP+XK0bXWdANZarlTr JsK1qdMjIXqJCXtVl9mbpG1+j54TtAfbBOxerxc5FmWEf3N3/824dzpwmXGFfuddQAL/ IQk/de9Ix++QAC+VYvO7eII9PBlHkDYsAAJnENkWO/Sc911AZ76R4ibAIlW0nWI39Jmz nBa1I8rtmEu1JC9q5LD65dIesCBBJfoE1nKKanknbtQIC1NBbsKuN6lFuYRxIKhyBxqX 2A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3dpybrtq64-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 20 Jan 2022 08:53:24 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 20 Jan 2022 08:53:23 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 20 Jan 2022 08:53:23 -0800 Received: from localhost.localdomain (unknown [10.28.48.55]) by maili.marvell.com (Postfix) with ESMTP id 745003F7048; Thu, 20 Jan 2022 08:53:19 -0800 (PST) From: Akhil Goyal To: CC: , , , , , , , , , Vidya Sagar Velumuri Subject: [PATCH v2 1/4] common/cnxk: configure reassembly specific params Date: Thu, 20 Jan 2022 22:23:07 +0530 Message-ID: <20220120165310.4165567-2-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120165310.4165567-1-gakhil@marvell.com> References: <20220103160149.1715058-1-gakhil@marvell.com> <20220120165310.4165567-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 4bz__oJ1ZFRjcMNWiqDwKSQc-HI0GiEm X-Proofpoint-GUID: 4bz__oJ1ZFRjcMNWiqDwKSQc-HI0GiEm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-20_06,2022-01-20_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri When reassembly is enabled by application, set corresponding flags in SA during creation. Provide roc API to configure reassembly unit with active and zombie limits and step size Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/cnxk_security.c | 5 ++++- drivers/common/cnxk/roc_nix_inl.c | 24 ++++++++++++++++++++++++ drivers/common/cnxk/roc_nix_inl.h | 7 +++++++ drivers/common/cnxk/version.map | 1 + 4 files changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c index 30562b46e3..9bd85fc4b4 100644 --- a/drivers/common/cnxk/cnxk_security.c +++ b/drivers/common/cnxk/cnxk_security.c @@ -295,9 +295,12 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa, * second pass meta and no defrag. */ sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META; - sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG; + sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_NO_FRAG; sa->w0.s.pkind = ROC_OT_CPT_META_PKIND; + if (ipsec_xfrm->options.reass_en) + sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG; + /* ESN */ sa->w2.s.esn_en = !!ipsec_xfrm->options.esn; if (ipsec_xfrm->options.udp_encap) { diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index f0fc690417..5251b51f9e 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -200,6 +200,30 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi) return (sa_base + (spi * sz)); } +int +roc_nix_reass_configure(uint32_t max_wait_time, uint16_t max_frags) +{ + struct idev_cfg *idev = idev_get_cfg(); + struct roc_cpt *roc_cpt; + struct roc_cpt_rxc_time_cfg cfg; + + (void)max_frags; + roc_cpt = idev->cpt; + if (!roc_cpt) { + plt_err("Cannot support inline inbound, cryptodev not probed"); + return -ENOTSUP; + } + + cfg.step = (max_wait_time * 1000 / ROC_NIX_INL_REAS_ACTIVE_LIMIT); + cfg.zombie_limit = ROC_NIX_INL_REAS_ZOMBIE_LIMIT; + cfg.zombie_thres = ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD; + cfg.active_limit = ROC_NIX_INL_REAS_ACTIVE_LIMIT; + cfg.active_thres = ROC_NIX_INL_REAS_ACTIVE_THRESHOLD; + + roc_cpt_rxc_time_cfg(roc_cpt, &cfg); + return 0; +} + int roc_nix_inl_inb_init(struct roc_nix *roc_nix) { diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index abbeac684a..73a17276c4 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -43,6 +43,11 @@ /* Alignment of SA Base */ #define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16) +#define ROC_NIX_INL_REAS_ACTIVE_LIMIT 0xFFF +#define ROC_NIX_INL_REAS_ACTIVE_THRESHOLD 10 +#define ROC_NIX_INL_REAS_ZOMBIE_LIMIT 0xFFF +#define ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD 10 + static inline struct roc_onf_ipsec_inb_sa * roc_nix_inl_onf_ipsec_inb_sa(uintptr_t base, uint64_t idx) { @@ -124,6 +129,8 @@ void __roc_api roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev); bool __roc_api roc_nix_inl_dev_is_probed(void); void __roc_api roc_nix_inl_dev_lock(void); void __roc_api roc_nix_inl_dev_unlock(void); +int __roc_api roc_nix_reass_configure(uint32_t max_wait_time, + uint16_t max_frags); /* NIX Inline Inbound API */ int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 5a03b91784..eab6e6a432 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -204,6 +204,7 @@ INTERNAL { roc_nix_ptp_tx_ena_dis; roc_nix_queues_ctx_dump; roc_nix_ras_intr_ena_dis; + roc_nix_reass_configure; roc_nix_register_cq_irqs; roc_nix_register_queue_irqs; roc_nix_rq_dump; From patchwork Thu Jan 20 16:53:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 106145 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 09BE2A034E; Thu, 20 Jan 2022 17:53:36 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EAA564271B; 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Thu, 20 Jan 2022 08:53:31 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 20 Jan 2022 08:53:28 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 20 Jan 2022 08:53:28 -0800 Received: from localhost.localdomain (unknown [10.28.48.55]) by maili.marvell.com (Postfix) with ESMTP id 828A63F704C; Thu, 20 Jan 2022 08:53:23 -0800 (PST) From: Akhil Goyal To: CC: , , , , , , , , , Vidya Sagar Velumuri , Akhil Goyal , Nithin Dabilpuram Subject: [PATCH v2 2/4] net/cnxk: support IP reassembly Date: Thu, 20 Jan 2022 22:23:08 +0530 Message-ID: <20220120165310.4165567-3-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120165310.4165567-1-gakhil@marvell.com> References: <20220103160149.1715058-1-gakhil@marvell.com> <20220120165310.4165567-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 9W3hEpzdoGGLSTWf4sfgZC5F4jyqGdhE X-Proofpoint-GUID: 9W3hEpzdoGGLSTWf4sfgZC5F4jyqGdhE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-20_06,2022-01-20_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Add capability and support for inbound reassembly in cnxk driver. Register the dynamic field for IPsec reassembly. Attach the fragments using the dynamic field in case of incomplete reassembly Signed-off-by: Vidya Sagar Velumuri Signed-off-by: Akhil Goyal Signed-off-by: Nithin Dabilpuram --- drivers/event/cnxk/cn10k_eventdev.c | 1 - drivers/event/cnxk/cn10k_worker.h | 16 +- drivers/event/cnxk/deq/cn10k/deq_128_143.c | 12 + .../event/cnxk/deq/cn10k/deq_128_143_burst.c | 14 + drivers/event/cnxk/deq/cn10k/deq_128_143_ca.c | 12 + .../cnxk/deq/cn10k/deq_128_143_ca_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_128_143_ca_seg.c | 12 + .../cnxk/deq/cn10k/deq_128_143_ca_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_128_143_ca_tmo.c | 12 + .../cnxk/deq/cn10k/deq_128_143_ca_tmo_burst.c | 14 + .../cnxk/deq/cn10k/deq_128_143_ca_tmo_seg.c | 13 + .../deq/cn10k/deq_128_143_ca_tmo_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_128_143_dual.c | 12 + .../event/cnxk/deq/cn10k/deq_128_143_seg.c | 12 + .../cnxk/deq/cn10k/deq_128_143_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_128_143_tmo.c | 12 + .../cnxk/deq/cn10k/deq_128_143_tmo_burst.c | 14 + .../cnxk/deq/cn10k/deq_128_143_tmo_seg.c | 12 + .../deq/cn10k/deq_128_143_tmo_seg_burst.c | 14 + drivers/event/cnxk/deq/cn10k/deq_144_159.c | 12 + .../event/cnxk/deq/cn10k/deq_144_159_burst.c | 14 + drivers/event/cnxk/deq/cn10k/deq_144_159_ca.c | 12 + .../cnxk/deq/cn10k/deq_144_159_ca_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_144_159_ca_seg.c | 12 + .../cnxk/deq/cn10k/deq_144_159_ca_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_144_159_ca_tmo.c | 12 + .../cnxk/deq/cn10k/deq_144_159_ca_tmo_burst.c | 14 + .../cnxk/deq/cn10k/deq_144_159_ca_tmo_seg.c | 13 + .../deq/cn10k/deq_144_159_ca_tmo_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_144_159_dual.c | 12 + .../event/cnxk/deq/cn10k/deq_144_159_seg.c | 12 + .../cnxk/deq/cn10k/deq_144_159_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_144_159_tmo.c | 12 + .../cnxk/deq/cn10k/deq_144_159_tmo_burst.c | 14 + .../cnxk/deq/cn10k/deq_144_159_tmo_seg.c | 12 + .../deq/cn10k/deq_144_159_tmo_seg_burst.c | 14 + drivers/event/cnxk/deq/cn10k/deq_160_175.c | 12 + .../event/cnxk/deq/cn10k/deq_160_175_burst.c | 14 + drivers/event/cnxk/deq/cn10k/deq_160_175_ca.c | 12 + .../cnxk/deq/cn10k/deq_160_175_ca_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_160_175_ca_seg.c | 12 + .../cnxk/deq/cn10k/deq_160_175_ca_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_160_175_ca_tmo.c | 12 + .../cnxk/deq/cn10k/deq_160_175_ca_tmo_burst.c | 14 + .../cnxk/deq/cn10k/deq_160_175_ca_tmo_seg.c | 13 + .../deq/cn10k/deq_160_175_ca_tmo_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_160_175_dual.c | 12 + .../event/cnxk/deq/cn10k/deq_160_175_seg.c | 12 + .../cnxk/deq/cn10k/deq_160_175_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_160_175_tmo.c | 12 + .../cnxk/deq/cn10k/deq_160_175_tmo_burst.c | 14 + .../cnxk/deq/cn10k/deq_160_175_tmo_seg.c | 12 + .../deq/cn10k/deq_160_175_tmo_seg_burst.c | 14 + drivers/event/cnxk/deq/cn10k/deq_176_191.c | 12 + .../event/cnxk/deq/cn10k/deq_176_191_burst.c | 14 + drivers/event/cnxk/deq/cn10k/deq_176_191_ca.c | 12 + .../cnxk/deq/cn10k/deq_176_191_ca_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_176_191_ca_seg.c | 12 + .../cnxk/deq/cn10k/deq_176_191_ca_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_176_191_ca_tmo.c | 12 + .../cnxk/deq/cn10k/deq_176_191_ca_tmo_burst.c | 14 + .../cnxk/deq/cn10k/deq_176_191_ca_tmo_seg.c | 13 + .../deq/cn10k/deq_176_191_ca_tmo_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_176_191_dual.c | 12 + .../event/cnxk/deq/cn10k/deq_176_191_seg.c | 12 + .../cnxk/deq/cn10k/deq_176_191_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_176_191_tmo.c | 12 + .../cnxk/deq/cn10k/deq_176_191_tmo_burst.c | 14 + .../cnxk/deq/cn10k/deq_176_191_tmo_seg.c | 12 + .../deq/cn10k/deq_176_191_tmo_seg_burst.c | 14 + drivers/event/cnxk/deq/cn10k/deq_192_207.c | 12 + .../event/cnxk/deq/cn10k/deq_192_207_burst.c | 14 + drivers/event/cnxk/deq/cn10k/deq_192_207_ca.c | 12 + .../cnxk/deq/cn10k/deq_192_207_ca_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_192_207_ca_seg.c | 12 + .../cnxk/deq/cn10k/deq_192_207_ca_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_192_207_ca_tmo.c | 12 + .../cnxk/deq/cn10k/deq_192_207_ca_tmo_burst.c | 14 + .../cnxk/deq/cn10k/deq_192_207_ca_tmo_seg.c | 13 + .../deq/cn10k/deq_192_207_ca_tmo_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_192_207_dual.c | 12 + .../event/cnxk/deq/cn10k/deq_192_207_seg.c | 12 + .../cnxk/deq/cn10k/deq_192_207_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_192_207_tmo.c | 12 + .../cnxk/deq/cn10k/deq_192_207_tmo_burst.c | 14 + .../cnxk/deq/cn10k/deq_192_207_tmo_seg.c | 12 + .../deq/cn10k/deq_192_207_tmo_seg_burst.c | 14 + drivers/event/cnxk/deq/cn10k/deq_208_223.c | 12 + .../event/cnxk/deq/cn10k/deq_208_223_burst.c | 14 + drivers/event/cnxk/deq/cn10k/deq_208_223_ca.c | 12 + .../cnxk/deq/cn10k/deq_208_223_ca_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_208_223_ca_seg.c | 12 + .../cnxk/deq/cn10k/deq_208_223_ca_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_208_223_ca_tmo.c | 12 + .../cnxk/deq/cn10k/deq_208_223_ca_tmo_burst.c | 14 + .../cnxk/deq/cn10k/deq_208_223_ca_tmo_seg.c | 13 + .../deq/cn10k/deq_208_223_ca_tmo_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_208_223_dual.c | 12 + .../event/cnxk/deq/cn10k/deq_208_223_seg.c | 12 + .../cnxk/deq/cn10k/deq_208_223_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_208_223_tmo.c | 12 + .../cnxk/deq/cn10k/deq_208_223_tmo_burst.c | 14 + .../cnxk/deq/cn10k/deq_208_223_tmo_seg.c | 12 + .../deq/cn10k/deq_208_223_tmo_seg_burst.c | 14 + drivers/event/cnxk/deq/cn10k/deq_224_239.c | 12 + .../event/cnxk/deq/cn10k/deq_224_239_burst.c | 14 + drivers/event/cnxk/deq/cn10k/deq_224_239_ca.c | 12 + .../cnxk/deq/cn10k/deq_224_239_ca_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_224_239_ca_seg.c | 12 + .../cnxk/deq/cn10k/deq_224_239_ca_seg_burst.c | 14 + .../event/cnxk/deq/cn10k/deq_224_239_ca_tmo.c | 12 + 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drivers/event/cnxk/deq/cn10k/deq_240_255_tmo_burst.c create mode 100644 drivers/event/cnxk/deq/cn10k/deq_240_255_tmo_seg.c create mode 100644 drivers/event/cnxk/deq/cn10k/deq_240_255_tmo_seg_burst.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_128_143.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_128_143_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_128_143_vec.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_128_143_vec_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_144_159.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_144_159_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_144_159_vec.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_144_159_vec_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_160_175.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_160_175_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_160_175_vec.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_160_175_vec_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_176_191.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_176_191_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_176_191_vec.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_176_191_vec_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_192_207.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_192_207_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_192_207_vec.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_192_207_vec_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_208_223.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_208_223_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_208_223_vec.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_208_223_vec_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_224_239.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_224_239_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_224_239_vec.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_224_239_vec_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_240_255.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_240_255_mseg.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_240_255_vec.c create mode 100644 drivers/net/cnxk/rx/cn10k/rx_240_255_vec_mseg.c diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index b56426960a..fa5fa518c5 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -330,7 +330,6 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev) const event_dequeue_t sso_hws_deq_seg[NIX_RX_OFFLOAD_MAX] = { #define R(name, flags) [flags] = cn10k_sso_hws_deq_seg_##name, - NIX_RX_FASTPATH_MODES #undef R }; diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index 78d029baaa..0d6d58faf0 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -157,9 +157,11 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, /* Translate meta to mbuf */ if (flags & NIX_RX_OFFLOAD_SECURITY_F) { const uint64_t cq_w1 = *((const uint64_t *)cqe + 1); + const uint64_t cq_w5 = *((const uint64_t *)cqe + 5); - mbuf = nix_sec_meta_to_mbuf_sc(cq_w1, sa_base, laddr, - &loff, mbuf, d_off); + mbuf = nix_sec_meta_to_mbuf_sc(cq_w1, cq_w5, sa_base, laddr, + &loff, mbuf, d_off, + flags, mbuf_init); } cn10k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem, @@ -225,26 +227,32 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev, uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]); if (flags & NIX_RX_OFFLOAD_SECURITY_F) { + const uint64_t mbuf_init = 0x100010000ULL | + RTE_PKTMBUF_HEADROOM | + (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0); struct rte_mbuf *m; uintptr_t sa_base; uint64_t iova = 0; uint8_t loff = 0; uint16_t d_off; uint64_t cq_w1; + uint64_t cq_w5; m = (struct rte_mbuf *)mbuf; d_off = (uintptr_t)(m->buf_addr) - (uintptr_t)m; d_off += RTE_PKTMBUF_HEADROOM; cq_w1 = *(uint64_t *)(gw.u64[1] + 8); + cq_w5 = *(uint64_t *)(gw.u64[1] + 40); sa_base = cnxk_nix_sa_base_get(port, lookup_mem); sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1); mbuf = (uint64_t)nix_sec_meta_to_mbuf_sc( - cq_w1, sa_base, (uintptr_t)&iova, &loff, - (struct rte_mbuf *)mbuf, d_off); + cq_w1, cq_w5, sa_base, (uintptr_t)&iova, &loff, + (struct rte_mbuf *)mbuf, d_off, flags, + mbuf_init | ((uint64_t)port) << 48); if (loff) roc_npa_aura_op_free(m->pool->pool_id, 0, iova); diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143.c b/drivers/event/cnxk/deq/cn10k/deq_128_143.c new file mode 100644 index 0000000000..b3bc4f195d --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ(cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_burst.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_burst.c new file mode 100644 index 0000000000..ebc1e20eec --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_burst_##name, \ + cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_ca.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca.c new file mode 100644 index 0000000000..f13499f490 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA(cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_burst.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_burst.c new file mode 100644 index 0000000000..a0fad1ad9b --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_burst_##name, \ + cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_seg.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_seg.c new file mode 100644 index 0000000000..4cec0c7db5 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA_SEG(cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_seg_burst.c new file mode 100644 index 0000000000..728a48cd75 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_tmo.c new file mode 100644 index 0000000000..cc98821998 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_CA(cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_tmo_burst.c new file mode 100644 index 0000000000..3d03c71ea2 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_tmo_seg.c new file mode 100644 index 0000000000..e2788d2d82 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_tmo_seg.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_DEQ_TMO_CA_SEG(cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_tmo_seg_burst.c new file mode 100644 index 0000000000..3c11c33879 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_ca_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_dual.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_dual.c new file mode 100644 index 0000000000..f495bbb02c --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_dual.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DUAL_DEQ(cn10k_sso_hws_dual_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_seg.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_seg.c new file mode 100644 index 0000000000..9e8226c7af --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_SEG(cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_seg_burst.c new file mode 100644 index 0000000000..c150a758c4 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_SEG_BURST(cn10k_sso_hws_deq_seg_burst_##name, \ + cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_tmo.c new file mode 100644 index 0000000000..611bd35f84 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO(cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_tmo_burst.c new file mode 100644 index 0000000000..7c91e0c842 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_burst_##name, \ + cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_tmo_seg.c new file mode 100644 index 0000000000..7f2d789efc --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_tmo_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_SEG(cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_128_143_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_128_143_tmo_seg_burst.c new file mode 100644 index 0000000000..994fbc17a7 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_128_143_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159.c b/drivers/event/cnxk/deq/cn10k/deq_144_159.c new file mode 100644 index 0000000000..483fa7c372 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ(cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_burst.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_burst.c new file mode 100644 index 0000000000..e9c2eae8fa --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_burst_##name, \ + cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_ca.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca.c new file mode 100644 index 0000000000..eaae80b696 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA(cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_burst.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_burst.c new file mode 100644 index 0000000000..203a8cbb92 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_burst_##name, \ + cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_seg.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_seg.c new file mode 100644 index 0000000000..b341368d85 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA_SEG(cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_seg_burst.c new file mode 100644 index 0000000000..251b13199b --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_tmo.c new file mode 100644 index 0000000000..16fde955cd --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_CA(cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_tmo_burst.c new file mode 100644 index 0000000000..f7615615c9 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_tmo_seg.c new file mode 100644 index 0000000000..d191b1f44f --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_tmo_seg.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_DEQ_TMO_CA_SEG(cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_tmo_seg_burst.c new file mode 100644 index 0000000000..802e0dbb74 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_ca_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_dual.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_dual.c new file mode 100644 index 0000000000..81e6e57717 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_dual.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DUAL_DEQ(cn10k_sso_hws_dual_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_seg.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_seg.c new file mode 100644 index 0000000000..fbeef19451 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_SEG(cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_seg_burst.c new file mode 100644 index 0000000000..450ccd018c --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_SEG_BURST(cn10k_sso_hws_deq_seg_burst_##name, \ + cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_tmo.c new file mode 100644 index 0000000000..ecd8a62195 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO(cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_tmo_burst.c new file mode 100644 index 0000000000..52de6b545e --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_burst_##name, \ + cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_tmo_seg.c new file mode 100644 index 0000000000..e1ce1e00bf --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_tmo_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_SEG(cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_144_159_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_144_159_tmo_seg_burst.c new file mode 100644 index 0000000000..22ec66cf7f --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_144_159_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175.c b/drivers/event/cnxk/deq/cn10k/deq_160_175.c new file mode 100644 index 0000000000..225d234ebe --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ(cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_burst.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_burst.c new file mode 100644 index 0000000000..c8ef1a144e --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_burst_##name, \ + cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_ca.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca.c new file mode 100644 index 0000000000..b304de6e5c --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA(cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_burst.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_burst.c new file mode 100644 index 0000000000..ef8442af7d --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_burst_##name, \ + cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_seg.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_seg.c new file mode 100644 index 0000000000..272d9a6126 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA_SEG(cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_seg_burst.c new file mode 100644 index 0000000000..452476e478 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_tmo.c new file mode 100644 index 0000000000..e481565fc9 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_CA(cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_tmo_burst.c new file mode 100644 index 0000000000..4bc5e54487 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_tmo_seg.c new file mode 100644 index 0000000000..cb63891568 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_tmo_seg.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_DEQ_TMO_CA_SEG(cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_tmo_seg_burst.c new file mode 100644 index 0000000000..effca85b06 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_ca_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_dual.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_dual.c new file mode 100644 index 0000000000..f8de8810bd --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_dual.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DUAL_DEQ(cn10k_sso_hws_dual_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_seg.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_seg.c new file mode 100644 index 0000000000..3afd3a4117 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_SEG(cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_seg_burst.c new file mode 100644 index 0000000000..a60e59df8e --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_SEG_BURST(cn10k_sso_hws_deq_seg_burst_##name, \ + cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_tmo.c new file mode 100644 index 0000000000..91179a1eca --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO(cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_tmo_burst.c new file mode 100644 index 0000000000..9a62c88942 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_burst_##name, \ + cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_tmo_seg.c new file mode 100644 index 0000000000..30218295b9 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_tmo_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_SEG(cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_160_175_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_160_175_tmo_seg_burst.c new file mode 100644 index 0000000000..7cb9f955a5 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_160_175_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191.c b/drivers/event/cnxk/deq/cn10k/deq_176_191.c new file mode 100644 index 0000000000..8e686199f4 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ(cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_burst.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_burst.c new file mode 100644 index 0000000000..a5494ddb72 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_burst_##name, \ + cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_ca.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca.c new file mode 100644 index 0000000000..6ef5e6c281 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA(cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_burst.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_burst.c new file mode 100644 index 0000000000..faebf51a51 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_burst_##name, \ + cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_seg.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_seg.c new file mode 100644 index 0000000000..0cc6ea32ee --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA_SEG(cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_seg_burst.c new file mode 100644 index 0000000000..2bcd802e6a --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_tmo.c new file mode 100644 index 0000000000..63cbe16bff --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_CA(cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_tmo_burst.c new file mode 100644 index 0000000000..49400d80af --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_tmo_seg.c new file mode 100644 index 0000000000..505864a280 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_tmo_seg.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_DEQ_TMO_CA_SEG(cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_tmo_seg_burst.c new file mode 100644 index 0000000000..561f907815 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_ca_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_dual.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_dual.c new file mode 100644 index 0000000000..539b19dacb --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_dual.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DUAL_DEQ(cn10k_sso_hws_dual_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_seg.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_seg.c new file mode 100644 index 0000000000..b0d134d4df --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_SEG(cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_seg_burst.c new file mode 100644 index 0000000000..1e346a0772 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_SEG_BURST(cn10k_sso_hws_deq_seg_burst_##name, \ + cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_tmo.c new file mode 100644 index 0000000000..38d1fbbefe --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO(cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_tmo_burst.c new file mode 100644 index 0000000000..b53bc86377 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_burst_##name, \ + cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_tmo_seg.c new file mode 100644 index 0000000000..5f2eaaad46 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_tmo_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_SEG(cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_176_191_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_176_191_tmo_seg_burst.c new file mode 100644 index 0000000000..5eb9e2bf0e --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_176_191_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207.c b/drivers/event/cnxk/deq/cn10k/deq_192_207.c new file mode 100644 index 0000000000..6f53dbce2a --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ(cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_burst.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_burst.c new file mode 100644 index 0000000000..f9789efbb2 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_burst_##name, \ + cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_ca.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca.c new file mode 100644 index 0000000000..56ed0cae38 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA(cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_burst.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_burst.c new file mode 100644 index 0000000000..70ed05e6e9 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_burst_##name, \ + cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_seg.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_seg.c new file mode 100644 index 0000000000..806b9e4ef0 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA_SEG(cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_seg_burst.c new file mode 100644 index 0000000000..93360814e1 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_tmo.c new file mode 100644 index 0000000000..43c735d123 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_CA(cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_tmo_burst.c new file mode 100644 index 0000000000..5f7da5500d --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_tmo_seg.c new file mode 100644 index 0000000000..4c6126f13a --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_tmo_seg.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_DEQ_TMO_CA_SEG(cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_tmo_seg_burst.c new file mode 100644 index 0000000000..81ae021b51 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_ca_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_dual.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_dual.c new file mode 100644 index 0000000000..2adcdaf59c --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_dual.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DUAL_DEQ(cn10k_sso_hws_dual_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_seg.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_seg.c new file mode 100644 index 0000000000..5d59f7fe23 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_SEG(cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_seg_burst.c new file mode 100644 index 0000000000..ddebe2aa40 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_SEG_BURST(cn10k_sso_hws_deq_seg_burst_##name, \ + cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_tmo.c new file mode 100644 index 0000000000..e1c5beb41d --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO(cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_tmo_burst.c new file mode 100644 index 0000000000..5d733766ee --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_burst_##name, \ + cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_tmo_seg.c new file mode 100644 index 0000000000..12bff5902c --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_tmo_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_SEG(cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_192_207_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_192_207_tmo_seg_burst.c new file mode 100644 index 0000000000..2d10cc6e68 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_192_207_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223.c b/drivers/event/cnxk/deq/cn10k/deq_208_223.c new file mode 100644 index 0000000000..965a9405f0 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ(cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_burst.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_burst.c new file mode 100644 index 0000000000..de9a048a0e --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_burst_##name, \ + cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_ca.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca.c new file mode 100644 index 0000000000..f9148acef3 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA(cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_burst.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_burst.c new file mode 100644 index 0000000000..12a927a872 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_burst_##name, \ + cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_seg.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_seg.c new file mode 100644 index 0000000000..1b020fbf98 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA_SEG(cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_seg_burst.c new file mode 100644 index 0000000000..2c826f2284 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_tmo.c new file mode 100644 index 0000000000..48c23b910d --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_CA(cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_tmo_burst.c new file mode 100644 index 0000000000..5381f1ce17 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_tmo_seg.c new file mode 100644 index 0000000000..116d9efc2d --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_tmo_seg.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_DEQ_TMO_CA_SEG(cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_tmo_seg_burst.c new file mode 100644 index 0000000000..86571c7027 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_ca_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_dual.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_dual.c new file mode 100644 index 0000000000..0fb35b9c83 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_dual.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DUAL_DEQ(cn10k_sso_hws_dual_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_seg.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_seg.c new file mode 100644 index 0000000000..df48426ff1 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_SEG(cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_seg_burst.c new file mode 100644 index 0000000000..f1342e3232 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_SEG_BURST(cn10k_sso_hws_deq_seg_burst_##name, \ + cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_tmo.c new file mode 100644 index 0000000000..6f2d909806 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO(cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_tmo_burst.c new file mode 100644 index 0000000000..3c6f226c4b --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_burst_##name, \ + cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_tmo_seg.c new file mode 100644 index 0000000000..44a794233f --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_tmo_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_SEG(cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_208_223_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_208_223_tmo_seg_burst.c new file mode 100644 index 0000000000..aa89930d3e --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_208_223_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239.c b/drivers/event/cnxk/deq/cn10k/deq_224_239.c new file mode 100644 index 0000000000..03f5bd3588 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ(cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_burst.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_burst.c new file mode 100644 index 0000000000..091419eb9b --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_burst_##name, \ + cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_ca.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca.c new file mode 100644 index 0000000000..8f4693e057 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA(cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_burst.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_burst.c new file mode 100644 index 0000000000..474c9b1eee --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_burst_##name, \ + cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_seg.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_seg.c new file mode 100644 index 0000000000..478df24934 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA_SEG(cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_seg_burst.c new file mode 100644 index 0000000000..3b78a0f91e --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_tmo.c new file mode 100644 index 0000000000..366ae27814 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_CA(cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_tmo_burst.c new file mode 100644 index 0000000000..db0751fece --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_tmo_seg.c new file mode 100644 index 0000000000..6dc3d2f870 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_tmo_seg.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_DEQ_TMO_CA_SEG(cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_tmo_seg_burst.c new file mode 100644 index 0000000000..11b1784868 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_ca_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_dual.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_dual.c new file mode 100644 index 0000000000..35429014da --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_dual.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DUAL_DEQ(cn10k_sso_hws_dual_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_seg.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_seg.c new file mode 100644 index 0000000000..19b5d2eedd --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_SEG(cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_seg_burst.c new file mode 100644 index 0000000000..fe8f8099b0 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_SEG_BURST(cn10k_sso_hws_deq_seg_burst_##name, \ + cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_tmo.c new file mode 100644 index 0000000000..4f196ddaaf --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO(cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_tmo_burst.c new file mode 100644 index 0000000000..252cf4f44d --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_burst_##name, \ + cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_tmo_seg.c new file mode 100644 index 0000000000..675149ec3a --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_tmo_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_SEG(cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_224_239_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_224_239_tmo_seg_burst.c new file mode 100644 index 0000000000..9347485e05 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_224_239_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255.c b/drivers/event/cnxk/deq/cn10k/deq_240_255.c new file mode 100644 index 0000000000..7890137548 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ(cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_burst.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_burst.c new file mode 100644 index 0000000000..b1241915c8 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_burst_##name, \ + cn10k_sso_hws_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_ca.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca.c new file mode 100644 index 0000000000..1f9abae4bc --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA(cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_burst.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_burst.c new file mode 100644 index 0000000000..a518f5e285 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_burst_##name, \ + cn10k_sso_hws_deq_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_seg.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_seg.c new file mode 100644 index 0000000000..f6408fbdd3 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_CA_SEG(cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_seg_burst.c new file mode 100644 index 0000000000..76bfa4ac08 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_tmo.c new file mode 100644 index 0000000000..f28b909b66 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_CA(cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_tmo_burst.c new file mode 100644 index 0000000000..5c76f78dca --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_tmo_seg.c new file mode 100644 index 0000000000..35af75874b --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_tmo_seg.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_DEQ_TMO_CA_SEG(cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_tmo_seg_burst.c new file mode 100644 index 0000000000..f8c6deb8ef --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_ca_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_ca_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_ca_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_dual.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_dual.c new file mode 100644 index 0000000000..0b227c2f99 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_dual.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DUAL_DEQ(cn10k_sso_hws_dual_deq_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_seg.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_seg.c new file mode 100644 index 0000000000..6af63491da --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_SEG(cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_seg_burst.c new file mode 100644 index 0000000000..6b20efd787 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_SEG_BURST(cn10k_sso_hws_deq_seg_burst_##name, \ + cn10k_sso_hws_deq_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_tmo.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_tmo.c new file mode 100644 index 0000000000..c074e55d02 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_tmo.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO(cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_tmo_burst.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_tmo_burst.c new file mode 100644 index 0000000000..88bf1541cb --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_tmo_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_burst_##name, \ + cn10k_sso_hws_deq_tmo_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_tmo_seg.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_tmo_seg.c new file mode 100644 index 0000000000..560fc74f64 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_tmo_seg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) SSO_DEQ_TMO_SEG(cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/deq/cn10k/deq_240_255_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_240_255_tmo_seg_burst.c new file mode 100644 index 0000000000..92017de4e2 --- /dev/null +++ b/drivers/event/cnxk/deq/cn10k/deq_240_255_tmo_seg_burst.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_seg_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build index b27bae7b12..26081faf0c 100644 --- a/drivers/event/cnxk/meson.build +++ b/drivers/event/cnxk/meson.build @@ -330,6 +330,14 @@ sources += files( 'deq/cn10k/deq_80_95_burst.c', 'deq/cn10k/deq_96_111_burst.c', 'deq/cn10k/deq_112_127_burst.c', + 'deq/cn10k/deq_128_143_burst.c', + 'deq/cn10k/deq_144_159_burst.c', + 'deq/cn10k/deq_160_175_burst.c', + 'deq/cn10k/deq_176_191_burst.c', + 'deq/cn10k/deq_192_207_burst.c', + 'deq/cn10k/deq_208_223_burst.c', + 'deq/cn10k/deq_224_239_burst.c', + 'deq/cn10k/deq_240_255_burst.c', 'deq/cn10k/deq_0_15_seg_burst.c', 'deq/cn10k/deq_16_31_seg_burst.c', 'deq/cn10k/deq_32_47_seg_burst.c', @@ -338,6 +346,14 @@ sources += files( 'deq/cn10k/deq_80_95_seg_burst.c', 'deq/cn10k/deq_96_111_seg_burst.c', 'deq/cn10k/deq_112_127_seg_burst.c', + 'deq/cn10k/deq_128_143_seg_burst.c', + 'deq/cn10k/deq_144_159_seg_burst.c', + 'deq/cn10k/deq_160_175_seg_burst.c', + 'deq/cn10k/deq_176_191_seg_burst.c', + 'deq/cn10k/deq_192_207_seg_burst.c', + 'deq/cn10k/deq_208_223_seg_burst.c', + 'deq/cn10k/deq_224_239_seg_burst.c', + 'deq/cn10k/deq_240_255_seg_burst.c', 'deq/cn10k/deq_0_15.c', 'deq/cn10k/deq_16_31.c', 'deq/cn10k/deq_32_47.c', @@ -346,6 +362,14 @@ sources += files( 'deq/cn10k/deq_80_95.c', 'deq/cn10k/deq_96_111.c', 'deq/cn10k/deq_112_127.c', + 'deq/cn10k/deq_128_143.c', + 'deq/cn10k/deq_144_159.c', + 'deq/cn10k/deq_160_175.c', + 'deq/cn10k/deq_176_191.c', + 'deq/cn10k/deq_192_207.c', + 'deq/cn10k/deq_208_223.c', + 'deq/cn10k/deq_224_239.c', + 'deq/cn10k/deq_240_255.c', 'deq/cn10k/deq_0_15_seg.c', 'deq/cn10k/deq_16_31_seg.c', 'deq/cn10k/deq_32_47_seg.c', @@ -354,6 +378,14 @@ sources += files( 'deq/cn10k/deq_80_95_seg.c', 'deq/cn10k/deq_96_111_seg.c', 'deq/cn10k/deq_112_127_seg.c', + 'deq/cn10k/deq_128_143_seg.c', + 'deq/cn10k/deq_144_159_seg.c', + 'deq/cn10k/deq_160_175_seg.c', + 'deq/cn10k/deq_176_191_seg.c', + 'deq/cn10k/deq_192_207_seg.c', + 'deq/cn10k/deq_208_223_seg.c', + 'deq/cn10k/deq_224_239_seg.c', + 'deq/cn10k/deq_240_255_seg.c', 'deq/cn10k/deq_0_15_tmo.c', 'deq/cn10k/deq_16_31_tmo.c', 'deq/cn10k/deq_32_47_tmo.c', @@ -362,6 +394,14 @@ sources += files( 'deq/cn10k/deq_80_95_tmo.c', 'deq/cn10k/deq_96_111_tmo.c', 'deq/cn10k/deq_112_127_tmo.c', + 'deq/cn10k/deq_128_143_tmo.c', + 'deq/cn10k/deq_144_159_tmo.c', + 'deq/cn10k/deq_160_175_tmo.c', + 'deq/cn10k/deq_176_191_tmo.c', + 'deq/cn10k/deq_192_207_tmo.c', + 'deq/cn10k/deq_208_223_tmo.c', + 'deq/cn10k/deq_224_239_tmo.c', + 'deq/cn10k/deq_240_255_tmo.c', 'deq/cn10k/deq_0_15_tmo_burst.c', 'deq/cn10k/deq_16_31_tmo_burst.c', 'deq/cn10k/deq_32_47_tmo_burst.c', @@ -370,6 +410,14 @@ sources += files( 'deq/cn10k/deq_80_95_tmo_burst.c', 'deq/cn10k/deq_96_111_tmo_burst.c', 'deq/cn10k/deq_112_127_tmo_burst.c', + 'deq/cn10k/deq_128_143_tmo_burst.c', + 'deq/cn10k/deq_144_159_tmo_burst.c', + 'deq/cn10k/deq_160_175_tmo_burst.c', + 'deq/cn10k/deq_176_191_tmo_burst.c', + 'deq/cn10k/deq_192_207_tmo_burst.c', + 'deq/cn10k/deq_208_223_tmo_burst.c', + 'deq/cn10k/deq_224_239_tmo_burst.c', + 'deq/cn10k/deq_240_255_tmo_burst.c', 'deq/cn10k/deq_0_15_tmo_seg.c', 'deq/cn10k/deq_16_31_tmo_seg.c', 'deq/cn10k/deq_32_47_tmo_seg.c', @@ -378,6 +426,14 @@ sources += files( 'deq/cn10k/deq_80_95_tmo_seg.c', 'deq/cn10k/deq_96_111_tmo_seg.c', 'deq/cn10k/deq_112_127_tmo_seg.c', + 'deq/cn10k/deq_128_143_tmo_seg.c', + 'deq/cn10k/deq_144_159_tmo_seg.c', + 'deq/cn10k/deq_160_175_tmo_seg.c', + 'deq/cn10k/deq_176_191_tmo_seg.c', + 'deq/cn10k/deq_192_207_tmo_seg.c', + 'deq/cn10k/deq_208_223_tmo_seg.c', + 'deq/cn10k/deq_224_239_tmo_seg.c', + 'deq/cn10k/deq_240_255_tmo_seg.c', 'deq/cn10k/deq_0_15_tmo_seg_burst.c', 'deq/cn10k/deq_16_31_tmo_seg_burst.c', 'deq/cn10k/deq_32_47_tmo_seg_burst.c', @@ -386,6 +442,14 @@ sources += files( 'deq/cn10k/deq_80_95_tmo_seg_burst.c', 'deq/cn10k/deq_96_111_tmo_seg_burst.c', 'deq/cn10k/deq_112_127_tmo_seg_burst.c', + 'deq/cn10k/deq_128_143_tmo_seg_burst.c', + 'deq/cn10k/deq_144_159_tmo_seg_burst.c', + 'deq/cn10k/deq_160_175_tmo_seg_burst.c', + 'deq/cn10k/deq_176_191_tmo_seg_burst.c', + 'deq/cn10k/deq_192_207_tmo_seg_burst.c', + 'deq/cn10k/deq_208_223_tmo_seg_burst.c', + 'deq/cn10k/deq_224_239_tmo_seg_burst.c', + 'deq/cn10k/deq_240_255_tmo_seg_burst.c', 'deq/cn10k/deq_0_15_ca.c', 'deq/cn10k/deq_16_31_ca.c', 'deq/cn10k/deq_32_47_ca.c', @@ -394,6 +458,14 @@ sources += files( 'deq/cn10k/deq_80_95_ca.c', 'deq/cn10k/deq_96_111_ca.c', 'deq/cn10k/deq_112_127_ca.c', + 'deq/cn10k/deq_128_143_ca.c', + 'deq/cn10k/deq_144_159_ca.c', + 'deq/cn10k/deq_160_175_ca.c', + 'deq/cn10k/deq_176_191_ca.c', + 'deq/cn10k/deq_192_207_ca.c', + 'deq/cn10k/deq_208_223_ca.c', + 'deq/cn10k/deq_224_239_ca.c', + 'deq/cn10k/deq_240_255_ca.c', 'deq/cn10k/deq_0_15_ca_burst.c', 'deq/cn10k/deq_16_31_ca_burst.c', 'deq/cn10k/deq_32_47_ca_burst.c', @@ -402,6 +474,14 @@ sources += files( 'deq/cn10k/deq_80_95_ca_burst.c', 'deq/cn10k/deq_96_111_ca_burst.c', 'deq/cn10k/deq_112_127_ca_burst.c', + 'deq/cn10k/deq_128_143_ca_burst.c', + 'deq/cn10k/deq_144_159_ca_burst.c', + 'deq/cn10k/deq_160_175_ca_burst.c', + 'deq/cn10k/deq_176_191_ca_burst.c', + 'deq/cn10k/deq_192_207_ca_burst.c', + 'deq/cn10k/deq_208_223_ca_burst.c', + 'deq/cn10k/deq_224_239_ca_burst.c', + 'deq/cn10k/deq_240_255_ca_burst.c', 'deq/cn10k/deq_0_15_ca_seg.c', 'deq/cn10k/deq_16_31_ca_seg.c', 'deq/cn10k/deq_32_47_ca_seg.c', @@ -410,6 +490,14 @@ sources += files( 'deq/cn10k/deq_80_95_ca_seg.c', 'deq/cn10k/deq_96_111_ca_seg.c', 'deq/cn10k/deq_112_127_ca_seg.c', + 'deq/cn10k/deq_128_143_ca_seg.c', + 'deq/cn10k/deq_144_159_ca_seg.c', + 'deq/cn10k/deq_160_175_ca_seg.c', + 'deq/cn10k/deq_176_191_ca_seg.c', + 'deq/cn10k/deq_192_207_ca_seg.c', + 'deq/cn10k/deq_208_223_ca_seg.c', + 'deq/cn10k/deq_224_239_ca_seg.c', + 'deq/cn10k/deq_240_255_ca_seg.c', 'deq/cn10k/deq_0_15_ca_seg_burst.c', 'deq/cn10k/deq_16_31_ca_seg_burst.c', 'deq/cn10k/deq_32_47_ca_seg_burst.c', @@ -418,6 +506,14 @@ sources += files( 'deq/cn10k/deq_80_95_ca_seg_burst.c', 'deq/cn10k/deq_96_111_ca_seg_burst.c', 'deq/cn10k/deq_112_127_ca_seg_burst.c', + 'deq/cn10k/deq_128_143_ca_seg_burst.c', + 'deq/cn10k/deq_144_159_ca_seg_burst.c', + 'deq/cn10k/deq_160_175_ca_seg_burst.c', + 'deq/cn10k/deq_176_191_ca_seg_burst.c', + 'deq/cn10k/deq_192_207_ca_seg_burst.c', + 'deq/cn10k/deq_208_223_ca_seg_burst.c', + 'deq/cn10k/deq_224_239_ca_seg_burst.c', + 'deq/cn10k/deq_240_255_ca_seg_burst.c', 'deq/cn10k/deq_0_15_ca_tmo.c', 'deq/cn10k/deq_16_31_ca_tmo.c', 'deq/cn10k/deq_32_47_ca_tmo.c', @@ -426,6 +522,14 @@ sources += files( 'deq/cn10k/deq_80_95_ca_tmo.c', 'deq/cn10k/deq_96_111_ca_tmo.c', 'deq/cn10k/deq_112_127_ca_tmo.c', + 'deq/cn10k/deq_128_143_ca_tmo.c', + 'deq/cn10k/deq_144_159_ca_tmo.c', + 'deq/cn10k/deq_160_175_ca_tmo.c', + 'deq/cn10k/deq_176_191_ca_tmo.c', + 'deq/cn10k/deq_192_207_ca_tmo.c', + 'deq/cn10k/deq_208_223_ca_tmo.c', + 'deq/cn10k/deq_224_239_ca_tmo.c', + 'deq/cn10k/deq_240_255_ca_tmo.c', 'deq/cn10k/deq_0_15_ca_tmo_burst.c', 'deq/cn10k/deq_16_31_ca_tmo_burst.c', 'deq/cn10k/deq_32_47_ca_tmo_burst.c', @@ -434,6 +538,14 @@ sources += files( 'deq/cn10k/deq_80_95_ca_tmo_burst.c', 'deq/cn10k/deq_96_111_ca_tmo_burst.c', 'deq/cn10k/deq_112_127_ca_tmo_burst.c', + 'deq/cn10k/deq_128_143_ca_tmo_burst.c', + 'deq/cn10k/deq_144_159_ca_tmo_burst.c', + 'deq/cn10k/deq_160_175_ca_tmo_burst.c', + 'deq/cn10k/deq_176_191_ca_tmo_burst.c', + 'deq/cn10k/deq_192_207_ca_tmo_burst.c', + 'deq/cn10k/deq_208_223_ca_tmo_burst.c', + 'deq/cn10k/deq_224_239_ca_tmo_burst.c', + 'deq/cn10k/deq_240_255_ca_tmo_burst.c', 'deq/cn10k/deq_0_15_ca_tmo_seg.c', 'deq/cn10k/deq_16_31_ca_tmo_seg.c', 'deq/cn10k/deq_32_47_ca_tmo_seg.c', @@ -442,6 +554,14 @@ sources += files( 'deq/cn10k/deq_80_95_ca_tmo_seg.c', 'deq/cn10k/deq_96_111_ca_tmo_seg.c', 'deq/cn10k/deq_112_127_ca_tmo_seg.c', + 'deq/cn10k/deq_128_143_ca_tmo_seg.c', + 'deq/cn10k/deq_144_159_ca_tmo_seg.c', + 'deq/cn10k/deq_160_175_ca_tmo_seg.c', + 'deq/cn10k/deq_176_191_ca_tmo_seg.c', + 'deq/cn10k/deq_192_207_ca_tmo_seg.c', + 'deq/cn10k/deq_208_223_ca_tmo_seg.c', + 'deq/cn10k/deq_224_239_ca_tmo_seg.c', + 'deq/cn10k/deq_240_255_ca_tmo_seg.c', 'deq/cn10k/deq_0_15_ca_tmo_seg_burst.c', 'deq/cn10k/deq_16_31_ca_tmo_seg_burst.c', 'deq/cn10k/deq_32_47_ca_tmo_seg_burst.c', @@ -450,6 +570,14 @@ sources += files( 'deq/cn10k/deq_80_95_ca_tmo_seg_burst.c', 'deq/cn10k/deq_96_111_ca_tmo_seg_burst.c', 'deq/cn10k/deq_112_127_ca_tmo_seg_burst.c', + 'deq/cn10k/deq_128_143_ca_tmo_seg_burst.c', + 'deq/cn10k/deq_144_159_ca_tmo_seg_burst.c', + 'deq/cn10k/deq_160_175_ca_tmo_seg_burst.c', + 'deq/cn10k/deq_176_191_ca_tmo_seg_burst.c', + 'deq/cn10k/deq_192_207_ca_tmo_seg_burst.c', + 'deq/cn10k/deq_208_223_ca_tmo_seg_burst.c', + 'deq/cn10k/deq_224_239_ca_tmo_seg_burst.c', + 'deq/cn10k/deq_240_255_ca_tmo_seg_burst.c', ) sources += files( diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index 8378cbffc2..9e30dfe4d0 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -39,6 +39,10 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev) if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) flags |= NIX_RX_OFFLOAD_SECURITY_F; + if (dev->rx_offloads & + (DEV_RX_OFFLOAD_SECURITY | RTE_ETH_RX_OFFLOAD_IP_REASSEMBLY)) + flags |= NIX_RX_OFFLOAD_REASSEMBLY_F; + return flags; } @@ -317,6 +321,10 @@ cn10k_nix_configure(struct rte_eth_dev *eth_dev) dev->rx_offload_flags = nix_rx_offload_flags(eth_dev); dev->tx_offload_flags = nix_tx_offload_flags(eth_dev); + /* reset reassembly dynfield/flag offset */ + dev->reass_dynfield_off = -1; + dev->reass_dynflag_bit = -1; + plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x" " tx_offload_flags=0x%x", eth_dev->data->port_id, dev->rx_offload_flags, @@ -470,6 +478,17 @@ cn10k_nix_dev_start(struct rte_eth_dev *eth_dev) return 0; } +static int +cn10k_nix_reass_conf_set(struct rte_eth_dev *dev, + struct rte_eth_ip_reass_params *conf) +{ + RTE_SET_USED(dev); + int rc = 0; + + rc = roc_nix_reass_configure(conf->reass_timeout, conf->max_frags); + return rc; +} + /* Update platform specific eth dev ops */ static void nix_eth_dev_ops_override(void) @@ -489,6 +508,7 @@ nix_eth_dev_ops_override(void) cnxk_eth_dev_ops.dev_ptypes_set = cn10k_nix_ptypes_set; cnxk_eth_dev_ops.timesync_enable = cn10k_nix_timesync_enable; cnxk_eth_dev_ops.timesync_disable = cn10k_nix_timesync_disable; + cnxk_eth_dev_ops.ip_reassembly_conf_set = cn10k_nix_reass_conf_set; } static void diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h index 0982158c62..3836c26afa 100644 --- a/drivers/net/cnxk/cn10k_ethdev.h +++ b/drivers/net/cnxk/cn10k_ethdev.h @@ -45,6 +45,8 @@ struct cn10k_eth_rxq { /* Private data in sw rsvd area of struct roc_ot_ipsec_inb_sa */ struct cn10k_inb_priv_data { void *userdata; + int reass_dynfield_off; + int reass_dynflag_bit; struct cnxk_eth_sec_sess *eth_sec; }; diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 235c16840e..c332d59012 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -249,6 +249,14 @@ cn10k_eth_sec_session_create(void *device, if (rte_security_dynfield_register() < 0) return -ENOTSUP; + if (conf->ipsec.options.reass_en && + dev->reass_dynfield_off < 0) { + if (rte_eth_ip_reass_dynfield_register( + &dev->reass_dynfield_off, + &dev->reass_dynflag_bit) < 0) + return -rte_errno; + } + if (rte_eal_process_type() == RTE_PROC_PRIMARY) roc_nix_inl_cb_register(cn10k_eth_sec_sso_work_cb, NULL); @@ -346,6 +354,12 @@ cn10k_eth_sec_session_create(void *device, sizeof(struct roc_ot_ipsec_inb_sa)); if (rc) goto mempool_put; + + if (conf->ipsec.options.reass_en) { + inb_priv->reass_dynfield_off = dev->reass_dynfield_off; + inb_priv->reass_dynflag_bit = dev->reass_dynflag_bit; + } + } else { struct roc_ot_ipsec_outb_sa *outb_sa, *outb_sa_dptr; struct cn10k_outb_priv_data *outb_priv; @@ -401,6 +415,8 @@ cn10k_eth_sec_session_create(void *device, TAILQ_INSERT_TAIL(&dev->outb.list, eth_sec, entry); dev->outb.nb_sess++; /* Sync session in context cache */ + dev->outb.nb_sess++; + /* Sync session in context cache */ rc = roc_nix_inl_ctx_write(&dev->nix, outb_sa_dptr, eth_sec->sa, eth_sec->inb, sizeof(struct roc_ot_ipsec_outb_sa)); diff --git a/drivers/net/cnxk/cn10k_rx.c b/drivers/net/cnxk/cn10k_rx.c index 5d603514c0..028abe8f39 100644 --- a/drivers/net/cnxk/cn10k_rx.c +++ b/drivers/net/cnxk/cn10k_rx.c @@ -5,7 +5,7 @@ #include "cn10k_ethdev.h" #include "cn10k_rx.h" -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ +#define R(name, f7, f6, f5, f4, f3, f2, f1, f0, flags) \ uint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_##name( \ void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \ { \ @@ -17,12 +17,13 @@ NIX_RX_FASTPATH_MODES static inline void pick_rx_func(struct rte_eth_dev *eth_dev, - const eth_rx_burst_t rx_burst[2][2][2][2][2][2][2]) + const eth_rx_burst_t rx_burst[2][2][2][2][2][2][2][2]) { struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); /* [VLAN] [TSP] [MARK] [CKSUM] [PTYPE] [RSS] */ eth_dev->rx_pkt_burst = rx_burst + [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_REASSEMBLY_F)] [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_SECURITY_F)] [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_VLAN_STRIP_F)] [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F)] @@ -39,42 +40,42 @@ cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev) { struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); - const eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_##name, + const eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2][2][2] = { +#define R(name, f7, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f7][f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_##name, NIX_RX_FASTPATH_MODES #undef R }; - const eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_mseg_##name, + const eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2][2][2][2][2] = { +#define R(name, f7, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f7][f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_mseg_##name, NIX_RX_FASTPATH_MODES #undef R }; - const eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_##name, + const eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2][2][2] = { +#define R(name, f7, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f7][f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_##name, NIX_RX_FASTPATH_MODES #undef R }; - const eth_rx_burst_t nix_eth_rx_vec_burst_mseg[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_mseg_##name, + const eth_rx_burst_t nix_eth_rx_vec_burst_mseg[2][2][2][2][2][2][2][2] = { +#define R(name, f7, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f7][f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_mseg_##name, - NIX_RX_FASTPATH_MODES + NIX_RX_FASTPATH_MODES #undef R - }; + }; /* Copy multi seg version with no offload for tear down sequence */ if (rte_eal_process_type() == RTE_PROC_PRIMARY) dev->rx_pkt_burst_no_offload = - nix_eth_rx_burst_mseg[0][0][0][0][0][0][0]; + nix_eth_rx_burst_mseg[0][0][0][0][0][0][0][0]; if (dev->scalar_ena) { if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index a2442d3726..eb94ae2360 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -17,7 +17,8 @@ #define NIX_RX_OFFLOAD_TSTAMP_F BIT(4) #define NIX_RX_OFFLOAD_VLAN_STRIP_F BIT(5) #define NIX_RX_OFFLOAD_SECURITY_F BIT(6) -#define NIX_RX_OFFLOAD_MAX (NIX_RX_OFFLOAD_SECURITY_F << 1) +#define NIX_RX_OFFLOAD_REASSEMBLY_F BIT(7) +#define NIX_RX_OFFLOAD_MAX (NIX_RX_OFFLOAD_REASSEMBLY_F << 1) /* Flags to control cqe_to_mbuf conversion function. * Defining it from backwards to denote its been @@ -37,6 +38,16 @@ (uint64_t *)(((uintptr_t)((uint64_t *)(b))[i]) + (o)) : \ (uint64_t *)(((uintptr_t)(b)) + CQE_SZ(i) + (o))) +#define NIX_RX_SEC_REASS_F \ + (NIX_RX_OFFLOAD_REASSEMBLY_F | NIX_RX_OFFLOAD_SECURITY_F) + +static inline rte_eth_ip_reass_dynfield_t * +cnxk_ip_reass_dynfield(struct rte_mbuf *mbuf, int ip_reass_dynfield_offset) +{ + return RTE_MBUF_DYNFIELD(mbuf, ip_reass_dynfield_offset, + rte_eth_ip_reass_dynfield_t *); +} + union mbuf_initializer { struct { uint16_t data_off; @@ -86,19 +97,348 @@ nix_sec_flush_meta(uintptr_t laddr, uint16_t lmt_id, uint8_t loff, roc_lmt_submit_steorl(lmt_id, pa); } +static struct rte_mbuf * +nix_sec_attach_frags(const struct cpt_parse_hdr_s *hdr, + struct cn10k_inb_priv_data *inb_priv, + const uint64_t mbuf_init) +{ + struct rte_mbuf *head, *mbuf, *mbuf_prev; + uint32_t offset = hdr->w2.fi_offset; + union nix_rx_parse_u *frag_rx; + struct cpt_frag_info_s *finfo; + uint64_t *frag_ptr, ol_flags; + uint16_t frag_size; + uint16_t rlen; + uint64_t *wqe; + int off; + + off = inb_priv->reass_dynfield_off; + ol_flags = BIT_ULL(inb_priv->reass_dynflag_bit); + ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD; + + /* offset of 0 implies 256B, otherwise it implies offset*8B */ + offset = (((offset - 1) & 0x1f) + 1) * 8; + finfo = RTE_PTR_ADD(hdr, offset + hdr->w2.fi_pad); + + /* Frag-0: */ + wqe = (uint64_t *)(rte_be_to_cpu_64(hdr->wqe_ptr)); + rlen = ((*(wqe + 10)) >> 16) & 0xFFFF; + + frag_rx = (union nix_rx_parse_u *)(wqe + 1); + frag_size = rlen + frag_rx->lcptr - frag_rx->laptr; + frag_rx->pkt_lenm1 = frag_size - 1; + + mbuf = (struct rte_mbuf *)((uintptr_t)wqe - sizeof(struct rte_mbuf)); + *(uint64_t *)(&mbuf->rearm_data) = mbuf_init; + mbuf->data_len = frag_size; + mbuf->pkt_len = frag_size; + mbuf->ol_flags = ol_flags; + mbuf->next = NULL; + head = mbuf; + mbuf_prev = mbuf; + /* Update dynamic field with userdata */ + *rte_security_dynfield(mbuf) = (uint64_t)inb_priv->userdata; + + cnxk_ip_reass_dynfield(head, off)->nb_frags = hdr->w0.num_frags - 1; + cnxk_ip_reass_dynfield(head, off)->next_frag = NULL; + + /* Frag-1: */ + if (hdr->w0.num_frags > 1) { + wqe = (uint64_t *)(rte_be_to_cpu_64(hdr->frag1_wqe_ptr)); + rlen = ((*(wqe + 10)) >> 16) & 0xFFFF; + + frag_rx = (union nix_rx_parse_u *)(wqe + 1); + frag_size = rlen + frag_rx->lcptr - frag_rx->laptr; + frag_rx->pkt_lenm1 = frag_size - 1; + + mbuf = (struct rte_mbuf *)((uintptr_t)wqe - + sizeof(struct rte_mbuf)); + *(uint64_t *)(&mbuf->rearm_data) = mbuf_init; + mbuf->data_len = frag_size; + mbuf->pkt_len = frag_size; + mbuf->ol_flags = ol_flags; + mbuf->next = NULL; + + /* Update dynamic field with userdata */ + *rte_security_dynfield(mbuf) = (uint64_t)inb_priv->userdata; + + cnxk_ip_reass_dynfield(mbuf, off)->nb_frags = + hdr->w0.num_frags - 2; + cnxk_ip_reass_dynfield(mbuf, off)->next_frag = NULL; + cnxk_ip_reass_dynfield(mbuf_prev, off)->next_frag = mbuf; + mbuf_prev = mbuf; + } + + /* Frag-2: */ + if (hdr->w0.num_frags > 2) { + frag_ptr = (uint64_t *)(finfo + 1); + wqe = (uint64_t *)(rte_be_to_cpu_64(*frag_ptr)); + rlen = ((*(wqe + 10)) >> 16) & 0xFFFF; + + frag_rx = (union nix_rx_parse_u *)(wqe + 1); + frag_size = rlen + frag_rx->lcptr - frag_rx->laptr; + frag_rx->pkt_lenm1 = frag_size - 1; + + mbuf = (struct rte_mbuf *)((uintptr_t)wqe - + sizeof(struct rte_mbuf)); + *(uint64_t *)(&mbuf->rearm_data) = mbuf_init; + mbuf->data_len = frag_size; + mbuf->pkt_len = frag_size; + mbuf->ol_flags = ol_flags; + mbuf->next = NULL; + + /* Update dynamic field with userdata */ + *rte_security_dynfield(mbuf) = (uint64_t)inb_priv->userdata; + + cnxk_ip_reass_dynfield(mbuf, off)->nb_frags = + hdr->w0.num_frags - 3; + cnxk_ip_reass_dynfield(mbuf, off)->next_frag = NULL; + cnxk_ip_reass_dynfield(mbuf_prev, off)->next_frag = mbuf; + mbuf_prev = mbuf; + } + + /* Frag-3: */ + if (hdr->w0.num_frags > 3) { + wqe = (uint64_t *)(rte_be_to_cpu_64(*(frag_ptr + 1))); + rlen = ((*(wqe + 10)) >> 16) & 0xFFFF; + + frag_rx = (union nix_rx_parse_u *)(wqe + 1); + frag_size = rlen + frag_rx->lcptr - frag_rx->laptr; + frag_rx->pkt_lenm1 = frag_size - 1; + + mbuf = (struct rte_mbuf *)((uintptr_t)wqe - + sizeof(struct rte_mbuf)); + *(uint64_t *)(&mbuf->rearm_data) = mbuf_init; + mbuf->data_len = frag_size; + mbuf->pkt_len = frag_size; + mbuf->ol_flags = ol_flags; + mbuf->next = NULL; + + /* Update dynamic field with userdata */ + *rte_security_dynfield(mbuf) = (uint64_t)inb_priv->userdata; + + cnxk_ip_reass_dynfield(mbuf, off)->nb_frags = + hdr->w0.num_frags - 4; + cnxk_ip_reass_dynfield(mbuf, off)->next_frag = NULL; + cnxk_ip_reass_dynfield(mbuf_prev, off)->next_frag = mbuf; + } + return head; +} + +static struct rte_mbuf * +nix_sec_reassemble_frags(const struct cpt_parse_hdr_s *hdr, uint64_t cq_w1, + uint64_t cq_w5, uint64_t mbuf_init) +{ + uint32_t fragx_sum, pkt_hdr_len, l3_hdr_size; + uint32_t offset = hdr->w2.fi_offset; + union nix_rx_parse_u *inner_rx; + uint16_t rlen, data_off, b_off; + union nix_rx_parse_u *frag_rx; + struct cpt_frag_info_s *finfo; + struct rte_mbuf *head, *mbuf; + rte_iova_t *inner_iova; + uint64_t *frag_ptr; + uint16_t frag_size; + uint64_t *wqe; + + /* Base data offset */ + b_off = mbuf_init & 0xFFFFUL; + mbuf_init &= ~0xFFFFUL; + + /* offset of 0 implies 256B, otherwise it implies offset*8B */ + offset = (((offset - 1) & 0x1f) + 1) * 8; + finfo = RTE_PTR_ADD(hdr, offset + hdr->w2.fi_pad); + + /* Frag-0: */ + wqe = (uint64_t *)rte_be_to_cpu_64(hdr->wqe_ptr); + inner_rx = (union nix_rx_parse_u *)(wqe + 1); + inner_iova = (rte_iova_t *)*(wqe + 9); + + /* Update only the upper 28-bits from meta pkt parse info */ + *((uint64_t *)inner_rx) = ((*((uint64_t *)inner_rx) & ((1ULL << 36) - 1)) | + (cq_w1 & ~((1ULL << 36) - 1))); + + rlen = ((*(wqe + 10)) >> 16) & 0xFFFF; + frag_size = rlen + ((cq_w5 >> 16) & 0xFF) - (cq_w5 & 0xFF); + fragx_sum = rte_be_to_cpu_16(finfo->w1.frag_size0); + pkt_hdr_len = frag_size - fragx_sum; + + mbuf = (struct rte_mbuf *)((uintptr_t)wqe - sizeof(struct rte_mbuf)); + *(uint64_t *)(&mbuf->rearm_data) = mbuf_init | b_off; + mbuf->data_len = frag_size; + head = mbuf; + + if (inner_rx->lctype == NPC_LT_LC_IP) { + struct rte_ipv4_hdr *hdr = (struct rte_ipv4_hdr *) + RTE_PTR_ADD(inner_iova, inner_rx->lcptr); + + l3_hdr_size = (hdr->version_ihl & 0xf) << 2; + } else { + struct rte_ipv6_hdr *hdr = (struct rte_ipv6_hdr *) + RTE_PTR_ADD(inner_iova, inner_rx->lcptr); + size_t ext_len = sizeof(struct rte_ipv6_hdr); + uint8_t *nxt_hdr = (uint8_t *)hdr; + int nh = hdr->proto; + + l3_hdr_size = 0; + while (nh != -EINVAL) { + nxt_hdr += ext_len; + l3_hdr_size += ext_len; + nh = rte_ipv6_get_next_ext(nxt_hdr, nh, &ext_len); + } + } + + /* Frag-1: */ + wqe = (uint64_t *)(rte_be_to_cpu_64(hdr->frag1_wqe_ptr)); + frag_size = rte_be_to_cpu_16(finfo->w1.frag_size1); + frag_rx = (union nix_rx_parse_u *)(wqe + 1); + + mbuf->next = (struct rte_mbuf *)((uintptr_t)wqe - sizeof(struct rte_mbuf)); + mbuf = mbuf->next; + data_off = b_off + frag_rx->lcptr + l3_hdr_size; + *(uint64_t *)(&mbuf->rearm_data) = mbuf_init | data_off; + mbuf->data_len = frag_size; + fragx_sum += frag_size; + + /* Frag-2: */ + if (hdr->w0.num_frags > 2) { + frag_ptr = (uint64_t *)(finfo + 1); + wqe = (uint64_t *)(rte_be_to_cpu_64(*frag_ptr)); + frag_size = rte_be_to_cpu_16(finfo->w1.frag_size2); + frag_rx = (union nix_rx_parse_u *)(wqe + 1); + + mbuf->next = (struct rte_mbuf *)((uintptr_t)wqe - sizeof(struct rte_mbuf)); + mbuf = mbuf->next; + data_off = b_off + frag_rx->lcptr + l3_hdr_size; + *(uint64_t *)(&mbuf->rearm_data) = mbuf_init | data_off; + mbuf->data_len = frag_size; + fragx_sum += frag_size; + } + + /* Frag-3: */ + if (hdr->w0.num_frags > 3) { + wqe = (uint64_t *)(rte_be_to_cpu_64(*(frag_ptr + 1))); + frag_size = rte_be_to_cpu_16(finfo->w1.frag_size3); + frag_rx = (union nix_rx_parse_u *)(wqe + 1); + + mbuf->next = (struct rte_mbuf *)((uintptr_t)wqe - sizeof(struct rte_mbuf)); + mbuf = mbuf->next; + data_off = b_off + frag_rx->lcptr + l3_hdr_size; + *(uint64_t *)(&mbuf->rearm_data) = mbuf_init | data_off; + mbuf->data_len = frag_size; + fragx_sum += frag_size; + } + + if (inner_rx->lctype == NPC_LT_LC_IP) { + struct rte_ipv4_hdr *hdr = (struct rte_ipv4_hdr *) + RTE_PTR_ADD(inner_iova, inner_rx->lcptr); + + hdr->fragment_offset = 0; + hdr->total_length = rte_cpu_to_be_16(fragx_sum + l3_hdr_size); + hdr->hdr_checksum = 0; + hdr->hdr_checksum = rte_ipv4_cksum(hdr); + + inner_rx->pkt_lenm1 = pkt_hdr_len + fragx_sum - 1; + } else { + /* Remove the frag header by moving header 8 bytes forward */ + struct rte_ipv6_hdr *hdr = (struct rte_ipv6_hdr *) + RTE_PTR_ADD(inner_iova, inner_rx->lcptr); + + hdr->payload_len = rte_cpu_to_be_16(fragx_sum + l3_hdr_size - + 8 - sizeof(struct rte_ipv6_hdr)); + + rte_memcpy(rte_pktmbuf_mtod_offset(head, void *, 8), + rte_pktmbuf_mtod(head, void *), + inner_rx->lcptr + sizeof(struct rte_ipv6_hdr)); + + inner_rx->pkt_lenm1 = pkt_hdr_len + fragx_sum - 8 - 1; + head->data_len -= 8; + head->data_off += 8; + } + mbuf->next = NULL; + head->pkt_len = inner_rx->pkt_lenm1 + 1; + head->nb_segs = hdr->w0.num_frags; + + return head; +} + static __rte_always_inline struct rte_mbuf * -nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, const uint64_t sa_base, uintptr_t laddr, - uint8_t *loff, struct rte_mbuf *mbuf, uint16_t data_off) +nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, const uint64_t sa_base, + uintptr_t laddr, uint8_t *loff, struct rte_mbuf *mbuf, + uint16_t data_off, const uint16_t flags, + const uint64_t mbuf_init) { const void *__p = (void *)((uintptr_t)mbuf + (uint16_t)data_off); const struct cpt_parse_hdr_s *hdr = (const struct cpt_parse_hdr_s *)__p; struct cn10k_inb_priv_data *inb_priv; - struct rte_mbuf *inner; + struct rte_mbuf *inner = NULL; + uint64_t res_w1; uint32_t sa_idx; + uint16_t uc_cc; + uint32_t len; void *inb_sa; uint64_t w0; - if (cq_w1 & BIT(11)) { + if ((flags & NIX_RX_OFFLOAD_REASSEMBLY_F) && (cq_w1 & BIT(11))) { + /* Get SPI from CPT_PARSE_S's cookie(already swapped) */ + w0 = hdr->w0.u64; + sa_idx = w0 >> 32; + + inb_sa = roc_nix_inl_ot_ipsec_inb_sa(sa_base, sa_idx); + inb_priv = roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(inb_sa); + + if (!hdr->w0.num_frags) { + /* No Reassembly or inbound error */ + inner = (struct rte_mbuf *) + (rte_be_to_cpu_64(hdr->wqe_ptr) - + sizeof(struct rte_mbuf)); + + /* Update dynamic field with userdata */ + *rte_security_dynfield(inner) = + (uint64_t)inb_priv->userdata; + + /* CPT result(struct cpt_cn10k_res_s) is at + * after first IOVA in meta + */ + res_w1 = *((uint64_t *)(&inner[1]) + 10); + uc_cc = res_w1 & 0xFF; + + /* Calculate inner packet length */ + len = ((res_w1 >> 16) & 0xFFFF) + hdr->w2.il3_off - + sizeof(struct cpt_parse_hdr_s) - (w0 & 0x7); + inner->pkt_len = len; + inner->data_len = len; + *(uint64_t *)(&inner->rearm_data) = mbuf_init; + + inner->ol_flags = ((uc_cc == CPT_COMP_WARN) ? + RTE_MBUF_F_RX_SEC_OFFLOAD : + (RTE_MBUF_F_RX_SEC_OFFLOAD | + RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED)); + inner->next = NULL; + } else if (!(hdr->w0.err_sum) && !(hdr->w0.reas_sts)) { + /* Reassembly success */ + inner = nix_sec_reassemble_frags(hdr, cq_w1, cq_w5, + mbuf_init); + + /* Update dynamic field with userdata */ + *rte_security_dynfield(inner) = + (uint64_t)inb_priv->userdata; + + /* Assume success */ + inner->ol_flags = RTE_MBUF_F_RX_SEC_OFFLOAD; + } else { + /* Reassembly failure */ + inner = nix_sec_attach_frags(hdr, inb_priv, mbuf_init); + } + + /* Store meta in lmtline to free + * Assume all meta's from same aura. + */ + *(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf; + *loff = *loff + 1; + + return inner; + } else if (cq_w1 & BIT(11)) { inner = (struct rte_mbuf *)(rte_be_to_cpu_64(hdr->wqe_ptr) - sizeof(struct rte_mbuf)); @@ -113,8 +453,25 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, const uint64_t sa_base, uintptr_t laddr, *rte_security_dynfield(inner) = (uint64_t)inb_priv->userdata; /* Update l2 hdr length first */ - inner->pkt_len = (hdr->w2.il3_off - - sizeof(struct cpt_parse_hdr_s) - (w0 & 0x7)); + + /* CPT result(struct cpt_cn10k_res_s) is at + * after first IOVA in meta + */ + res_w1 = *((uint64_t *)(&inner[1]) + 10); + uc_cc = res_w1 & 0xFF; + + /* Calculate inner packet length */ + len = ((res_w1 >> 16) & 0xFFFF) + hdr->w2.il3_off - + sizeof(struct cpt_parse_hdr_s) - (w0 & 0x7); + inner->pkt_len = len; + inner->data_len = len; + *(uint64_t *)(&inner->rearm_data) = mbuf_init; + + inner->ol_flags = ((uc_cc == CPT_COMP_WARN) ? + RTE_MBUF_F_RX_SEC_OFFLOAD : + (RTE_MBUF_F_RX_SEC_OFFLOAD | + RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED)); + inner->next = NULL; /* Store meta in lmtline to free * Assume all meta's from same aura. @@ -124,18 +481,23 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, const uint64_t sa_base, uintptr_t laddr, return inner; } + + mbuf->next = NULL; return mbuf; } #if defined(RTE_ARCH_ARM64) static __rte_always_inline struct rte_mbuf * -nix_sec_meta_to_mbuf(uint64_t cq_w1, uintptr_t sa_base, uintptr_t laddr, - uint8_t *loff, struct rte_mbuf *mbuf, uint16_t data_off, - uint8x16_t *rx_desc_field1, uint64_t *ol_flags) +nix_sec_meta_to_mbuf(uint64_t cq_w1, uint64_t cq_w5, uintptr_t sa_base, + uintptr_t laddr, uint8_t *loff, struct rte_mbuf *mbuf, + uint16_t data_off, uint8x16_t *rx_desc_field1, + uint64_t *ol_flags, const uint16_t flags, + uint64x2_t *rearm) { const void *__p = (void *)((uintptr_t)mbuf + (uint16_t)data_off); const struct cpt_parse_hdr_s *hdr = (const struct cpt_parse_hdr_s *)__p; + uint64_t mbuf_init = vgetq_lane_u64(*rearm, 0); struct cn10k_inb_priv_data *inb_priv; struct rte_mbuf *inner; uint64_t *sg, res_w1; @@ -144,7 +506,102 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uintptr_t sa_base, uintptr_t laddr, uint16_t len; uint64_t w0; - if (cq_w1 & BIT(11)) { + if ((flags & NIX_RX_OFFLOAD_REASSEMBLY_F) && (cq_w1 & BIT(11))) { + w0 = hdr->w0.u64; + sa_idx = w0 >> 32; + + /* Get SPI from CPT_PARSE_S's cookie(already swapped) */ + w0 = hdr->w0.u64; + sa_idx = w0 >> 32; + + inb_sa = roc_nix_inl_ot_ipsec_inb_sa(sa_base, sa_idx); + inb_priv = roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(inb_sa); + + /* Clear checksum flags */ + *ol_flags &= ~(RTE_MBUF_F_RX_L4_CKSUM_MASK | + RTE_MBUF_F_RX_IP_CKSUM_MASK); + + if (!hdr->w0.num_frags) { + /* No Reassembly or inbound error */ + inner = (struct rte_mbuf *) + (rte_be_to_cpu_64(hdr->wqe_ptr) - + sizeof(struct rte_mbuf)); + /* Update dynamic field with userdata */ + *rte_security_dynfield(inner) = + (uint64_t)inb_priv->userdata; + + /* CPT result(struct cpt_cn10k_res_s) is at + * after first IOVA in meta + */ + sg = (uint64_t *)(inner + 1); + res_w1 = sg[10]; + + /* Clear checksum flags and update security flag + */ + *ol_flags &= ~(RTE_MBUF_F_RX_L4_CKSUM_MASK | + RTE_MBUF_F_RX_IP_CKSUM_MASK); + *ol_flags |= + (((res_w1 & 0xFF) == CPT_COMP_WARN) ? + RTE_MBUF_F_RX_SEC_OFFLOAD : + (RTE_MBUF_F_RX_SEC_OFFLOAD | + RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED)); + /* Calculate inner packet length */ + len = ((res_w1 >> 16) & 0xFFFF) + + hdr->w2.il3_off - + sizeof(struct cpt_parse_hdr_s) - + (w0 & 0x7); + /* Update pkt_len and data_len */ + *rx_desc_field1 = + vsetq_lane_u16(len, *rx_desc_field1, 2); + *rx_desc_field1 = + vsetq_lane_u16(len, *rx_desc_field1, 4); + + inner->next = NULL; + } else if (!(hdr->w0.err_sum) && !(hdr->w0.reas_sts)) { + /* Reassembly success */ + inner = nix_sec_reassemble_frags(hdr, cq_w1, cq_w5, + mbuf_init); + sg = (uint64_t *)(inner + 1); + res_w1 = sg[10]; + + /* Update dynamic field with userdata */ + *rte_security_dynfield(inner) = + (uint64_t)inb_priv->userdata; + + /* Assume success */ + *ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD; + + /* Update pkt_len and data_len */ + *rx_desc_field1 = vsetq_lane_u16(inner->pkt_len, + *rx_desc_field1, 2); + *rx_desc_field1 = vsetq_lane_u16(inner->data_len, + *rx_desc_field1, 4); + + /* Data offset might be updated */ + mbuf_init = *(uint64_t *)(&inner->rearm_data); + *rearm = vsetq_lane_u64(mbuf_init, *rearm, 0); + } else { + /* Reassembly failure */ + inner = nix_sec_attach_frags(hdr, inb_priv, mbuf_init); + *ol_flags |= inner->ol_flags; + + /* Update pkt_len and data_len */ + *rx_desc_field1 = vsetq_lane_u16(inner->pkt_len, + *rx_desc_field1, 2); + *rx_desc_field1 = vsetq_lane_u16(inner->data_len, + *rx_desc_field1, 4); + } + + /* Store meta in lmtline to free + * Assume all meta's from same aura. + */ + *(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf; + *loff = *loff + 1; + + /* Return inner mbuf */ + return inner; + + } else if (cq_w1 & BIT(11)) { inner = (struct rte_mbuf *)(rte_be_to_cpu_64(hdr->wqe_ptr) - sizeof(struct rte_mbuf)); /* Get SPI from CPT_PARSE_S's cookie(already swapped) */ @@ -181,10 +638,12 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uintptr_t sa_base, uintptr_t laddr, *(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf; *loff = *loff + 1; + inner->next = NULL; /* Return inner mbuf */ return inner; } + mbuf->next = NULL; /* Return same mbuf as it is not a decrypted pkt */ return mbuf; } @@ -253,7 +712,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, sg = *(const uint64_t *)(rx + 1); nb_segs = (sg >> 48) & 0x3; - if (nb_segs == 1) { + if (nb_segs == 1 && !(flags & NIX_RX_SEC_REASS_F)) { mbuf->next = NULL; return; } @@ -319,30 +778,10 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag, ol_flags |= RTE_MBUF_F_RX_RSS_HASH; } - /* Process Security packets */ - if (flag & NIX_RX_OFFLOAD_SECURITY_F) { - if (w1 & BIT(11)) { - /* CPT result(struct cpt_cn10k_res_s) is at - * after first IOVA in meta - */ - const uint64_t *sg = (const uint64_t *)(mbuf + 1); - const uint64_t res_w1 = sg[10]; - const uint16_t uc_cc = res_w1 & 0xFF; - - /* Rlen */ - len = ((res_w1 >> 16) & 0xFFFF) + mbuf->pkt_len; - ol_flags |= ((uc_cc == CPT_COMP_WARN) ? - RTE_MBUF_F_RX_SEC_OFFLOAD : - (RTE_MBUF_F_RX_SEC_OFFLOAD | - RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED)); - } else { - if (flag & NIX_RX_OFFLOAD_CHECKSUM_F) - ol_flags |= nix_rx_olflags_get(lookup_mem, w1); - } - } else { - if (flag & NIX_RX_OFFLOAD_CHECKSUM_F) - ol_flags |= nix_rx_olflags_get(lookup_mem, w1); - } + /* Skip rx ol flags extraction for Security packets */ + if ((!(flag & NIX_RX_SEC_REASS_F) || !(w1 & BIT(11))) && + flag & NIX_RX_OFFLOAD_CHECKSUM_F) + ol_flags |= nix_rx_olflags_get(lookup_mem, w1); if (flag & NIX_RX_OFFLOAD_VLAN_STRIP_F) { if (rx->vtag0_gone) { @@ -358,14 +797,19 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag, if (flag & NIX_RX_OFFLOAD_MARK_UPDATE_F) ol_flags = nix_update_match_id(rx->match_id, ol_flags, mbuf); - mbuf->ol_flags = ol_flags; - mbuf->pkt_len = len; - mbuf->data_len = len; - *(uint64_t *)(&mbuf->rearm_data) = val; + /* Packet data length and ol flags is already updated for sec */ + if (flag & NIX_RX_SEC_REASS_F && w1 & BIT_ULL(11)) { + mbuf->ol_flags |= ol_flags; + } else { + mbuf->ol_flags = ol_flags; + mbuf->pkt_len = len; + mbuf->data_len = len; + *(uint64_t *)(&mbuf->rearm_data) = val; + } if (flag & NIX_RX_MULTI_SEG_F) nix_cqe_xtract_mseg(rx, mbuf, val, flag); - else + else if (!(flag & NIX_RX_SEC_REASS_F)) mbuf->next = NULL; } @@ -443,9 +887,11 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts, /* Translate meta to mbuf */ if (flags & NIX_RX_OFFLOAD_SECURITY_F) { const uint64_t cq_w1 = *((const uint64_t *)cq + 1); + const uint64_t cq_w5 = *((const uint64_t *)cq + 5); - mbuf = nix_sec_meta_to_mbuf_sc(cq_w1, sa_base, laddr, - &loff, mbuf, data_off); + mbuf = nix_sec_meta_to_mbuf_sc(cq_w1, cq_w5, sa_base, laddr, + &loff, mbuf, data_off, + flags, mbuf_init); } cn10k_nix_cqe_to_mbuf(cq, cq->tag, mbuf, lookup_mem, mbuf_init, @@ -711,25 +1157,40 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, /* Translate meta to mbuf */ if (flags & NIX_RX_OFFLOAD_SECURITY_F) { + uint64_t cq0_w5 = *(uint64_t *)(cq0 + CQE_SZ(0) + 40); + uint64_t cq1_w5 = *(uint64_t *)(cq0 + CQE_SZ(1) + 40); + uint64_t cq2_w5 = *(uint64_t *)(cq0 + CQE_SZ(2) + 40); + uint64_t cq3_w5 = *(uint64_t *)(cq0 + CQE_SZ(3) + 40); + + /* Initialize rearm data when reassembly is enabled as + * data offset might change. + */ + if (flags & NIX_RX_OFFLOAD_REASSEMBLY_F) { + rearm0 = vdupq_n_u64(mbuf_initializer); + rearm1 = vdupq_n_u64(mbuf_initializer); + rearm2 = vdupq_n_u64(mbuf_initializer); + rearm3 = vdupq_n_u64(mbuf_initializer); + } + /* Checksum ol_flags will be cleared if mbuf is meta */ - mbuf0 = nix_sec_meta_to_mbuf(cq0_w1, sa_base, laddr, + mbuf0 = nix_sec_meta_to_mbuf(cq0_w1, cq0_w5, sa_base, laddr, &loff, mbuf0, d_off, &f0, - &ol_flags0); + &ol_flags0, flags, &rearm0); mbuf01 = vsetq_lane_u64((uint64_t)mbuf0, mbuf01, 0); - mbuf1 = nix_sec_meta_to_mbuf(cq1_w1, sa_base, laddr, + mbuf1 = nix_sec_meta_to_mbuf(cq1_w1, cq1_w5, sa_base, laddr, &loff, mbuf1, d_off, &f1, - &ol_flags1); + &ol_flags1, flags, &rearm1); mbuf01 = vsetq_lane_u64((uint64_t)mbuf1, mbuf01, 1); - mbuf2 = nix_sec_meta_to_mbuf(cq2_w1, sa_base, laddr, + mbuf2 = nix_sec_meta_to_mbuf(cq2_w1, cq2_w5, sa_base, laddr, &loff, mbuf2, d_off, &f2, - &ol_flags2); + &ol_flags2, flags, &rearm2); mbuf23 = vsetq_lane_u64((uint64_t)mbuf2, mbuf23, 0); - mbuf3 = nix_sec_meta_to_mbuf(cq3_w1, sa_base, laddr, + mbuf3 = nix_sec_meta_to_mbuf(cq3_w1, cq3_w5, sa_base, laddr, &loff, mbuf3, d_off, &f3, - &ol_flags3); + &ol_flags3, flags, &rearm3); mbuf23 = vsetq_lane_u64((uint64_t)mbuf3, mbuf23, 1); } @@ -891,7 +1352,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, nix_cqe_xtract_mseg((union nix_rx_parse_u *) (CQE_PTR_OFF(cq0, 3, 8, flags)), mbuf3, mbuf_initializer, flags); - } else { + } else if (!(flags & NIX_RX_SEC_REASS_F)) { /* Update that no more segments */ mbuf0->next = NULL; mbuf1->next = NULL; @@ -986,6 +1447,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, #define TS_F NIX_RX_OFFLOAD_TSTAMP_F #define RX_VLAN_F NIX_RX_OFFLOAD_VLAN_STRIP_F #define R_SEC_F NIX_RX_OFFLOAD_SECURITY_F +#define R_REAS_F NIX_RX_OFFLOAD_REASSEMBLY_F /* [R_SEC_F] [RX_VLAN_F] [TS] [MARK] [CKSUM] [PTYPE] [RSS] */ #define NIX_RX_FASTPATH_MODES_0_15 \ @@ -1152,6 +1614,101 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, R(sec_vlan_ts_mark_cksum_ptype_rss, \ R_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) +/* R_REAS_F cannot work without R_SEC_F */ +#define NIX_RX_FASTPATH_MODES_128_143 +#define NIX_RX_FASTPATH_MODES_144_159 +#define NIX_RX_FASTPATH_MODES_160_175 +#define NIX_RX_FASTPATH_MODES_176_191 + +#define NIX_RX_FASTPATH_MODES_192_207 \ + R(reas_sec, R_REAS_F | R_SEC_F) \ + R(reas_sec_rss, R_REAS_F | R_SEC_F | RSS_F) \ + R(reas_sec_ptype, R_REAS_F | R_SEC_F | PTYPE_F) \ + R(reas_sec_ptype_rss, R_REAS_F | R_SEC_F | PTYPE_F | RSS_F) \ + R(reas_sec_cksum, R_REAS_F | R_SEC_F | CKSUM_F) \ + R(reas_sec_cksum_rss, R_REAS_F | R_SEC_F | CKSUM_F | RSS_F) \ + R(reas_sec_cksum_ptype, R_REAS_F | R_SEC_F | CKSUM_F | PTYPE_F) \ + R(reas_sec_cksum_ptype_rss, R_REAS_F | R_SEC_F | CKSUM_F | PTYPE_F | RSS_F) \ + R(reas_sec_mark, R_REAS_F | R_SEC_F | MARK_F) \ + R(reas_sec_mark_rss, R_REAS_F | R_SEC_F | MARK_F | RSS_F) \ + R(reas_sec_mark_ptype, R_REAS_F | R_SEC_F | MARK_F | PTYPE_F) \ + R(reas_sec_mark_ptype_rss, R_REAS_F | R_SEC_F | MARK_F | PTYPE_F | RSS_F) \ + R(reas_sec_mark_cksum, R_REAS_F | R_SEC_F | MARK_F | CKSUM_F) \ + R(reas_sec_mark_cksum_rss, R_REAS_F | R_SEC_F | MARK_F | CKSUM_F | RSS_F) \ + R(reas_sec_mark_cksum_ptype, R_REAS_F | R_SEC_F | MARK_F | CKSUM_F | PTYPE_F) \ + R(reas_sec_mark_cksum_ptype_rss, \ + R_REAS_F | R_SEC_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) + +#define NIX_RX_FASTPATH_MODES_208_223 \ + R(reas_sec_ts, R_REAS_F | R_SEC_F | TS_F) \ + R(reas_sec_ts_rss, R_REAS_F | R_SEC_F | TS_F | RSS_F) \ + R(reas_sec_ts_ptype, R_REAS_F | R_SEC_F | TS_F | PTYPE_F) \ + R(reas_sec_ts_ptype_rss, R_REAS_F | R_SEC_F | TS_F | PTYPE_F | RSS_F) \ + R(reas_sec_ts_cksum, R_REAS_F | R_SEC_F | TS_F | CKSUM_F) \ + R(reas_sec_ts_cksum_rss, R_REAS_F | R_SEC_F | TS_F | CKSUM_F | RSS_F) \ + R(reas_sec_ts_cksum_ptype, R_REAS_F | R_SEC_F | TS_F | CKSUM_F | PTYPE_F) \ + R(reas_sec_ts_cksum_ptype_rss, R_REAS_F | R_SEC_F | TS_F | CKSUM_F | PTYPE_F | RSS_F) \ + R(reas_sec_ts_mark, R_REAS_F | R_SEC_F | TS_F | MARK_F) \ + R(reas_sec_ts_mark_rss, R_REAS_F | R_SEC_F | TS_F | MARK_F | RSS_F) \ + R(reas_sec_ts_mark_ptype, R_REAS_F | R_SEC_F | TS_F | MARK_F | PTYPE_F) \ + R(reas_sec_ts_mark_ptype_rss, R_REAS_F | R_SEC_F | TS_F | MARK_F | PTYPE_F | RSS_F) \ + R(reas_sec_ts_mark_cksum, R_REAS_F | R_SEC_F | TS_F | MARK_F | CKSUM_F) \ + R(reas_sec_ts_mark_cksum_rss, R_REAS_F | R_SEC_F | TS_F | MARK_F | CKSUM_F | RSS_F) \ + R(reas_sec_ts_mark_cksum_ptype, \ + R_REAS_F | R_SEC_F | TS_F | MARK_F | CKSUM_F | PTYPE_F) \ + R(reas_sec_ts_mark_cksum_ptype_rss, \ + R_REAS_F | R_SEC_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) + +#define NIX_RX_FASTPATH_MODES_224_239 \ + R(reas_sec_vlan, R_REAS_F | R_SEC_F | RX_VLAN_F) \ + R(reas_sec_vlan_rss, R_REAS_F | R_SEC_F | RX_VLAN_F | RSS_F) \ + R(reas_sec_vlan_ptype, R_REAS_F | R_SEC_F | RX_VLAN_F | PTYPE_F) \ + R(reas_sec_vlan_ptype_rss, R_REAS_F | R_SEC_F | RX_VLAN_F | PTYPE_F | RSS_F) \ + R(reas_sec_vlan_cksum, R_REAS_F | R_SEC_F | RX_VLAN_F | CKSUM_F) \ + R(reas_sec_vlan_cksum_rss, R_REAS_F | R_SEC_F | RX_VLAN_F | CKSUM_F | RSS_F) \ + R(reas_sec_vlan_cksum_ptype, R_REAS_F | R_SEC_F | RX_VLAN_F | CKSUM_F | PTYPE_F) \ + R(reas_sec_vlan_cksum_ptype_rss, \ + R_REAS_F | R_SEC_F | RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F) \ + R(reas_sec_vlan_mark, R_REAS_F | R_SEC_F | RX_VLAN_F | MARK_F) \ + R(reas_sec_vlan_mark_rss, R_REAS_F | R_SEC_F | RX_VLAN_F | MARK_F | RSS_F) \ + R(reas_sec_vlan_mark_ptype, R_REAS_F | R_SEC_F | RX_VLAN_F | MARK_F | PTYPE_F) \ + R(reas_sec_vlan_mark_ptype_rss, \ + R_REAS_F | R_SEC_F | RX_VLAN_F | MARK_F | PTYPE_F | RSS_F) \ + R(reas_sec_vlan_mark_cksum, R_REAS_F | R_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F) \ + R(reas_sec_vlan_mark_cksum_rss, \ + R_REAS_F | R_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F | RSS_F) \ + R(reas_sec_vlan_mark_cksum_ptype, \ + R_REAS_F | R_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F) \ + R(reas_sec_vlan_mark_cksum_ptype_rss, \ + R_REAS_F | R_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) + +#define NIX_RX_FASTPATH_MODES_240_255 \ + R(reas_sec_vlan_ts, R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F) \ + R(reas_sec_vlan_ts_rss, R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | RSS_F) \ + R(reas_sec_vlan_ts_ptype, R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | PTYPE_F) \ + R(reas_sec_vlan_ts_ptype_rss, R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | PTYPE_F | RSS_F) \ + R(reas_sec_vlan_ts_cksum, R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | CKSUM_F) \ + R(reas_sec_vlan_ts_cksum_rss, R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | CKSUM_F | RSS_F) \ + R(reas_sec_vlan_ts_cksum_ptype, \ + R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F) \ + R(reas_sec_vlan_ts_cksum_ptype_rss, \ + R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F | RSS_F) \ + R(reas_sec_vlan_ts_mark, R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | MARK_F) \ + R(reas_sec_vlan_ts_mark_rss, R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | MARK_F | RSS_F) \ + R(reas_sec_vlan_ts_mark_ptype, \ + R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | MARK_F | PTYPE_F) \ + R(reas_sec_vlan_ts_mark_ptype_rss, \ + R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | MARK_F | PTYPE_F | RSS_F) \ + R(reas_sec_vlan_ts_mark_cksum, \ + R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F) \ + R(reas_sec_vlan_ts_mark_cksum_rss, \ + R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F | RSS_F) \ + R(reas_sec_vlan_ts_mark_cksum_ptype, \ + R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F) \ + R(reas_sec_vlan_ts_mark_cksum_ptype_rss, \ + R_REAS_F | R_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) + + #define NIX_RX_FASTPATH_MODES \ NIX_RX_FASTPATH_MODES_0_15 \ NIX_RX_FASTPATH_MODES_16_31 \ @@ -1160,7 +1717,15 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, NIX_RX_FASTPATH_MODES_64_79 \ NIX_RX_FASTPATH_MODES_80_95 \ NIX_RX_FASTPATH_MODES_96_111 \ - NIX_RX_FASTPATH_MODES_112_127 + NIX_RX_FASTPATH_MODES_112_127 \ + NIX_RX_FASTPATH_MODES_128_143 \ + NIX_RX_FASTPATH_MODES_144_159 \ + NIX_RX_FASTPATH_MODES_160_175 \ + NIX_RX_FASTPATH_MODES_176_191 \ + NIX_RX_FASTPATH_MODES_192_207 \ + NIX_RX_FASTPATH_MODES_208_223 \ + NIX_RX_FASTPATH_MODES_224_239 \ + NIX_RX_FASTPATH_MODES_240_255 #define R(name, flags) \ uint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_##name( \ diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 74f625553d..47810a2c64 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -12,6 +12,9 @@ nix_get_rx_offload_capa(struct cnxk_eth_dev *dev) dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG) capa &= ~RTE_ETH_RX_OFFLOAD_TIMESTAMP; + if (roc_model_is_cn10ka() && !roc_nix_is_sdp(&dev->nix)) + capa |= RTE_ETH_RX_OFFLOAD_IP_REASSEMBLY; + return capa; } diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 5bfda3d815..0ea46ec710 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -398,6 +398,10 @@ struct cnxk_eth_dev { /* Security data */ struct cnxk_eth_dev_sec_inb inb; struct cnxk_eth_dev_sec_outb outb; + + /* Reassembly dynfield/flag offsets */ + int reass_dynfield_off; + int reass_dynflag_bit; }; struct cnxk_eth_rxq_sp { diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index ce5f1f7240..6ae9c706d9 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -65,6 +65,11 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) .nb_mtu_seg_max = CNXK_NIX_TX_NB_SEG_MAX, }; + if (roc_model_is_cn10ka()) { + devinfo->reass_capa.reass_timeout = 60 * 1000; + devinfo->reass_capa.max_frags = 4; + } + devinfo->speed_capa = dev->speed_capa; devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; diff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build index 375c75d1c7..35b9b4fbdb 100644 --- a/drivers/net/cnxk/meson.build +++ b/drivers/net/cnxk/meson.build @@ -120,6 +120,14 @@ sources += files( 'rx/cn10k/rx_80_95.c', 'rx/cn10k/rx_96_111.c', 'rx/cn10k/rx_112_127.c', + 'rx/cn10k/rx_128_143.c', + 'rx/cn10k/rx_144_159.c', + 'rx/cn10k/rx_160_175.c', + 'rx/cn10k/rx_176_191.c', + 'rx/cn10k/rx_192_207.c', + 'rx/cn10k/rx_208_223.c', + 'rx/cn10k/rx_224_239.c', + 'rx/cn10k/rx_240_255.c', 'rx/cn10k/rx_0_15_mseg.c', 'rx/cn10k/rx_16_31_mseg.c', 'rx/cn10k/rx_32_47_mseg.c', @@ -128,6 +136,14 @@ sources += files( 'rx/cn10k/rx_80_95_mseg.c', 'rx/cn10k/rx_96_111_mseg.c', 'rx/cn10k/rx_112_127_mseg.c', + 'rx/cn10k/rx_128_143_mseg.c', + 'rx/cn10k/rx_144_159_mseg.c', + 'rx/cn10k/rx_160_175_mseg.c', + 'rx/cn10k/rx_176_191_mseg.c', + 'rx/cn10k/rx_192_207_mseg.c', + 'rx/cn10k/rx_208_223_mseg.c', + 'rx/cn10k/rx_224_239_mseg.c', + 'rx/cn10k/rx_240_255_mseg.c', 'rx/cn10k/rx_0_15_vec.c', 'rx/cn10k/rx_16_31_vec.c', 'rx/cn10k/rx_32_47_vec.c', @@ -136,6 +152,14 @@ sources += files( 'rx/cn10k/rx_80_95_vec.c', 'rx/cn10k/rx_96_111_vec.c', 'rx/cn10k/rx_112_127_vec.c', + 'rx/cn10k/rx_128_143_vec.c', + 'rx/cn10k/rx_144_159_vec.c', + 'rx/cn10k/rx_160_175_vec.c', + 'rx/cn10k/rx_176_191_vec.c', + 'rx/cn10k/rx_192_207_vec.c', + 'rx/cn10k/rx_208_223_vec.c', + 'rx/cn10k/rx_224_239_vec.c', + 'rx/cn10k/rx_240_255_vec.c', 'rx/cn10k/rx_0_15_vec_mseg.c', 'rx/cn10k/rx_16_31_vec_mseg.c', 'rx/cn10k/rx_32_47_vec_mseg.c', @@ -144,6 +168,14 @@ sources += files( 'rx/cn10k/rx_80_95_vec_mseg.c', 'rx/cn10k/rx_96_111_vec_mseg.c', 'rx/cn10k/rx_112_127_vec_mseg.c', + 'rx/cn10k/rx_128_143_vec_mseg.c', + 'rx/cn10k/rx_144_159_vec_mseg.c', + 'rx/cn10k/rx_160_175_vec_mseg.c', + 'rx/cn10k/rx_176_191_vec_mseg.c', + 'rx/cn10k/rx_192_207_vec_mseg.c', + 'rx/cn10k/rx_208_223_vec_mseg.c', + 'rx/cn10k/rx_224_239_vec_mseg.c', + 'rx/cn10k/rx_240_255_vec_mseg.c', ) sources += files( diff --git a/drivers/net/cnxk/rx/cn10k/rx_128_143.c b/drivers/net/cnxk/rx/cn10k/rx_128_143.c new file mode 100644 index 0000000000..8c33b5b383 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_128_143.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV(cn10k_nix_recv_pkts_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_128_143_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_128_143_mseg.c new file mode 100644 index 0000000000..172fa190dd --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_128_143_mseg.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_MSEG(cn10k_nix_recv_pkts_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_128_143_vec.c b/drivers/net/cnxk/rx/cn10k/rx_128_143_vec.c new file mode 100644 index 0000000000..fa0182ee3c --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_128_143_vec.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_VEC(cn10k_nix_recv_pkts_vec_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_128_143_vec_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_128_143_vec_mseg.c new file mode 100644 index 0000000000..620d6817ed --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_128_143_vec_mseg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) \ + NIX_RX_RECV_VEC_MSEG(cn10k_nix_recv_pkts_vec_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_128_143 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_144_159.c b/drivers/net/cnxk/rx/cn10k/rx_144_159.c new file mode 100644 index 0000000000..4f5bf2be77 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_144_159.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV(cn10k_nix_recv_pkts_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_144_159_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_144_159_mseg.c new file mode 100644 index 0000000000..acc2adbd2a --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_144_159_mseg.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_MSEG(cn10k_nix_recv_pkts_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_144_159_vec.c b/drivers/net/cnxk/rx/cn10k/rx_144_159_vec.c new file mode 100644 index 0000000000..cfb8ca424e --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_144_159_vec.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_VEC(cn10k_nix_recv_pkts_vec_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_144_159_vec_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_144_159_vec_mseg.c new file mode 100644 index 0000000000..68acf2f169 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_144_159_vec_mseg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) \ + NIX_RX_RECV_VEC_MSEG(cn10k_nix_recv_pkts_vec_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_144_159 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_160_175.c b/drivers/net/cnxk/rx/cn10k/rx_160_175.c new file mode 100644 index 0000000000..e14e730453 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_160_175.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV(cn10k_nix_recv_pkts_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_160_175_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_160_175_mseg.c new file mode 100644 index 0000000000..fb0a551278 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_160_175_mseg.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_MSEG(cn10k_nix_recv_pkts_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_160_175_vec.c b/drivers/net/cnxk/rx/cn10k/rx_160_175_vec.c new file mode 100644 index 0000000000..eae8fb977a --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_160_175_vec.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_VEC(cn10k_nix_recv_pkts_vec_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_160_175_vec_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_160_175_vec_mseg.c new file mode 100644 index 0000000000..89faf62fdc --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_160_175_vec_mseg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) \ + NIX_RX_RECV_VEC_MSEG(cn10k_nix_recv_pkts_vec_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_160_175 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_176_191.c b/drivers/net/cnxk/rx/cn10k/rx_176_191.c new file mode 100644 index 0000000000..0d25f35913 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_176_191.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV(cn10k_nix_recv_pkts_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_176_191_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_176_191_mseg.c new file mode 100644 index 0000000000..dd67fefcbb --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_176_191_mseg.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_MSEG(cn10k_nix_recv_pkts_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_176_191_vec.c b/drivers/net/cnxk/rx/cn10k/rx_176_191_vec.c new file mode 100644 index 0000000000..a86ef5d24c --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_176_191_vec.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_VEC(cn10k_nix_recv_pkts_vec_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_176_191_vec_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_176_191_vec_mseg.c new file mode 100644 index 0000000000..c07a2ba7ce --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_176_191_vec_mseg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) \ + NIX_RX_RECV_VEC_MSEG(cn10k_nix_recv_pkts_vec_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_176_191 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_192_207.c b/drivers/net/cnxk/rx/cn10k/rx_192_207.c new file mode 100644 index 0000000000..45da8e9997 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_192_207.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV(cn10k_nix_recv_pkts_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_192_207_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_192_207_mseg.c new file mode 100644 index 0000000000..869be355f9 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_192_207_mseg.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_MSEG(cn10k_nix_recv_pkts_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_192_207_vec.c b/drivers/net/cnxk/rx/cn10k/rx_192_207_vec.c new file mode 100644 index 0000000000..3d214158ec --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_192_207_vec.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_VEC(cn10k_nix_recv_pkts_vec_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_192_207_vec_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_192_207_vec_mseg.c new file mode 100644 index 0000000000..762e9f5512 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_192_207_vec_mseg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) \ + NIX_RX_RECV_VEC_MSEG(cn10k_nix_recv_pkts_vec_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_192_207 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_208_223.c b/drivers/net/cnxk/rx/cn10k/rx_208_223.c new file mode 100644 index 0000000000..ca64ab5fde --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_208_223.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV(cn10k_nix_recv_pkts_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_208_223_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_208_223_mseg.c new file mode 100644 index 0000000000..35e443a06e --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_208_223_mseg.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_MSEG(cn10k_nix_recv_pkts_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_208_223_vec.c b/drivers/net/cnxk/rx/cn10k/rx_208_223_vec.c new file mode 100644 index 0000000000..b7f9feece2 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_208_223_vec.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_VEC(cn10k_nix_recv_pkts_vec_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_208_223_vec_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_208_223_vec_mseg.c new file mode 100644 index 0000000000..b3da6ec11e --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_208_223_vec_mseg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) \ + NIX_RX_RECV_VEC_MSEG(cn10k_nix_recv_pkts_vec_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_208_223 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_224_239.c b/drivers/net/cnxk/rx/cn10k/rx_224_239.c new file mode 100644 index 0000000000..bd288f3330 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_224_239.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV(cn10k_nix_recv_pkts_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_224_239_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_224_239_mseg.c new file mode 100644 index 0000000000..bf5af065df --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_224_239_mseg.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_MSEG(cn10k_nix_recv_pkts_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_224_239_vec.c b/drivers/net/cnxk/rx/cn10k/rx_224_239_vec.c new file mode 100644 index 0000000000..c05bb99414 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_224_239_vec.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_VEC(cn10k_nix_recv_pkts_vec_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_224_239_vec_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_224_239_vec_mseg.c new file mode 100644 index 0000000000..5f7f8efdae --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_224_239_vec_mseg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) \ + NIX_RX_RECV_VEC_MSEG(cn10k_nix_recv_pkts_vec_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_224_239 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_240_255.c b/drivers/net/cnxk/rx/cn10k/rx_240_255.c new file mode 100644 index 0000000000..d72b2eec1c --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_240_255.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV(cn10k_nix_recv_pkts_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_240_255_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_240_255_mseg.c new file mode 100644 index 0000000000..f248ad8c77 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_240_255_mseg.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_MSEG(cn10k_nix_recv_pkts_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_240_255_vec.c b/drivers/net/cnxk/rx/cn10k/rx_240_255_vec.c new file mode 100644 index 0000000000..7e81ed1883 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_240_255_vec.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) NIX_RX_RECV_VEC(cn10k_nix_recv_pkts_vec_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R diff --git a/drivers/net/cnxk/rx/cn10k/rx_240_255_vec_mseg.c b/drivers/net/cnxk/rx/cn10k/rx_240_255_vec_mseg.c new file mode 100644 index 0000000000..db8aeca013 --- /dev/null +++ b/drivers/net/cnxk/rx/cn10k/rx_240_255_vec_mseg.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include "cn10k_rx.h" + +#define R(name, flags) \ + NIX_RX_RECV_VEC_MSEG(cn10k_nix_recv_pkts_vec_mseg_##name, flags) + +NIX_RX_FASTPATH_MODES_240_255 +#undef R From patchwork Thu Jan 20 16:53:09 2022 Content-Type: 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DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 20 Jan 2022 08:53:32 -0800 Received: from localhost.localdomain (unknown [10.28.48.55]) by maili.marvell.com (Postfix) with ESMTP id A78C13F7048; Thu, 20 Jan 2022 08:53:28 -0800 (PST) From: Akhil Goyal To: CC: , , , , , , , , , Nithin Dabilpuram Subject: [PATCH v2 3/4] net/cnxk: add dev args for min-max spi Date: Thu, 20 Jan 2022 22:23:09 +0530 Message-ID: <20220120165310.4165567-4-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120165310.4165567-1-gakhil@marvell.com> References: <20220103160149.1715058-1-gakhil@marvell.com> <20220120165310.4165567-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 06bomUdx_kioHDUmrBqcKeOzxa85AoN8 X-Proofpoint-GUID: 06bomUdx_kioHDUmrBqcKeOzxa85AoN8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-20_06,2022-01-20_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Nithin Dabilpuram Add support for inline inbound SPI range via devargs instead of just max SPI value and range being 0..max. Signed-off-by: Nithin Dabilpuram --- doc/guides/nics/cnxk.rst | 28 ++++++++++- drivers/common/cnxk/roc_nix.h | 5 +- drivers/common/cnxk/roc_nix_inl.c | 65 +++++++++++++++----------- drivers/common/cnxk/roc_nix_inl.h | 8 ++-- drivers/common/cnxk/roc_nix_inl_dev.c | 22 ++++++--- drivers/common/cnxk/roc_nix_inl_priv.h | 4 +- drivers/common/cnxk/roc_nix_priv.h | 1 + drivers/common/cnxk/version.map | 2 +- drivers/net/cnxk/cn10k_ethdev_sec.c | 13 ++++-- drivers/net/cnxk/cn9k_ethdev_sec.c | 10 ++-- drivers/net/cnxk/cnxk_ethdev_devargs.c | 25 +++++++--- drivers/net/cnxk/cnxk_ethdev_sec.c | 16 +++++-- drivers/net/cnxk/cnxk_lookup.c | 3 +- 13 files changed, 141 insertions(+), 61 deletions(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index 2119ba51c8..e90a7d166b 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -187,6 +187,18 @@ Runtime Config Options -a 0002:02:00.0,tag_as_xor=1 +- ``Min SPI for inbound inline IPsec`` (default ``0``) + + Min SPI supported for inbound inline IPsec processing can be specified by + ``ipsec_in_min_spi`` ``devargs`` parameter. + + For example:: + + -a 0002:02:00.0,ipsec_in_min_spi=6 + + With the above configuration, application can enable inline IPsec processing + for inbound SA with min SPI of 6. + - ``Max SPI for inbound inline IPsec`` (default ``255``) Max SPI supported for inbound inline IPsec processing can be specified by @@ -197,7 +209,7 @@ Runtime Config Options -a 0002:02:00.0,ipsec_in_max_spi=128 With the above configuration, application can enable inline IPsec processing - for 128 inbound SAs (SPI 0-127). + with max SPI of 128. - ``Max SA's for outbound inline IPsec`` (default ``4096``) @@ -365,6 +377,18 @@ VF ``177D:A0F1``. Runtime Config Options for inline device ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +- ``Min SPI for inbound inline IPsec`` (default ``0``) + + Min SPI supported for inbound inline IPsec processing can be specified by + ``ipsec_in_min_spi`` ``devargs`` parameter. + + For example:: + + -a 0002:1d:00.0,ipsec_in_min_spi=6 + + With the above configuration, application can enable inline IPsec processing + for inbound SA with min SPI of 6 for traffic aggregated on inline device. + - ``Max SPI for inbound inline IPsec`` (default ``255``) Max SPI supported for inbound inline IPsec processing can be specified by @@ -375,7 +399,7 @@ Runtime Config Options for inline device -a 0002:1d:00.0,ipsec_in_max_spi=128 With the above configuration, application can enable inline IPsec processing - for 128 inbound SAs (SPI 0-127) for traffic aggregated on inline device. + for inbound SA with max SPI of 128 for traffic aggregated on inline device. Debugging Options diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 69a5e8e7b4..ae42690470 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -380,8 +380,9 @@ struct roc_nix { uint8_t lock_rx_ctx; uint32_t outb_nb_desc; uint16_t outb_nb_crypto_qs; - uint16_t ipsec_in_max_spi; - uint16_t ipsec_out_max_sa; + uint32_t ipsec_in_min_spi; + uint32_t ipsec_in_max_spi; + uint32_t ipsec_out_max_sa; /* End of input parameters */ /* LMT line base for "Per Core Tx LMT line" mode*/ uintptr_t lmt_base; diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 5251b51f9e..849473063f 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -19,12 +19,16 @@ PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ == static int nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix) { - uint16_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi; + uint32_t ipsec_in_min_spi = roc_nix->ipsec_in_min_spi; + uint32_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi; struct nix *nix = roc_nix_to_nix_priv(roc_nix); struct roc_nix_ipsec_cfg cfg; + uint64_t max_sa, i; size_t inb_sa_sz; - int rc, i; void *sa; + int rc; + + max_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1); /* CN9K SA size is different */ if (roc_model_is_cn9k()) @@ -34,14 +38,15 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix) /* Alloc contiguous memory for Inbound SA's */ nix->inb_sa_sz = inb_sa_sz; - nix->inb_sa_base = plt_zmalloc(inb_sa_sz * ipsec_in_max_spi, + nix->inb_spi_mask = max_sa - 1; + nix->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa, ROC_NIX_INL_SA_BASE_ALIGN); if (!nix->inb_sa_base) { plt_err("Failed to allocate memory for Inbound SA"); return -ENOMEM; } if (roc_model_is_cn10k()) { - for (i = 0; i < ipsec_in_max_spi; i++) { + for (i = 0; i < max_sa; i++) { sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz); roc_nix_inl_inb_sa_init(sa); } @@ -50,7 +55,7 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix) memset(&cfg, 0, sizeof(cfg)); cfg.sa_size = inb_sa_sz; cfg.iova = (uintptr_t)nix->inb_sa_base; - cfg.max_sa = ipsec_in_max_spi + 1; + cfg.max_sa = max_sa; cfg.tt = SSO_TT_ORDERED; /* Setup device specific inb SA table */ @@ -129,26 +134,34 @@ roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev) } uint32_t -roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev) +roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix, bool inb_inl_dev, + uint32_t *min_spi, uint32_t *max_spi) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); struct idev_cfg *idev = idev_get_cfg(); + uint32_t min = 0, max = 0, mask = 0; struct nix_inl_dev *inl_dev; - if (idev == NULL) - return 0; - - if (!nix->inl_inb_ena) - return 0; + if (idev == NULL || !nix->inl_inb_ena) + goto exit; inl_dev = idev->nix_inl_dev; - if (inb_inl_dev) { - if (inl_dev) - return inl_dev->ipsec_in_max_spi; - return 0; + if (inb_inl_dev && inl_dev) { + min = inl_dev->ipsec_in_min_spi; + max = inl_dev->ipsec_in_max_spi; + mask = inl_dev->inb_spi_mask; + } else if (!inb_inl_dev) { + min = roc_nix->ipsec_in_min_spi; + max = roc_nix->ipsec_in_max_spi; + mask = nix->inb_spi_mask; } - return roc_nix->ipsec_in_max_spi; +exit: + if (min_spi) + *min_spi = min; + if (max_spi) + *max_spi = max; + return mask; } uint32_t @@ -175,8 +188,8 @@ roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool inl_dev_sa) uintptr_t roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi) { + uint32_t max_spi, min_spi, mask; uintptr_t sa_base; - uint32_t max_spi; uint64_t sz; sa_base = roc_nix_inl_inb_sa_base_get(roc_nix, inb_inl_dev); @@ -185,11 +198,11 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi) return 0; /* Check if SPI is in range */ - max_spi = roc_nix_inl_inb_sa_max_spi(roc_nix, inb_inl_dev); - if (spi > max_spi) { - plt_err("Inbound SA SPI %u exceeds max %u", spi, max_spi); - return 0; - } + mask = roc_nix_inl_inb_spi_range(roc_nix, inb_inl_dev, &min_spi, + &max_spi); + if (spi > max_spi || spi < min_spi) + plt_warn("Inbound SA SPI %u not in range (%u..%u)", spi, + min_spi, max_spi); /* Get SA size */ sz = roc_nix_inl_inb_sa_sz(roc_nix, inb_inl_dev); @@ -197,7 +210,7 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi) return 0; /* Basic logic of SPI->SA for now */ - return (sa_base + (spi * sz)); + return (sa_base + ((spi & mask) * sz)); } int @@ -300,11 +313,11 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix) struct nix_inl_dev *inl_dev; uint16_t sso_pffunc; uint8_t eng_grpmask; - uint64_t blkaddr; + uint64_t blkaddr, i; uint16_t nb_lf; void *sa_base; size_t sa_sz; - int i, j, rc; + int j, rc; void *sa; if (idev == NULL) @@ -745,7 +758,7 @@ roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix, uint32_t tag_const, memset(&cfg, 0, sizeof(cfg)); cfg.sa_size = nix->inb_sa_sz; cfg.iova = (uintptr_t)nix->inb_sa_base; - cfg.max_sa = roc_nix->ipsec_in_max_spi + 1; + cfg.max_sa = nix->inb_spi_mask + 1; cfg.tt = tt; cfg.tag_const = tag_const; diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 73a17276c4..280ea7cb80 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -110,7 +110,8 @@ typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args); struct roc_nix_inl_dev { /* Input parameters */ struct plt_pci_device *pci_dev; - uint16_t ipsec_in_max_spi; + uint32_t ipsec_in_min_spi; + uint32_t ipsec_in_max_spi; bool selftest; bool is_multi_channel; uint16_t channel; @@ -138,8 +139,9 @@ int __roc_api roc_nix_inl_inb_fini(struct roc_nix *roc_nix); bool __roc_api roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix); uintptr_t __roc_api roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inl_dev_sa); -uint32_t __roc_api roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, - bool inl_dev_sa); +uint32_t __roc_api roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix, + bool inl_dev_sa, uint32_t *min, + uint32_t *max); uint32_t __roc_api roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool inl_dev_sa); uintptr_t __roc_api roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index a0fe6ecd82..f75d14ba8b 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -114,6 +114,7 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena) { struct nix_inline_ipsec_lf_cfg *lf_cfg; struct mbox *mbox = (&inl_dev->dev)->mbox; + uint64_t max_sa; uint32_t sa_w; lf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_cfg(mbox); @@ -121,8 +122,9 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena) return -ENOSPC; if (ena) { - sa_w = plt_align32pow2(inl_dev->ipsec_in_max_spi + 1); - sa_w = plt_log2_u32(sa_w); + + max_sa = inl_dev->inb_spi_mask + 1; + sa_w = plt_log2_u32(max_sa); lf_cfg->enable = 1; lf_cfg->sa_base_addr = (uintptr_t)inl_dev->inb_sa_base; @@ -132,7 +134,7 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena) lf_cfg->ipsec_cfg0.lenm1_max = NIX_CN9K_MAX_HW_FRS - 1; else lf_cfg->ipsec_cfg0.lenm1_max = NIX_RPM_MAX_HW_FRS - 1; - lf_cfg->ipsec_cfg1.sa_idx_max = inl_dev->ipsec_in_max_spi; + lf_cfg->ipsec_cfg1.sa_idx_max = max_sa - 1; lf_cfg->ipsec_cfg0.sa_pow2_size = plt_log2_u32(inl_dev->inb_sa_sz); @@ -341,15 +343,19 @@ nix_inl_sso_release(struct nix_inl_dev *inl_dev) static int nix_inl_nix_setup(struct nix_inl_dev *inl_dev) { - uint16_t ipsec_in_max_spi = inl_dev->ipsec_in_max_spi; + uint32_t ipsec_in_min_spi = inl_dev->ipsec_in_min_spi; + uint32_t ipsec_in_max_spi = inl_dev->ipsec_in_max_spi; struct dev *dev = &inl_dev->dev; struct mbox *mbox = dev->mbox; struct nix_lf_alloc_rsp *rsp; struct nix_lf_alloc_req *req; + uint64_t max_sa, i; size_t inb_sa_sz; - int i, rc = -ENOSPC; + int rc = -ENOSPC; void *sa; + max_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1); + /* Alloc NIX LF needed for single RQ */ req = mbox_alloc_msg_nix_lf_alloc(mbox); if (req == NULL) @@ -397,7 +403,8 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev) /* Alloc contiguous memory for Inbound SA's */ inl_dev->inb_sa_sz = inb_sa_sz; - inl_dev->inb_sa_base = plt_zmalloc(inb_sa_sz * ipsec_in_max_spi, + inl_dev->inb_spi_mask = max_sa - 1; + inl_dev->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa, ROC_NIX_INL_SA_BASE_ALIGN); if (!inl_dev->inb_sa_base) { plt_err("Failed to allocate memory for Inbound SA"); @@ -406,7 +413,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev) } if (roc_model_is_cn10k()) { - for (i = 0; i < ipsec_in_max_spi; i++) { + for (i = 0; i < max_sa; i++) { sa = ((uint8_t *)inl_dev->inb_sa_base) + (i * inb_sa_sz); roc_nix_inl_inb_sa_init(sa); @@ -562,6 +569,7 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev) memset(inl_dev, 0, sizeof(*inl_dev)); inl_dev->pci_dev = pci_dev; + inl_dev->ipsec_in_min_spi = roc_inl_dev->ipsec_in_min_spi; inl_dev->ipsec_in_max_spi = roc_inl_dev->ipsec_in_max_spi; inl_dev->selftest = roc_inl_dev->selftest; inl_dev->is_multi_channel = roc_inl_dev->is_multi_channel; diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h index 3dc526f929..71bfd50c75 100644 --- a/drivers/common/cnxk/roc_nix_inl_priv.h +++ b/drivers/common/cnxk/roc_nix_inl_priv.h @@ -53,7 +53,9 @@ struct nix_inl_dev { uint16_t channel; uint16_t chan_mask; bool is_multi_channel; - uint16_t ipsec_in_max_spi; + uint32_t ipsec_in_min_spi; + uint32_t ipsec_in_max_spi; + uint32_t inb_spi_mask; bool attach_cptlf; }; diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 04575af295..4bd69cbec5 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -173,6 +173,7 @@ struct nix { bool inl_outb_ena; void *inb_sa_base; size_t inb_sa_sz; + uint32_t inb_spi_mask; void *outb_sa_base; size_t outb_sa_sz; uint16_t outb_err_sso_pffunc; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index eab6e6a432..26ea18527d 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -140,7 +140,7 @@ INTERNAL { roc_nix_inl_inb_init; roc_nix_inl_inb_sa_base_get; roc_nix_inl_inb_sa_get; - roc_nix_inl_inb_sa_max_spi; + roc_nix_inl_inb_spi_range; roc_nix_inl_inb_sa_sz; roc_nix_inl_inb_tag_update; roc_nix_inl_inb_fini; diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index c332d59012..59c7befb8e 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -237,6 +237,7 @@ cn10k_eth_sec_session_create(void *device, struct cn10k_sec_sess_priv sess_priv; struct rte_crypto_sym_xform *crypto; struct cnxk_eth_sec_sess *eth_sec; + struct roc_nix *nix = &dev->nix; bool inbound, inl_dev; int rc = 0; @@ -287,13 +288,16 @@ cn10k_eth_sec_session_create(void *device, if (inbound) { struct roc_ot_ipsec_inb_sa *inb_sa, *inb_sa_dptr; struct cn10k_inb_priv_data *inb_priv; + uint32_t spi_mask; uintptr_t sa; PLT_STATIC_ASSERT(sizeof(struct cn10k_inb_priv_data) < ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD); + spi_mask = roc_nix_inl_inb_spi_range(nix, inl_dev, NULL, NULL); + /* Get Inbound SA from NIX_RX_IPSEC_SA_BASE */ - sa = roc_nix_inl_inb_sa_get(&dev->nix, inl_dev, ipsec->spi); + sa = roc_nix_inl_inb_sa_get(nix, inl_dev, ipsec->spi); if (!sa && dev->inb.inl_dev) { plt_err("Failed to create ingress sa, inline dev " "not found or spi not in range"); @@ -332,16 +336,17 @@ cn10k_eth_sec_session_create(void *device, inb_priv->userdata = conf->userdata; /* Save SA index/SPI in cookie for now */ - inb_sa_dptr->w1.s.cookie = rte_cpu_to_be_32(ipsec->spi); + inb_sa_dptr->w1.s.cookie = + rte_cpu_to_be_32(ipsec->spi & spi_mask); /* Prepare session priv */ sess_priv.inb_sa = 1; - sess_priv.sa_idx = ipsec->spi; + sess_priv.sa_idx = ipsec->spi & spi_mask; /* Pointer from eth_sec -> inb_sa */ eth_sec->sa = inb_sa; eth_sec->sess = sess; - eth_sec->sa_idx = ipsec->spi; + eth_sec->sa_idx = ipsec->spi & spi_mask; eth_sec->spi = ipsec->spi; eth_sec->inl_dev = !!dev->inb.inl_dev; eth_sec->inb = true; diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c b/drivers/net/cnxk/cn9k_ethdev_sec.c index b070ad57fc..cf0431184a 100644 --- a/drivers/net/cnxk/cn9k_ethdev_sec.c +++ b/drivers/net/cnxk/cn9k_ethdev_sec.c @@ -146,6 +146,7 @@ cn9k_eth_sec_session_create(void *device, struct cn9k_sec_sess_priv sess_priv; struct rte_crypto_sym_xform *crypto; struct cnxk_eth_sec_sess *eth_sec; + struct roc_nix *nix = &dev->nix; bool inbound; int rc = 0; @@ -180,15 +181,18 @@ cn9k_eth_sec_session_create(void *device, if (inbound) { struct cn9k_inb_priv_data *inb_priv; struct roc_onf_ipsec_inb_sa *inb_sa; + uint32_t spi_mask; PLT_STATIC_ASSERT(sizeof(struct cn9k_inb_priv_data) < ROC_NIX_INL_ONF_IPSEC_INB_SW_RSVD); + spi_mask = roc_nix_inl_inb_spi_range(nix, false, NULL, NULL); + /* Get Inbound SA from NIX_RX_IPSEC_SA_BASE. Assume no inline * device always for CN9K. */ inb_sa = (struct roc_onf_ipsec_inb_sa *) - roc_nix_inl_inb_sa_get(&dev->nix, false, ipsec->spi); + roc_nix_inl_inb_sa_get(nix, false, ipsec->spi); if (!inb_sa) { plt_err("Failed to create ingress sa"); rc = -EFAULT; @@ -228,12 +232,12 @@ cn9k_eth_sec_session_create(void *device, /* Prepare session priv */ sess_priv.inb_sa = 1; - sess_priv.sa_idx = ipsec->spi; + sess_priv.sa_idx = ipsec->spi & spi_mask; /* Pointer from eth_sec -> inb_sa */ eth_sec->sa = inb_sa; eth_sec->sess = sess; - eth_sec->sa_idx = ipsec->spi; + eth_sec->sa_idx = ipsec->spi & spi_mask; eth_sec->spi = ipsec->spi; eth_sec->inb = true; diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c index e068f55349..2923d2b18b 100644 --- a/drivers/net/cnxk/cnxk_ethdev_devargs.c +++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c @@ -37,14 +37,17 @@ parse_outb_nb_crypto_qs(const char *key, const char *value, void *extra_args) } static int -parse_ipsec_in_max_spi(const char *key, const char *value, void *extra_args) +parse_ipsec_in_spi_range(const char *key, const char *value, void *extra_args) { RTE_SET_USED(key); uint32_t val; - val = atoi(value); + errno = 0; + val = strtoul(value, NULL, 0); + if (errno) + val = 0; - *(uint16_t *)extra_args = val; + *(uint32_t *)extra_args = val; return 0; } @@ -55,7 +58,10 @@ parse_ipsec_out_max_sa(const char *key, const char *value, void *extra_args) RTE_SET_USED(key); uint32_t val; - val = atoi(value); + errno = 0; + val = strtoul(value, NULL, 0); + if (errno) + val = 0; *(uint16_t *)extra_args = val; @@ -172,6 +178,7 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args) #define CNXK_SWITCH_HEADER_TYPE "switch_header" #define CNXK_RSS_TAG_AS_XOR "tag_as_xor" #define CNXK_LOCK_RX_CTX "lock_rx_ctx" +#define CNXK_IPSEC_IN_MIN_SPI "ipsec_in_min_spi" #define CNXK_IPSEC_IN_MAX_SPI "ipsec_in_max_spi" #define CNXK_IPSEC_OUT_MAX_SA "ipsec_out_max_sa" #define CNXK_OUTB_NB_DESC "outb_nb_desc" @@ -183,13 +190,14 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) { uint16_t reta_sz = ROC_NIX_RSS_RETA_SZ_64; uint16_t sqb_count = CNXK_NIX_TX_MAX_SQB; - uint16_t ipsec_in_max_spi = BIT(8) - 1; - uint16_t ipsec_out_max_sa = BIT(12); + uint32_t ipsec_in_max_spi = BIT(8) - 1; + uint32_t ipsec_out_max_sa = BIT(12); uint16_t flow_prealloc_size = 1; uint16_t switch_header_type = 0; uint16_t flow_max_priority = 3; uint16_t force_inb_inl_dev = 0; uint16_t outb_nb_crypto_qs = 1; + uint32_t ipsec_in_min_spi = 0; uint16_t outb_nb_desc = 8200; uint16_t rss_tag_as_xor = 0; uint16_t scalar_enable = 0; @@ -218,8 +226,10 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) rte_kvargs_process(kvlist, CNXK_RSS_TAG_AS_XOR, &parse_flag, &rss_tag_as_xor); rte_kvargs_process(kvlist, CNXK_LOCK_RX_CTX, &parse_flag, &lock_rx_ctx); + rte_kvargs_process(kvlist, CNXK_IPSEC_IN_MIN_SPI, + &parse_ipsec_in_spi_range, &ipsec_in_min_spi); rte_kvargs_process(kvlist, CNXK_IPSEC_IN_MAX_SPI, - &parse_ipsec_in_max_spi, &ipsec_in_max_spi); + &parse_ipsec_in_spi_range, &ipsec_in_max_spi); rte_kvargs_process(kvlist, CNXK_IPSEC_OUT_MAX_SA, &parse_ipsec_out_max_sa, &ipsec_out_max_sa); rte_kvargs_process(kvlist, CNXK_OUTB_NB_DESC, &parse_outb_nb_desc, @@ -237,6 +247,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) dev->outb.max_sa = ipsec_out_max_sa; dev->outb.nb_desc = outb_nb_desc; dev->outb.nb_crypto_qs = outb_nb_crypto_qs; + dev->nix.ipsec_in_min_spi = ipsec_in_min_spi; dev->nix.ipsec_in_max_spi = ipsec_in_max_spi; dev->nix.ipsec_out_max_sa = ipsec_out_max_sa; dev->nix.rss_tag_as_xor = !!rss_tag_as_xor; diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index 3fef0562ea..a20203501a 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -5,6 +5,7 @@ #include #define CNXK_NIX_INL_SELFTEST "selftest" +#define CNXK_NIX_INL_IPSEC_IN_MIN_SPI "ipsec_in_min_spi" #define CNXK_NIX_INL_IPSEC_IN_MAX_SPI "ipsec_in_max_spi" #define CNXK_INL_CPT_CHANNEL "inl_cpt_channel" @@ -119,14 +120,17 @@ struct rte_security_ops cnxk_eth_sec_ops = { }; static int -parse_ipsec_in_max_spi(const char *key, const char *value, void *extra_args) +parse_ipsec_in_spi_range(const char *key, const char *value, void *extra_args) { RTE_SET_USED(key); uint32_t val; - val = atoi(value); + errno = 0; + val = strtoul(value, NULL, 0); + if (errno) + val = 0; - *(uint16_t *)extra_args = val; + *(uint32_t *)extra_args = val; return 0; } @@ -169,6 +173,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, struct roc_nix_inl_dev *inl_dev) { uint32_t ipsec_in_max_spi = BIT(8) - 1; + uint32_t ipsec_in_min_spi = 0; struct inl_cpt_channel cpt_channel; struct rte_kvargs *kvlist; uint8_t selftest = 0; @@ -184,13 +189,16 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, rte_kvargs_process(kvlist, CNXK_NIX_INL_SELFTEST, &parse_selftest, &selftest); + rte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MIN_SPI, + &parse_ipsec_in_spi_range, &ipsec_in_min_spi); rte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MAX_SPI, - &parse_ipsec_in_max_spi, &ipsec_in_max_spi); + &parse_ipsec_in_spi_range, &ipsec_in_max_spi); rte_kvargs_process(kvlist, CNXK_INL_CPT_CHANNEL, &parse_inl_cpt_channel, &cpt_channel); rte_kvargs_free(kvlist); null_devargs: + inl_dev->ipsec_in_min_spi = ipsec_in_min_spi; inl_dev->ipsec_in_max_spi = ipsec_in_max_spi; inl_dev->selftest = selftest; inl_dev->channel = cpt_channel.channel; diff --git a/drivers/net/cnxk/cnxk_lookup.c b/drivers/net/cnxk/cnxk_lookup.c index 4eb1ecf17d..f36fb8f27a 100644 --- a/drivers/net/cnxk/cnxk_lookup.c +++ b/drivers/net/cnxk/cnxk_lookup.c @@ -337,7 +337,8 @@ cnxk_nix_lookup_mem_sa_base_set(struct cnxk_eth_dev *dev) if (!sa_base) return -ENOTSUP; - sa_w = plt_log2_u32(dev->nix.ipsec_in_max_spi + 1); + sa_w = plt_log2_u32(dev->nix.ipsec_in_max_spi + 1 - + dev->nix.ipsec_in_min_spi); /* Set SA Base in lookup mem */ sa_base_tbl = (uintptr_t)lookup_mem; From patchwork Thu Jan 20 16:53:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 106147 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EF006A034E; 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Thu, 20 Jan 2022 08:53:37 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 20 Jan 2022 08:53:36 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 20 Jan 2022 08:53:36 -0800 Received: from localhost.localdomain (unknown [10.28.48.55]) by maili.marvell.com (Postfix) with ESMTP id B61813F704A; Thu, 20 Jan 2022 08:53:32 -0800 (PST) From: Akhil Goyal To: CC: , , , , , , , , , Nithin Dabilpuram Subject: [PATCH v2 4/4] net/cnxk: add option to override outbound inline sa iv Date: Thu, 20 Jan 2022 22:23:10 +0530 Message-ID: <20220120165310.4165567-5-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120165310.4165567-1-gakhil@marvell.com> References: <20220103160149.1715058-1-gakhil@marvell.com> <20220120165310.4165567-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: i1qsKCk9Nq7A5XeL0cugftsQqWxRljmD X-Proofpoint-ORIG-GUID: i1qsKCk9Nq7A5XeL0cugftsQqWxRljmD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-20_06,2022-01-20_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Nithin Dabilpuram Add option to override outbound inline sa iv for debug purposes via environment variable. User can set env variable as: export CN10K_ETH_SEC_IV_OVR="0x0, 0x0,..." Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_ethdev_sec.c | 62 +++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 59c7befb8e..a8788195f4 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -225,6 +225,63 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args) rte_pktmbuf_free(mbuf); } +static void +outb_dbg_iv_update(struct roc_ot_ipsec_outb_sa *outb_sa, const char *__iv_str) +{ + uint8_t *iv_dbg = outb_sa->iv.iv_dbg; + char *iv_str = strdup(__iv_str); + char *iv_b = NULL, len = 16; + char *save; + int i; + + if (!iv_str) + return; + + if (outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_GCM || + outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_CTR || + outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_CCM || + outb_sa->w2.s.auth_type == ROC_IE_OT_SA_AUTH_AES_GMAC) { + memset(outb_sa->iv.s.iv_dbg1, 0, sizeof(outb_sa->iv.s.iv_dbg1)); + memset(outb_sa->iv.s.iv_dbg2, 0, sizeof(outb_sa->iv.s.iv_dbg2)); + + iv_dbg = outb_sa->iv.s.iv_dbg1; + for (i = 0; i < 4; i++) { + iv_b = strtok_r(i ? NULL : iv_str, ",", &save); + if (!iv_b) + break; + iv_dbg[i] = strtoul(iv_b, NULL, 0); + } + *(uint32_t *)iv_dbg = rte_be_to_cpu_32(*(uint32_t *)iv_dbg); + + iv_dbg = outb_sa->iv.s.iv_dbg2; + for (i = 0; i < 4; i++) { + iv_b = strtok_r(NULL, ",", &save); + if (!iv_b) + break; + iv_dbg[i] = strtoul(iv_b, NULL, 0); + } + *(uint32_t *)iv_dbg = rte_be_to_cpu_32(*(uint32_t *)iv_dbg); + + } else { + iv_dbg = outb_sa->iv.iv_dbg; + memset(iv_dbg, 0, sizeof(outb_sa->iv.iv_dbg)); + + for (i = 0; i < len; i++) { + iv_b = strtok_r(i ? NULL : iv_str, ",", &save); + if (!iv_b) + break; + iv_dbg[i] = strtoul(iv_b, NULL, 0); + } + *(uint64_t *)iv_dbg = rte_be_to_cpu_64(*(uint64_t *)iv_dbg); + *(uint64_t *)&iv_dbg[8] = + rte_be_to_cpu_64(*(uint64_t *)&iv_dbg[8]); + } + + /* Update source of IV */ + outb_sa->w2.s.iv_src = ROC_IE_OT_SA_IV_SRC_FROM_SA; + free(iv_str); +} + static int cn10k_eth_sec_session_create(void *device, struct rte_security_session_conf *conf, @@ -370,6 +427,7 @@ cn10k_eth_sec_session_create(void *device, struct cn10k_outb_priv_data *outb_priv; struct cnxk_ipsec_outb_rlens *rlens; uint64_t sa_base = dev->outb.sa_base; + const char *iv_str; uint32_t sa_idx; PLT_STATIC_ASSERT(sizeof(struct cn10k_outb_priv_data) < @@ -395,6 +453,10 @@ cn10k_eth_sec_session_create(void *device, goto mempool_put; } + iv_str = getenv("CN10K_ETH_SEC_IV_OVR"); + if (iv_str) + outb_dbg_iv_update(outb_sa_dptr, iv_str); + /* Save userdata */ outb_priv->userdata = conf->userdata; outb_priv->sa_idx = sa_idx;