From patchwork Mon Feb 14 09:00:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 107418 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C674DA00C4; Mon, 14 Feb 2022 10:00:26 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B052040C35; Mon, 14 Feb 2022 10:00:26 +0100 (CET) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2050.outbound.protection.outlook.com [40.107.237.50]) by mails.dpdk.org (Postfix) with ESMTP id C40B04067E; Mon, 14 Feb 2022 10:00:24 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=g2yqC88yw0lcq+OMLaMQDbNFTRiBcFVlg7Gt3/BxcJzRdCfE3UcSRY0tsOZTTI3KyvHL7nPn3eO6yAKSbQYq8MPzf+DholMcYSLC2X27ZgR8Upu/2pRLl5ZJYg4QCd2QEHw3V/XkFEEoVS12ntwWlxNjZHOtdsN6E1pM+VsJLSne4tTxVcBeWPFzaWZ9W+g39eNolQgcFPxM6BJ6rDFOvQcgH/4xC52RvPYoXqiFlNiJdqrJf60P87JKypESRL3tknxjkX7Gu9XlLQNS7TZv6qKbmVDJEeB0kt+IGuXhSL2dBKazTKtA2MaQhw7cyfHrY75h+sOzWsDG45gq+xkCaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Uk1ifJqph/20ZlE411bHimiqsX4ih7UI2RFUPpwkuZQ=; b=ECf03PJqX2ph2Rvof6DYks/jSo7t82TJs2KrGSoMXuC8deK/mKSOC8CoXXauPB9ZHZkiNFpL0mGEyKJ2nwkiejXsBqCDo4HB41/r2DYzOgsK/bvi6nPZeMNoQxzkOgMS9FSamF66/2/VOZ4wWzSSwLfa3P8j4C3JhURBBKW3CuSht+IGUD7+L4PA/z3+q0xh4qk+mHvTBtJMeW/C4vz3HbxFzGXIUL0iGNAZReTDieMUYjd86WzjfI/MX1McXkY3S+m/kMOyqr2wNbfvBl09SLJaxX+vLsfinU6w6hcNc537cG25f+mWFHVQHjuU2PFZyEW+yXoaSGoeeEAr8QLyZg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Uk1ifJqph/20ZlE411bHimiqsX4ih7UI2RFUPpwkuZQ=; b=JKYTRF7Cf4x3x04McxoEa08L16QNcCDuaDO7fcQygrhO+oFj0DLNltDt+AT7CvuyKLZUrX1Vk5cSNg+J/ZsUmim7hpw6kv6J0KMuFGhnOE2dU2kz7yIt0qknio+xOHPQQZGmREegBWmlSXleRRQo2AjbhG58MzVNtQSVaNadRhPR4m0nTyjv+JYdfHXr+WI3bQbmpwMstccjG1VVn1esEN/lTDKmDrmGG6LSfBpwDp/h7VY7yBUl/Qyi+9rWwNhHX3Rb8NMXZCMIeYOFYMqRqrDhWVmqdqaQROP7j3xleijFbg90xv6RP9J7mHDn8VtUBBmkerdRcSVx9Q1jo9ZgAw== Received: from MWHPR20CA0020.namprd20.prod.outlook.com (2603:10b6:300:13d::30) by MW4PR12MB5604.namprd12.prod.outlook.com (2603:10b6:303:184::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4975.11; Mon, 14 Feb 2022 09:00:23 +0000 Received: from CO1NAM11FT049.eop-nam11.prod.protection.outlook.com (2603:10b6:300:13d:cafe::52) by MWHPR20CA0020.outlook.office365.com (2603:10b6:300:13d::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4951.19 via Frontend Transport; Mon, 14 Feb 2022 09:00:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by CO1NAM11FT049.mail.protection.outlook.com (10.13.175.50) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4975.11 via Frontend Transport; Mon, 14 Feb 2022 09:00:22 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 14 Feb 2022 09:00:21 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Mon, 14 Feb 2022 01:00:20 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9 via Frontend Transport; Mon, 14 Feb 2022 01:00:19 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Subject: [PATCH 1/2] net/mlx5: fix invalid entry in shared RXQs list Date: Mon, 14 Feb 2022 11:00:09 +0200 Message-ID: <20220214090010.1541746-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220214090010.1541746-1-michaelba@nvidia.com> References: <20220214090010.1541746-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 087511b7-713a-46ac-5f79-08d9ef986f1a X-MS-TrafficTypeDiagnostic: MW4PR12MB5604:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ih+wsjsfxgwT6FIaZc858bFYUUWXx/cpxhtesu86dCZjymd+AYWj5Zb7ke9yojYFU9PSY0HVgWYzUZoSmOZrab2ydIUgkMjM6bbXxxrYYT5CEAP/ydVHt7d2lhxK8HtnlQehJuckkmVUbXg0sIBjHO3yYTjsiBC3sfN9jBHEJZERpLEmlpwoR0bJu529laHbO4OZnC3bc+xPcSRpZHwGEVFY0m9ZiXQ4gyoftZw62KkPEVhNhCj+REpjVMsZhT5PKtis5MZyDsfLzGXEzQN1LwA8wSVHLNZ02D+Wuc+llqFghKgp6pS/ezK57Q1ZgNYAZg/pRX1OaUMkHtX+5Ge+PwikRADe4guX+y7+J7Zc1xkjkWIGXDXRnmR9BINHs6dh8R3JZirR9jw89J7ao0ns+gMCKzQ4LMD8EmNVyc/fkeTcZRipO8hi6VmuTMIK3NBExCfVhwRph0Or1MVcVy+hS2hUIxVgT+r3WrBjGlM2A9cyhU8kBRe+DrNoztDBQI8Q/v+vRKQAZzsN0vtNfQQfnBb+tJNjXhOPfDU3Nz/pzekC2WCrZ87YVsiESKsYCK8RdfosT7CfPM8hwtBWdxgOLXVuN+GOrRd82UczdZkRKZD61LLsqUkwYgFZlxsc29P5WbRHK8xTcdurS4o3/JC9Zjx/z8j92Q1lXEmUQDVTkbsaiytfGLK2sGW/HFd3z8D1CAtj2UmkaLnl/KrLyJca2A== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(47076005)(36860700001)(426003)(83380400001)(508600001)(2906002)(26005)(186003)(6286002)(1076003)(36756003)(81166007)(2616005)(356005)(55016003)(336012)(8936002)(4326008)(70206006)(40460700003)(8676002)(450100002)(7696005)(70586007)(5660300002)(316002)(6666004)(86362001)(82310400004)(54906003)(6916009)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2022 09:00:22.6608 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 087511b7-713a-46ac-5f79-08d9ef986f1a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5604 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The mlx5_rxq_new function creates control structure and if it from shared group, it is inserted into the shared RXQs list. After that, there are some validations which in case they fail, RxQ control object is released. In these cases, invalid pointer to the object still in the list, and access it may cause a crash. Move the list insertion to the end of the function where the RxQ control object is surely valid. Fixes: 09c2555303be ("net/mlx5: support shared Rx queue") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_rxq.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 580d7ae868..fe72cf49d3 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -1719,12 +1719,6 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, return NULL; } LIST_INIT(&tmpl->owners); - if (conf->share_group > 0) { - tmpl->rxq.shared = 1; - tmpl->share_group = conf->share_group; - tmpl->share_qid = conf->share_qid; - LIST_INSERT_HEAD(&priv->sh->shared_rxqs, tmpl, share_entry); - } rxq->ctrl = tmpl; LIST_INSERT_HEAD(&tmpl->owners, rxq, owner_entry); MLX5_ASSERT(n_seg && n_seg <= MLX5_MAX_RXQ_NSEG); @@ -1933,6 +1927,12 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, tmpl->rxq.mprq_bufs = (struct mlx5_mprq_buf *(*)[desc])(*tmpl->rxq.elts + desc_n); tmpl->rxq.idx = idx; + if (conf->share_group > 0) { + tmpl->rxq.shared = 1; + tmpl->share_group = conf->share_group; + tmpl->share_qid = conf->share_qid; + LIST_INSERT_HEAD(&priv->sh->shared_rxqs, tmpl, share_entry); + } LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next); return tmpl; error: From patchwork Mon Feb 14 09:00:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 107420 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 641D0A00C4; Mon, 14 Feb 2022 10:00:39 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DD92A41158; Mon, 14 Feb 2022 10:00:28 +0100 (CET) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2060.outbound.protection.outlook.com [40.107.93.60]) by mails.dpdk.org (Postfix) with ESMTP id 7BFC64067E for ; Mon, 14 Feb 2022 10:00:26 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=eP4o3HNI0wA5TjQENRo0b9QPjNw8/mB0YKNtx7F1iidprJerI/soWioPPcWN7hcOdaZlog1LrofP6PQ2UiKcNu9B2VLD+MhpB6QdObHZvN9h8rPBFvoyva5czo0nWtIKVTnQ52GiFIhjwyeYDarZxh+Obu8YWgx+wBpS2UgWHaB+jp3jPbr2j4bO/feYpYY9fMM523Y6ijL/TLYGODAYyrtq0Is8BzMKo9rKs2V0y/4AJMGcOu0lyeSpgbnANntXJs8C6qzz3nxLpKgYVQyIz6AWDs2Va7fobxKINN3pBRfFJXSfymsr5rPnuzIJKnsv9H5bMSrihjJHC+wrqR6Oyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2HP55COwoSeG9GFv9vzOWAu02VoIJpFvUUKrI70WweU=; b=AQMYrzM/Ef9dNQt69kkXnrfCyfXDYS+g1oEY4iImE9daUS5q/HH+x48IQLn4omlPGfQ7Wc6FiKUrT2CtovzUus9OYeIjteEcAXtovZ0DQeSdVVIOwum4ap2w65Dux19VHFZlhjrkeCmPt9ghEKzte3ionVNOoCHmTM/qlv47ktNCLNJHsVlUTFha7qHuMw92z4KelydqTdtx4Rv9wbw5A0cWxCoKhwx5kBfh+ZfxpbT7aDJmPwmiIBbEC51Lwe09ofYRTYLeD5JUEcJ5q9y/NKwtqyHK12QHgJr00FVhuin/grTILhL+u+dguhhZJBxj2+nPi6hRfgJeEe6ITV0GGQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2HP55COwoSeG9GFv9vzOWAu02VoIJpFvUUKrI70WweU=; b=av4QPnOavFXtuxA+JGSaYwqeDF+Xgf0EONqWCabjyHtChpoEAWUrbHd6WRUVAtXMrKZrTl6PILvqnMXRxuPaO9wHUSVDH+e4vhcI/fDtur2+FVRwbNVC/bfIefOHdB7wtjl20Izno2ZTOv/oSGngyET2wsCl3WI1DwcUJ+mY5r1PBQeS1uRM7hFuMZjw8J4PIsp2eZjPZvC2Ae2ChwoV+yt3jY8M9deIosYPsGNuTlI03yNIh+b/cTwRZJG10JM8XnvdIuKKAcpaoIG86Dt1RFVRjDULQKfTbNU6AH6oAfBFH8lNO3y6UOTeGYtzNWpRsYYYMPA6uSjIc2DOr2s3EQ== Received: from DM5PR07CA0155.namprd07.prod.outlook.com (2603:10b6:3:ee::21) by BN9PR12MB5353.namprd12.prod.outlook.com (2603:10b6:408:102::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4975.12; Mon, 14 Feb 2022 09:00:24 +0000 Received: from DM6NAM11FT012.eop-nam11.prod.protection.outlook.com (2603:10b6:3:ee:cafe::3e) by DM5PR07CA0155.outlook.office365.com (2603:10b6:3:ee::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4975.13 via Frontend Transport; Mon, 14 Feb 2022 09:00:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.236) by DM6NAM11FT012.mail.protection.outlook.com (10.13.173.109) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4975.11 via Frontend Transport; Mon, 14 Feb 2022 09:00:24 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 14 Feb 2022 09:00:23 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Mon, 14 Feb 2022 01:00:22 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9 via Frontend Transport; Mon, 14 Feb 2022 01:00:21 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko Subject: [PATCH 2/2] net/mlx5: optimize RxQ creation Date: Mon, 14 Feb 2022 11:00:10 +0200 Message-ID: <20220214090010.1541746-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220214090010.1541746-1-michaelba@nvidia.com> References: <20220214090010.1541746-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6a862e39-faf9-41aa-6fc8-08d9ef986fef X-MS-TrafficTypeDiagnostic: BN9PR12MB5353:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: N9i0QtQSjFXgL5suzqu+TaQVxOQhLXlO0Gjg/SaDlwqRk2IscejmP8TCNao8fLKejcLdZVg1xtZd7rHHs+vnDUlkNFODxsTJWkI6FQU9dhilC4B+pjBoaKz5oa46P+9kWRUrj+j9K89qfkFKeVk3IAOmuC6biTvVwZpGgG7LFMVOF3HwsBfL/b1pX4VFwoC9T5e0vy3FzBZg6YLfrQAlvFOmQfxjDz2Lgesd6MZw0W7o7HoeMXk+Xn8TJPGTzf2WMsMOyMWJSkxnS7CiuPGA83Ou/ICaqS//rzPhNL1Z3TrQ4rfkkzIhznZtX8I5EWbHF7NXDALy3Uhqh++PZC5XpM4ozOpU0xvRMlHG6hGnQXVSIvasLVbnY5oBi6dqHdSMdgP07+pUsuAmAtef7L8640mifrMtl3Up9xXBIyy6s9tM2u8N18tRl9Z7kEBdAbBMZrZurhF34/Es9SkW2+4XO0YkAFs52BdUrhVBJiw8VLnZ80+waPVl1jQv/1yk/ZJ1d/EyoqgVJPU+5OSF3eZvNqMvb9ku9VUuJkbVDpvEUSFak+o1ddJjl05gad8ctOK5JtuVo3Jhrrg5LPb1vF4BnradPk4TGsR73rWwCNbUJ7AZskkAR5KobC4xG/AWmP7ddI/h47fIuKt3NZjqPlZwLdh7Y2528WsZ51t5uk3BX40TUQqILmrOqxIy1ET6t2Hazs087saJWEvdM8Q6VNHd+w== X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(336012)(6916009)(54906003)(426003)(316002)(82310400004)(8936002)(70586007)(86362001)(70206006)(8676002)(4326008)(356005)(26005)(6286002)(7696005)(107886003)(2616005)(81166007)(186003)(2906002)(47076005)(1076003)(508600001)(83380400001)(36860700001)(55016003)(36756003)(40460700003)(5660300002)(6666004)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2022 09:00:24.0416 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a862e39-faf9-41aa-6fc8-08d9ef986fef X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5353 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Recently shared RxQ has been introduced. All shared Rx queues with same group and queue ID share the same rxq_ctrl, but each one has mlx5_rxq_priv structure. The mlx5_rx_queue_setup generates a new rxq_priv structure, and looks for a rxq_ctrl structure to refer to. If there is already a compatible rxq_ctrl structure it refers it, otherwise it calls the mlx5_rxq_new function that generates a new one. This patch makes mlx5_rxq_new function "standalone", it generates a rxq_ctrl structure regardless to specific rxq_priv structure. All operations on the rxq_ctrl structure that depend on the new rxq_priv structure are performed in the mlx5_rx_queue_setup function, at the same place for either a new rxq_ctrl structure or an existing rxq_ctrl structure. Signed-off-by: Michael Baum Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_rx.h | 3 +-- drivers/net/mlx5/mlx5_rxq.c | 28 +++++++++++----------------- 2 files changed, 12 insertions(+), 19 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index 7e417819f7..38335fd744 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -204,8 +204,7 @@ void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev); int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id); int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id); int mlx5_rxq_obj_verify(struct rte_eth_dev *dev); -struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, - struct mlx5_rxq_priv *rxq, +struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, const struct rte_eth_rxconf *conf, const struct rte_eth_rxseg_split *rx_seg, diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index fe72cf49d3..eaa48487cc 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -910,25 +910,23 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, rte_errno = ENOMEM; return -rte_errno; } - rxq->priv = priv; - rxq->idx = idx; - (*priv->rxq_privs)[idx] = rxq; - if (rxq_ctrl != NULL) { - /* Join owner list. */ - LIST_INSERT_HEAD(&rxq_ctrl->owners, rxq, owner_entry); - rxq->ctrl = rxq_ctrl; - } else { - rxq_ctrl = mlx5_rxq_new(dev, rxq, desc, socket, conf, rx_seg, + if (rxq_ctrl == NULL) { + rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, rx_seg, n_seg); if (rxq_ctrl == NULL) { DRV_LOG(ERR, "port %u unable to allocate rx queue index %u", dev->data->port_id, idx); mlx5_free(rxq); - (*priv->rxq_privs)[idx] = NULL; rte_errno = ENOMEM; return -rte_errno; } } + rxq->priv = priv; + rxq->idx = idx; + (*priv->rxq_privs)[idx] = rxq; + /* Join owner list. */ + LIST_INSERT_HEAD(&rxq_ctrl->owners, rxq, owner_entry); + rxq->ctrl = rxq_ctrl; mlx5_rxq_ref(dev, idx); DRV_LOG(DEBUG, "port %u adding Rx queue %u to list", dev->data->port_id, idx); @@ -1660,8 +1658,8 @@ mlx5_mprq_prepare(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, * * @param dev * Pointer to Ethernet device. - * @param rxq - * RX queue private data. + * @param idx + * RX queue index. * @param desc * Number of descriptors to configure in queue. * @param socket @@ -1671,12 +1669,10 @@ mlx5_mprq_prepare(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, * A DPDK queue object on success, NULL otherwise and rte_errno is set. */ struct mlx5_rxq_ctrl * -mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, - uint16_t desc, +mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, const struct rte_eth_rxconf *conf, const struct rte_eth_rxseg_split *rx_seg, uint16_t n_seg) { - uint16_t idx = rxq->idx; struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_rxq_ctrl *tmpl; unsigned int mb_len = rte_pktmbuf_data_room_size(rx_seg[0].mp); @@ -1719,8 +1715,6 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, return NULL; } LIST_INIT(&tmpl->owners); - rxq->ctrl = tmpl; - LIST_INSERT_HEAD(&tmpl->owners, rxq, owner_entry); MLX5_ASSERT(n_seg && n_seg <= MLX5_MAX_RXQ_NSEG); /* * Save the original segment configuration in the shared queue