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Tue, 1 Mar 2022 23:48:09 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko Subject: [PATCH 1/2] net/mlx5: fix external RQ dereferencing Date: Wed, 2 Mar 2022 09:48:00 +0200 Message-ID: <20220302074801.4140079-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302074801.4140079-1-michaelba@nvidia.com> References: <20220302074801.4140079-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: feb9619b-222d-45d6-6d33-08d9fc210100 X-MS-TrafficTypeDiagnostic: SN6PR12MB5696:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2Fsarmp7igv39UrMoe7MmLkJJXGP1bBJ8qWMWli/gbbQKuJUoNRDMDvVBe6TTYS+gGnAzCaak3iNH1IWquLu7oxugaN9UQ3NlNXXo6WNk0jeNNtqQay12Yl/ZGjwBC/WkVJK7LFIMp5piLzH8iha55Jlp5KL0abgFU/4Dco6jkQcbJEZM1VTrKfzjs7ztu52ZsMHADY041B2N1wRanY8jkk1DjvLBLkTkOr42XvzRiFHhTZcX0jOL4tcFHoGivPZC+TDy8cF63iaiVvfqihPsvx7aOQQn2+OKQH7gJhkp5Gz10FkiNSRh54SRpE4JVnkbX01YFvsStdJOUQiGvFo/o0lqiS2g3BvS7oqKwl2iuQRV58uWz84fcW1cfY6w10OypGx2Mp03N6/kb7IGMwV2H+3TtAaiCN7pS+I6wIc31Io7tfjaYPqnrpGdGsgOg13tZc0aXdIOteCnktZ8Nfgztg6ViNmkr7Zsu9n+HgK8vp6QG3rTY3e353Kg5C80cYsoswdKGLOmIiz5P/RnC+dssEs7daXlBFGxjLmAsrWGnRJB9Tpwj6BbpSKITk8BBgqLvHEJ+gGUeUwi9KFSdr/Kb2OuwYa2UNyYDSNxGkbuIL7nAlftlbAJ8HBWiAshC+1A/ZclW5phGWBF1/mrnJy+4OGOQafNtyGza8lnJPcQktWSc66EbWaCDn2w9pTkN6HcwaFvPIEn+pdKowZCeDQWg== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(508600001)(83380400001)(4326008)(86362001)(54906003)(8936002)(70586007)(70206006)(36756003)(426003)(26005)(81166007)(7696005)(336012)(356005)(40460700003)(6666004)(2906002)(186003)(55016003)(1076003)(6286002)(82310400004)(2616005)(5660300002)(316002)(6916009)(47076005)(36860700001)(107886003)(8676002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2022 07:48:12.9311 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: feb9619b-222d-45d6-6d33-08d9fc210100 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB5696 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When an indirection table is destroyed, each RX queue related to it, should be dereferenced. The regular queues are indeed dereferenced. However, the external RxQs are not. This patch adds dereferencing for external RxQs too. Fixes: 311b17e669ab ("net/mlx5: support queue/RSS actions for external Rx queue") Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_rxq.c | 41 ++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index ff293d9d56..19c75b7b32 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -2143,6 +2143,30 @@ mlx5_ext_rxq_get(struct rte_eth_dev *dev, uint16_t idx) return &priv->ext_rxqs[idx - MLX5_EXTERNAL_RX_QUEUE_ID_MIN]; } +/** + * Dereference a list of Rx queues. + * + * @param dev + * Pointer to Ethernet device. + * @param queues + * List of Rx queues to deref. + * @param queues_n + * Number of queues in the array. + */ +static void +mlx5_rxqs_deref(struct rte_eth_dev *dev, uint16_t *queues, + const uint32_t queues_n) +{ + uint32_t i; + + for (i = 0; i < queues_n; i++) { + if (mlx5_is_external_rxq(dev, queues[i])) + claim_nonzero(mlx5_ext_rxq_deref(dev, queues[i])); + else + claim_nonzero(mlx5_rxq_deref(dev, queues[i])); + } +} + /** * Release a Rx queue. * @@ -2377,7 +2401,7 @@ mlx5_ind_table_obj_release(struct rte_eth_dev *dev, bool deref_rxqs) { struct mlx5_priv *priv = dev->data->dev_private; - unsigned int i, ret; + unsigned int ret; rte_rwlock_write_lock(&priv->ind_tbls_lock); ret = __atomic_sub_fetch(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED); @@ -2387,10 +2411,8 @@ mlx5_ind_table_obj_release(struct rte_eth_dev *dev, if (ret) return 1; priv->obj_ops.ind_table_destroy(ind_tbl); - if (deref_rxqs) { - for (i = 0; i != ind_tbl->queues_n; ++i) - claim_nonzero(mlx5_rxq_deref(dev, ind_tbl->queues[i])); - } + if (deref_rxqs) + mlx5_rxqs_deref(dev, ind_tbl->queues, ind_tbl->queues_n); mlx5_free(ind_tbl); return 0; } @@ -2443,7 +2465,7 @@ mlx5_ind_table_obj_setup(struct rte_eth_dev *dev, struct mlx5_priv *priv = dev->data->dev_private; uint32_t queues_n = ind_tbl->queues_n; uint16_t *queues = ind_tbl->queues; - unsigned int i = 0, j; + unsigned int i = 0; int ret = 0, err; const unsigned int n = rte_is_power_of_2(queues_n) ? log2above(queues_n) : @@ -2471,12 +2493,7 @@ mlx5_ind_table_obj_setup(struct rte_eth_dev *dev, error: if (ref_qs) { err = rte_errno; - for (j = 0; j < i; j++) { - if (mlx5_is_external_rxq(dev, queues[j])) - mlx5_ext_rxq_deref(dev, queues[j]); - else - mlx5_rxq_deref(dev, queues[j]); - } + mlx5_rxqs_deref(dev, queues, i); rte_errno = err; } DRV_LOG(DEBUG, "Port %u cannot setup indirection table.", From patchwork Wed Mar 2 07:48:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 108473 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7DF8AA04A4; Wed, 2 Mar 2022 08:48:28 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 290BC42707; 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Wed, 2 Mar 2022 07:48:14 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Tue, 1 Mar 2022 23:48:13 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9 via Frontend Transport; Tue, 1 Mar 2022 23:48:12 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko Subject: [PATCH 2/2] net/mlx5: fix external RQ refrencing Date: Wed, 2 Mar 2022 09:48:01 +0200 Message-ID: <20220302074801.4140079-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302074801.4140079-1-michaelba@nvidia.com> References: <20220302074801.4140079-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 286415b9-1f92-4261-e4d0-08d9fc210257 X-MS-TrafficTypeDiagnostic: MN0PR12MB5835:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2022 07:48:15.0727 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 286415b9-1f92-4261-e4d0-08d9fc210257 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5835 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When an indirection table object is modified, it updates the reference counter for each RX queue related to it. The reference counter for regular queues are indeed updated. However, the reference counter for external RxQs are not. This patch adds updating for external RxQs too. Fixes: 311b17e669ab ("net/mlx5: support queue/RSS actions for external Rx queue") Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_rxq.c | 121 +++++++++++++++++++++--------------- 1 file changed, 70 insertions(+), 51 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 19c75b7b32..f16795bac3 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -2167,6 +2167,41 @@ mlx5_rxqs_deref(struct rte_eth_dev *dev, uint16_t *queues, } } +/** + * Increase reference count for list of Rx queues. + * + * @param dev + * Pointer to Ethernet device. + * @param queues + * List of Rx queues to ref. + * @param queues_n + * Number of queues in the array. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_rxqs_ref(struct rte_eth_dev *dev, uint16_t *queues, + const uint32_t queues_n) +{ + uint32_t i; + + for (i = 0; i != queues_n; ++i) { + if (mlx5_is_external_rxq(dev, queues[i])) { + if (mlx5_ext_rxq_ref(dev, queues[i]) == NULL) + goto error; + } else { + if (mlx5_rxq_ref(dev, queues[i]) == NULL) + goto error; + } + } + return 0; +error: + mlx5_rxqs_deref(dev, queues, i); + rte_errno = EINVAL; + return -rte_errno; +} + /** * Release a Rx queue. * @@ -2464,41 +2499,30 @@ mlx5_ind_table_obj_setup(struct rte_eth_dev *dev, { struct mlx5_priv *priv = dev->data->dev_private; uint32_t queues_n = ind_tbl->queues_n; - uint16_t *queues = ind_tbl->queues; - unsigned int i = 0; - int ret = 0, err; + int ret; const unsigned int n = rte_is_power_of_2(queues_n) ? log2above(queues_n) : log2above(priv->sh->dev_cap.ind_table_max_size); - if (ref_qs) - for (i = 0; i != queues_n; ++i) { - if (mlx5_is_external_rxq(dev, queues[i])) { - if (mlx5_ext_rxq_ref(dev, queues[i]) == NULL) { - ret = -rte_errno; - goto error; - } - } else { - if (mlx5_rxq_ref(dev, queues[i]) == NULL) { - ret = -rte_errno; - goto error; - } - } - } + if (ref_qs && mlx5_rxqs_ref(dev, ind_tbl->queues, queues_n) < 0) { + DRV_LOG(DEBUG, "Port %u invalid indirection table queues.", + dev->data->port_id); + return -rte_errno; + } ret = priv->obj_ops.ind_table_new(dev, n, ind_tbl); - if (ret) - goto error; + if (ret) { + DRV_LOG(DEBUG, "Port %u cannot create a new indirection table.", + dev->data->port_id); + if (ref_qs) { + int err = rte_errno; + + mlx5_rxqs_deref(dev, ind_tbl->queues, queues_n); + rte_errno = err; + } + return ret; + } __atomic_fetch_add(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED); return 0; -error: - if (ref_qs) { - err = rte_errno; - mlx5_rxqs_deref(dev, queues, i); - rte_errno = err; - } - DRV_LOG(DEBUG, "Port %u cannot setup indirection table.", - dev->data->port_id); - return ret; } /** @@ -2603,8 +2627,7 @@ mlx5_ind_table_obj_modify(struct rte_eth_dev *dev, bool standalone, bool ref_new_qs, bool deref_old_qs) { struct mlx5_priv *priv = dev->data->dev_private; - unsigned int i = 0, j; - int ret = 0, err; + int ret; const unsigned int n = rte_is_power_of_2(queues_n) ? log2above(queues_n) : log2above(priv->sh->dev_cap.ind_table_max_size); @@ -2613,33 +2636,29 @@ mlx5_ind_table_obj_modify(struct rte_eth_dev *dev, RTE_SET_USED(standalone); if (mlx5_ind_table_obj_check_standalone(dev, ind_tbl) < 0) return -rte_errno; - if (ref_new_qs) - for (i = 0; i != queues_n; ++i) { - if (!mlx5_rxq_ref(dev, queues[i])) { - ret = -rte_errno; - goto error; - } - } + if (ref_new_qs && mlx5_rxqs_ref(dev, queues, queues_n) < 0) { + DRV_LOG(DEBUG, "Port %u invalid indirection table queues.", + dev->data->port_id); + return -rte_errno; + } MLX5_ASSERT(priv->obj_ops.ind_table_modify); ret = priv->obj_ops.ind_table_modify(dev, n, queues, queues_n, ind_tbl); - if (ret) - goto error; + if (ret) { + DRV_LOG(DEBUG, "Port %u cannot modify indirection table.", + dev->data->port_id); + if (ref_new_qs) { + int err = rte_errno; + + mlx5_rxqs_deref(dev, queues, queues_n); + rte_errno = err; + } + return ret; + } if (deref_old_qs) - for (i = 0; i < ind_tbl->queues_n; i++) - claim_nonzero(mlx5_rxq_deref(dev, ind_tbl->queues[i])); + mlx5_rxqs_deref(dev, ind_tbl->queues, ind_tbl->queues_n); ind_tbl->queues_n = queues_n; ind_tbl->queues = queues; return 0; -error: - if (ref_new_qs) { - err = rte_errno; - for (j = 0; j < i; j++) - mlx5_rxq_deref(dev, queues[j]); - rte_errno = err; - } - DRV_LOG(DEBUG, "Port %u cannot setup indirection table.", - dev->data->port_id); - return ret; } /**