From patchwork Fri Mar 25 13:03:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Bhansali X-Patchwork-Id: 108870 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DCC07A00C3; Fri, 25 Mar 2022 14:04:01 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BEBBE40687; Fri, 25 Mar 2022 14:04:01 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1B49140140 for ; Fri, 25 Mar 2022 14:03:59 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22P6EwnT022341 for ; Fri, 25 Mar 2022 06:03:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=quRc5qWLgeVma2hIsSOv/vg6cwUjY0tZQaeyNBl7Ggg=; b=hVMxiL0fN+YAkvKkNxasNUtPSr5EFpKzJuimtOFZPE9E4FdTQ7sEfZDQachdDAhpIWqy ctwzP/+1jixl83hPCbZsZj8XPTUACj0l9dbvjnaW1BoDCJOCik2K0SwtZpO88zrI7FE0 tj/7ZydilmrUP+XxALhpBvSf53uzkZm4hfz3sd2Klv7ADC7VbZTaP1pTqI/ZUuCC5yN1 N8xdbMpr8HmWPuqXy2qxTivI5+eG6PbZQlT2gWMijnwFogebyjYl8C+MzpwNOuEQlNYi eoPXE4k3yrczXXK2sK+X5Ext3OctwtWzAPVmWFKvcX5bUhFfgy878ajSMYFXpt2StncG wg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3f0mn6xgqq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 25 Mar 2022 06:03:59 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 25 Mar 2022 06:03:57 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 25 Mar 2022 06:03:57 -0700 Received: from localhost.localdomain (unknown [10.28.48.107]) by maili.marvell.com (Postfix) with ESMTP id A10613F7043; Fri, 25 Mar 2022 06:03:55 -0700 (PDT) From: Rahul Bhansali To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rahul Bhansali Subject: [PATCH 1/4] common/cnxk: add CN103XX platform support Date: Fri, 25 Mar 2022 18:33:48 +0530 Message-ID: <20220325130351.3207019-1-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-GUID: NoDDRObhGLarYf8mGfkeqKj--XnPO538 X-Proofpoint-ORIG-GUID: NoDDRObhGLarYf8mGfkeqKj--XnPO538 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-25_02,2022-03-24_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added support for CN103XX (cn10kb) platform. Signed-off-by: Rahul Bhansali --- doc/guides/platform/cnxk.rst | 1 + drivers/common/cnxk/roc_constants.h | 1 + drivers/common/cnxk/roc_model.c | 4 ++++ drivers/common/cnxk/roc_model.h | 11 ++++++++++- 4 files changed, 16 insertions(+), 1 deletion(-) diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst index 3dee725ac5..92aa702a78 100644 --- a/doc/guides/platform/cnxk.rst +++ b/doc/guides/platform/cnxk.rst @@ -18,6 +18,7 @@ Supported OCTEON cnxk SoCs - CN98xx - CN106xx - CNF105xx +- CN103XX Resource Virtualization Unit architecture ----------------------------------------- diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h index 38e2087a26..1daaabfe55 100644 --- a/drivers/common/cnxk/roc_constants.h +++ b/drivers/common/cnxk/roc_constants.h @@ -52,6 +52,7 @@ #define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900 #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900 #define PCI_SUBSYSTEM_DEVID_CNF10KA 0xBA00 +#define PCI_SUBSYSTEM_DEVID_CN10KB 0xB900 #define PCI_SUBSYSTEM_DEVID_CN9KA 0x0000 #define PCI_SUBSYSTEM_DEVID_CN9KB 0xb400 diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c index 4120029541..1dd374e0fd 100644 --- a/drivers/common/cnxk/roc_model.c +++ b/drivers/common/cnxk/roc_model.c @@ -16,6 +16,7 @@ struct roc_model *roc_model; #define PART_106xx 0xB9 #define PART_105xx 0xBA #define PART_105xxN 0xBC +#define PART_103xx 0xBE #define PART_98xx 0xB1 #define PART_96xx 0xB2 #define PART_95xx 0xB3 @@ -46,6 +47,7 @@ static const struct model_db { } model_db[] = { {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"}, {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"}, + {VENDOR_ARM, PART_103xx, 0, 0, ROC_MODEL_CN103xx_A0, "cn10kb_a0"}, {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"}, {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"}, {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"}, @@ -92,6 +94,8 @@ cn10k_part_get(void) soc = PART_105xx; } else if (strcmp("cnf10kb", ptr) == 0) { soc = PART_105xxN; + } else if (strcmp("cn10kb", ptr) == 0) { + soc = PART_103xx; } else { plt_err("Unidentified 'CPU compatible': <%s>", ptr); goto fclose; diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index 4567566169..885c3d668f 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -24,6 +24,7 @@ struct roc_model { #define ROC_MODEL_CN106xx_A0 BIT_ULL(20) #define ROC_MODEL_CNF105xx_A0 BIT_ULL(21) #define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22) +#define ROC_MODEL_CN103xx_A0 BIT_ULL(23) /* Following flags describe platform code is running on */ #define ROC_ENV_HW BIT_ULL(61) #define ROC_ENV_EMUL BIT_ULL(62) @@ -50,8 +51,10 @@ struct roc_model { #define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0) #define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0) #define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0) +#define ROC_MODEL_CN103xx (ROC_MODEL_CN103xx_A0) #define ROC_MODEL_CN10K \ - (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN) + (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN | \ + ROC_MODEL_CN103xx) #define ROC_MODEL_CNF10K (ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN) /* Runtime variants */ @@ -152,6 +155,12 @@ roc_model_is_cnf10kb(void) return roc_model->flag & ROC_MODEL_CNF105xxN; } +static inline uint64_t +roc_model_is_cn10kb_a0(void) +{ + return roc_model->flag & ROC_MODEL_CN103xx_A0; +} + static inline uint64_t roc_model_is_cn10ka_a0(void) { From patchwork Fri Mar 25 13:03:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Bhansali X-Patchwork-Id: 108871 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E4B34A00C3; Fri, 25 Mar 2022 14:04:08 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D4E6542867; Fri, 25 Mar 2022 14:04:05 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id E695C4286C for ; Fri, 25 Mar 2022 14:04:03 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22P6URPs024133 for ; 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Fri, 25 Mar 2022 06:04:01 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 25 Mar 2022 06:04:01 -0700 Received: from localhost.localdomain (unknown [10.28.48.107]) by maili.marvell.com (Postfix) with ESMTP id 63CB33F704D; Fri, 25 Mar 2022 06:03:59 -0700 (PDT) From: Rahul Bhansali To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rahul Bhansali Subject: [PATCH 2/4] net/cnxk: add CN103XX platform support Date: Fri, 25 Mar 2022 18:33:49 +0530 Message-ID: <20220325130351.3207019-2-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220325130351.3207019-1-rbhansali@marvell.com> References: <20220325130351.3207019-1-rbhansali@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: oFje-ZejQYjKk3gyHIHXyxV7wlOKAyG8 X-Proofpoint-ORIG-GUID: oFje-ZejQYjKk3gyHIHXyxV7wlOKAyG8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-25_02,2022-03-24_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added PCI device ID for CN103XX (cn10kb) platform. Signed-off-by: Rahul Bhansali --- drivers/net/cnxk/cn10k_ethdev.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index 15dbea2180..ce3707be6f 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -795,12 +795,15 @@ static const struct rte_pci_id cn10k_pci_nix_map[] = { CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_PF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_PF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_PF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_VF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_VF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_VF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_AF_VF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_AF_VF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_AF_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_AF_VF), { .vendor_id = 0, }, From patchwork Fri Mar 25 13:03:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Bhansali X-Patchwork-Id: 108872 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9B2B4A00C3; Fri, 25 Mar 2022 14:04:14 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AFE764286F; Fri, 25 Mar 2022 14:04:09 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 9FDA34286F for ; Fri, 25 Mar 2022 14:04:07 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22P0vIAE016808 for ; Fri, 25 Mar 2022 06:04:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=jyVxYFiyOqX5c5E4KRBEEBxfpitRL2GV/XNz1Knx1S0=; b=eIvJlbb4fJ00kOj2Go+I3yPxNAvbXICteSRcs00qUirVjZ6BH473pk7OATzr/OQ0Orxr A1XBx0EOOLjptB7IxBL6WStefzwhwbLe+Ne/MmopxfNSoiCHC69OX8VA/ocvU+x8lr+r GlWm749SzAxZ9Ro7gFgt4oWbiHUJtWJx3Qf/CGYpIB1QIhBgjKso4/Xa8Vuq0fqnjJH3 2qGBrbDKAFNM1HYh3FWcdglY44QARcnC3UN4CyjPDO4C83gcKTm7W31yaFdygmvGFhIj c7XCayf7t+/UyDhETGiR56Lf/Hxz+/7cdR7LwmYEezNULbwBNyK1miZxC4ubgWEMYo5o Tg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3eystf5a3q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 25 Mar 2022 06:04:06 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 25 Mar 2022 06:04:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 25 Mar 2022 06:04:04 -0700 Received: from localhost.localdomain (unknown [10.28.48.107]) by maili.marvell.com (Postfix) with ESMTP id 290C03F704F; Fri, 25 Mar 2022 06:04:02 -0700 (PDT) From: Rahul Bhansali To: , Pavan Nikhilesh , "Shijith Thotton" CC: , Rahul Bhansali Subject: [PATCH 3/4] event/cnxk: add CN103XX platform support Date: Fri, 25 Mar 2022 18:33:50 +0530 Message-ID: <20220325130351.3207019-3-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220325130351.3207019-1-rbhansali@marvell.com> References: <20220325130351.3207019-1-rbhansali@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 0usG-lttbliM7xgSHHR8FUReycpvTV1C X-Proofpoint-GUID: 0usG-lttbliM7xgSHHR8FUReycpvTV1C X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-25_02,2022-03-24_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added PCI device ID for CN103XX (cn10kb) platform. Signed-off-by: Rahul Bhansali --- drivers/event/cnxk/cn10k_eventdev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 9b4d2895ec..75c748f611 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -935,9 +935,11 @@ static const struct rte_pci_id cn10k_pci_sso_map[] = { CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_SSO_TIM_PF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_SSO_TIM_VF), { .vendor_id = 0, }, From patchwork Fri Mar 25 13:03:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Bhansali X-Patchwork-Id: 108873 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 21B0CA00C3; Fri, 25 Mar 2022 14:04:20 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 89F5E4286B; Fri, 25 Mar 2022 14:04:12 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B2C9F42873 for ; Fri, 25 Mar 2022 14:04:10 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22P5c6US022013 for ; Fri, 25 Mar 2022 06:04:09 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=zl6pm3zRks8X9N6RRHuBPVreNDJEd6U9U60T905DG+Y=; b=a5JP9Y4Xs0jC1Mvuvn2wNeupEEoR4Zrrd70D1BqujjaMi4TPmjCR5kyLcKyh2nsK/POG xoSvG7U6x0IVUkBslkbqZ88Jc+pXNaB6x4ssMY3lTauiyINe0/zIuB4ihwb46zmeRNth VSpL9cPUWqMJ5HUclnNwB6bKi4KIZfTAoAdLDwupQVyaD26Fd4GWWUeDdQudO3pYF310 iHF1FuhV1WGBU9kjF4DJ3rLmhA7G3zrg80u1vnX41zLzXaEC6E2+SAAG80Qhx3jE+npc wxJMqBfMq2UbUHENlZpC7Iebcy8s6N2D8M3C34TTMmmIA9pLPPVsC53bGO/RKdFdXe9o UA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3f0mn6xgs0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 25 Mar 2022 06:04:09 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 25 Mar 2022 06:04:08 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 25 Mar 2022 06:04:07 -0700 Received: from localhost.localdomain (unknown [10.28.48.107]) by maili.marvell.com (Postfix) with ESMTP id 5193D3F704F; Fri, 25 Mar 2022 06:04:06 -0700 (PDT) From: Rahul Bhansali To: , Ashwin Sekhar T K , Pavan Nikhilesh CC: , Rahul Bhansali Subject: [PATCH 4/4] mempool/cnxk: add CN103XX platform support Date: Fri, 25 Mar 2022 18:33:51 +0530 Message-ID: <20220325130351.3207019-4-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220325130351.3207019-1-rbhansali@marvell.com> References: <20220325130351.3207019-1-rbhansali@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: DO1chQDwf1vKmi58RNV-y9qPvJSkBGaD X-Proofpoint-ORIG-GUID: DO1chQDwf1vKmi58RNV-y9qPvJSkBGaD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-25_02,2022-03-24_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added PCI device ID for CN103XX (cn10kb) platform. Signed-off-by: Rahul Bhansali --- drivers/mempool/cnxk/cnxk_mempool.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mempool/cnxk/cnxk_mempool.c b/drivers/mempool/cnxk/cnxk_mempool.c index ea473552dd..a28fe5406d 100644 --- a/drivers/mempool/cnxk/cnxk_mempool.c +++ b/drivers/mempool/cnxk/cnxk_mempool.c @@ -163,6 +163,7 @@ npa_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) static const struct rte_pci_id npa_pci_map[] = { CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_NPA_PF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_NPA_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_NPA_PF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_NPA_PF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_NPA_PF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_NPA_PF), @@ -170,6 +171,7 @@ static const struct rte_pci_id npa_pci_map[] = { CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_NPA_PF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_NPA_VF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_NPA_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_NPA_VF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_NPA_VF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_NPA_VF), CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_NPA_VF),