From patchwork Mon Mar 28 06:47:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 108900 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BE03AA034C; Mon, 28 Mar 2022 08:47:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 987ED41141; Mon, 28 Mar 2022 08:47:55 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 20BF34068B for ; Mon, 28 Mar 2022 08:47:54 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22RLRYF4001115 for ; Sun, 27 Mar 2022 23:47:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=XfUajRiQhU1+QSNlaaE1VR6t1IRHfQ1vgrF7ifw9GG0=; b=bzRrSzxJi7SvvAlm+lXpgMSSgfGNTlh2+i8HmvnWvNMonKxaqFmR6fzlTFdHYtVSsjnd /HMveph9Jffi6Aeusca8OVlQ6imimS/dwxJG/LPkOQmDwmu6kiwQDDZ9jrnu4flCVPmJ /UZmO4DYZV6G1r5HRCuwJQhBSEu7Kgb6w3RZcERW0xyN6wqiB2//o2NUtcAbaq1V+89H ht6IlBTj2ah3V6Oq5dyqcSmAEe4mfDi3+kjcNZPNP3r1IdDI8bQYHw/TT8e/BAVdXnlY kLnSKwGLlVaVwFNUrhGCa2Jy8CWBph19sGFT5ibynYXySeRN+AHbWLEBoSt5zvmqGby7 cQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3f22bn5emm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 27 Mar 2022 23:47:53 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 27 Mar 2022 23:47:51 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.32 via Frontend Transport; Sun, 27 Mar 2022 23:47:51 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 46CE23F7050; Sun, 27 Mar 2022 23:47:49 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH 1/4] common/cnxk: use aggregate level rr prio from mbox Date: Mon, 28 Mar 2022 12:17:37 +0530 Message-ID: <20220328064740.8049-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 MIME-Version: 1.0 X-Proofpoint-GUID: FOdBblP0OlhSDOTtcCVSJuVnvKUBUOZP X-Proofpoint-ORIG-GUID: FOdBblP0OlhSDOTtcCVSJuVnvKUBUOZP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-28_02,2022-03-24_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Use aggregate level Round Robin Priority from mbox response instead of fixing it to single macro. This is useful when kernel AF driver changes the constant. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix_priv.h | 5 +++-- drivers/common/cnxk/roc_nix_tm.c | 3 ++- drivers/common/cnxk/roc_nix_tm_utils.c | 8 ++++---- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 9b9ffae..cc69d71 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -181,6 +181,7 @@ struct nix { uint16_t tm_root_lvl; uint16_t tm_flags; uint16_t tm_link_cfg_lvl; + uint8_t tm_aggr_lvl_rr_prio; uint16_t contig_rsvd[NIX_TXSCH_LVL_CNT]; uint16_t discontig_rsvd[NIX_TXSCH_LVL_CNT]; uint64_t tm_markfmt_en; @@ -284,7 +285,6 @@ void nix_unregister_irqs(struct nix *nix); /* Default TL1 priority and Quantum from AF */ #define NIX_TM_TL1_DFLT_RR_QTM ((1 << 24) - 1) -#define NIX_TM_TL1_DFLT_RR_PRIO 1 struct nix_tm_shaper_data { uint64_t burst_exponent; @@ -432,7 +432,8 @@ bool nix_tm_child_res_valid(struct nix_tm_node_list *list, struct nix_tm_node *parent); uint16_t nix_tm_resource_estimate(struct nix *nix, uint16_t *schq_contig, uint16_t *schq, enum roc_nix_tm_tree tree); -uint8_t nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg, +uint8_t nix_tm_tl1_default_prep(struct nix *nix, uint32_t schq, + volatile uint64_t *reg, volatile uint64_t *regval); uint8_t nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, volatile uint64_t *reg, diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c index 5b70c7b..84815d0 100644 --- a/drivers/common/cnxk/roc_nix_tm.c +++ b/drivers/common/cnxk/roc_nix_tm.c @@ -55,7 +55,7 @@ nix_tm_node_reg_conf(struct nix *nix, struct nix_tm_node *node) req = mbox_alloc_msg_nix_txschq_cfg(mbox); req->lvl = NIX_TXSCH_LVL_TL1; - k = nix_tm_tl1_default_prep(node->parent_hw_id, req->reg, + k = nix_tm_tl1_default_prep(nix, node->parent_hw_id, req->reg, req->regval); req->num_regs = k; rc = mbox_process(mbox); @@ -1281,6 +1281,7 @@ nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree) } while (pend); nix->tm_link_cfg_lvl = rsp->link_cfg_lvl; + nix->tm_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio; return 0; alloc_err: for (i = 0; i < NIX_TXSCH_LVL_CNT; i++) { diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index bcdf990..b9b605f 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -478,7 +478,7 @@ nix_tm_child_res_valid(struct nix_tm_node_list *list, } uint8_t -nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg, +nix_tm_tl1_default_prep(struct nix *nix, uint32_t schq, volatile uint64_t *reg, volatile uint64_t *regval) { uint8_t k = 0; @@ -496,7 +496,7 @@ nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg, k++; reg[k] = NIX_AF_TL1X_TOPOLOGY(schq); - regval[k] = (NIX_TM_TL1_DFLT_RR_PRIO << 1); + regval[k] = (nix->tm_aggr_lvl_rr_prio << 1); k++; reg[k] = NIX_AF_TL1X_CIR(schq); @@ -540,7 +540,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, * Static Priority is disabled */ if (hw_lvl == NIX_TXSCH_LVL_TL1 && nix->tm_flags & NIX_TM_TL1_NO_SP) { - rr_prio = NIX_TM_TL1_DFLT_RR_PRIO; + rr_prio = nix->tm_aggr_lvl_rr_prio; child = 0; } @@ -662,7 +662,7 @@ nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node, */ if (hw_lvl == NIX_TXSCH_LVL_TL2 && (!nix_tm_have_tl1_access(nix) || nix->tm_flags & NIX_TM_TL1_NO_SP)) - strict_prio = NIX_TM_TL1_DFLT_RR_PRIO; + strict_prio = nix->tm_aggr_lvl_rr_prio; plt_tm_dbg("Schedule config node %s(%u) lvl %u id %u, " "prio 0x%" PRIx64 ", rr_quantum/rr_wt 0x%" PRIx64 " (%p)", From patchwork Mon Mar 28 06:47:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 108901 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 74CADA034C; Mon, 28 Mar 2022 08:48:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 657E842867; 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Sun, 27 Mar 2022 23:47:57 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 27 Mar 2022 23:47:55 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 27 Mar 2022 23:47:55 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 954BB3F7050; Sun, 27 Mar 2022 23:47:53 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH 2/4] net/cnxk: support loopback mode on AF VF's Date: Mon, 28 Mar 2022 12:17:38 +0530 Message-ID: <20220328064740.8049-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220328064740.8049-1-ndabilpuram@marvell.com> References: <20220328064740.8049-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: vpls1zqsPCbVMIjcLsy5dov02gYBimJu X-Proofpoint-ORIG-GUID: vpls1zqsPCbVMIjcLsy5dov02gYBimJu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-28_02,2022-03-24_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support internal loopback mode on AF VF's using RoC by setting Tx channel same as Rx channel. Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cnxk_ethdev.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 1fa4131..7f8479a 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1116,6 +1116,9 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) nb_rxq = RTE_MAX(data->nb_rx_queues, 1); nb_txq = RTE_MAX(data->nb_tx_queues, 1); + if (roc_nix_is_lbk(nix)) + nix->enable_loop = eth_dev->data->dev_conf.lpbk_mode; + /* Alloc a nix lf */ rc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg); if (rc) { @@ -1239,6 +1242,9 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) } } + if (roc_nix_is_lbk(nix)) + goto skip_lbk_setup; + /* Configure loop back mode */ rc = roc_nix_mac_loopback_enable(nix, eth_dev->data->dev_conf.lpbk_mode); @@ -1247,6 +1253,7 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) goto cq_fini; } +skip_lbk_setup: /* Setup Inline security support */ rc = nix_security_setup(dev); if (rc) From patchwork Mon Mar 28 06:47:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 108902 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 493CEA034C; Mon, 28 Mar 2022 08:48:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 398364286D; Mon, 28 Mar 2022 08:48:02 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0850D42863 for ; Mon, 28 Mar 2022 08:48:00 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22RNDbZp004272 for ; Sun, 27 Mar 2022 23:48:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=Ub1JxHaYCNEQAAiNwrCa6u7s0rtwgWole6uk86gCfqs=; b=L37d3OEOyTvQOrOkkdnlh+JP9mseFd7E8us4XShX8kO6kWJkspSBDyTfhw8Ouk9oYFS5 0+pEUsED0A7VH4r8xLN1WAKgQWS88Q72zqAPNJHcxS4FOTK7U41O0EIzaS8+jn0nfera CLj8j+R2Ye580JRmMvqjQOk3pC0DwzkAV8vSClTVB1nRSBINxyZAY5Me+s+1NwTCNa4R efXJ6aBByPj6ox0xqBhsMGr13yuvrFwqacyVTsJUUpJ+S8DaYMUAQxBq433FlqNvH2A9 Fx/iDXKssfZCHvbRdVpOY7NOUiJUWKLbyJpgoXrDG5bz34V5oT4n26HNj3xBUe/Yhylz kw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3f206p5umr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 27 Mar 2022 23:48:00 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Sun, 27 Mar 2022 23:47:58 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.32 via Frontend Transport; Sun, 27 Mar 2022 23:47:58 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id BE9E43F7050; Sun, 27 Mar 2022 23:47:56 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH 3/4] net/cnxk: update LBK ethdev link info Date: Mon, 28 Mar 2022 12:17:39 +0530 Message-ID: <20220328064740.8049-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220328064740.8049-1-ndabilpuram@marvell.com> References: <20220328064740.8049-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ZOA4h2F9vaWpRYyFFAGKkm2wrB8p3c_G X-Proofpoint-ORIG-GUID: ZOA4h2F9vaWpRYyFFAGKkm2wrB8p3c_G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-28_02,2022-03-24_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update link info of LBK ethdev i.e AF's VF's as always up and 100G. This is because there is no phy for the LBK interfaces and we won't get a link update notification for the same. Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cnxk_link.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/cnxk/cnxk_link.c b/drivers/net/cnxk/cnxk_link.c index f10a502..b1d59e3 100644 --- a/drivers/net/cnxk/cnxk_link.c +++ b/drivers/net/cnxk/cnxk_link.c @@ -12,6 +12,17 @@ cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set) else dev->flags &= ~CNXK_LINK_CFG_IN_PROGRESS_F; + /* Update link info for LBK */ + if (!set && roc_nix_is_lbk(&dev->nix)) { + struct rte_eth_link link; + + link.link_status = RTE_ETH_LINK_UP; + link.link_speed = RTE_ETH_SPEED_NUM_100G; + link.link_autoneg = RTE_ETH_LINK_FIXED; + link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; + rte_eth_linkstatus_set(dev->eth_dev, &link); + } + rte_wmb(); } From patchwork Mon Mar 28 06:47:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 108903 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E1F76A034C; Mon, 28 Mar 2022 08:48:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5A83F42874; Mon, 28 Mar 2022 08:48:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 74DB74287B; Mon, 28 Mar 2022 08:48:05 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22RMbX5Y026749; Sun, 27 Mar 2022 23:48:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=Jz4fuzVL5nbzhmNNEgknatWGvBjUjVsaXKEILaN8F3A=; b=DML+Y9ZiOwTZ7229D16zgGIgXz0yAzAiUEQyiwo9iCLVwvUIxc9/bXQopBUm8SrxKNTM hhr50EzADZZbzTdZterQ60X9vcwoeaLa+4/GitVrX1v0XxBT5dy7q91ekhsEDEpKYdJw ahlBNGW+Z1gvU4gXsvXKeyBMRDn/tCHbLdWz1dUItZ4U4kNHFu1q/hLSi3evK29nwKIf XiNUHCmbqhY+EZSyBf1hwFI7FVLhtULxQx2eSkdu4tql4fEo9BwST8StCmHJvP5GBsM1 0i/4Pf8bwWi3svFNyBkeousqFVHv+ID3bpJcEyWYO+lVmKvnL4S+nCGMXF0BUxrqIv6p hQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3f22bn5enh-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 27 Mar 2022 23:48:04 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 27 Mar 2022 23:48:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 27 Mar 2022 23:48:02 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id E44A73F7050; Sun, 27 Mar 2022 23:47:59 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 4/4] net/cnxk: add barrier after meta batch free in scalar Date: Mon, 28 Mar 2022 12:17:40 +0530 Message-ID: <20220328064740.8049-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220328064740.8049-1-ndabilpuram@marvell.com> References: <20220328064740.8049-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 4VcLQXTmQ7zvGy11o3tzG4PQS2Rwen7d X-Proofpoint-ORIG-GUID: 4VcLQXTmQ7zvGy11o3tzG4PQS2Rwen7d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-28_02,2022-03-24_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add barrier after meta batch free in scalar routine when lmt lines are exactly full to make sure that next LMT line user in Tx only starts writing the lines only when previous stoerl's are complete. Fixes: 4382a7ccf781 ("net/cnxk: support Rx security offload on cn10k") Cc: stable@dpdk.org Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_rx.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index e4f5a55..94c1f1e 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -1007,10 +1007,11 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts, plt_write64((wdata | nb_pkts), rxq->cq_door); /* Free remaining meta buffers if any */ - if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) { + if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) nix_sec_flush_meta(laddr, lmt_id + lnum, loff, aura_handle); - plt_io_wmb(); - } + + if (flags & NIX_RX_OFFLOAD_SECURITY_F) + rte_io_wmb(); return nb_pkts; }