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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by DM6NAM11FT061.mail.protection.outlook.com (10.13.173.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5123.19 via Frontend Transport; Fri, 1 Apr 2022 03:22:58 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Fri, 1 Apr 2022 03:22:58 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 31 Mar 2022 20:22:55 -0700 From: Spike Du To: , , , CC: , Subject: [RFC 1/6] net/mlx5: add LWM support for Rxq Date: Fri, 1 Apr 2022 06:22:27 +0300 Message-ID: <20220401032232.1267376-2-spiked@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220401032232.1267376-1-spiked@nvidia.com> References: <20220401032232.1267376-1-spiked@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 49bbf954-b03f-4802-347e-08da138eebca X-MS-TrafficTypeDiagnostic: MW2PR12MB2410:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2022 03:22:58.7277 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49bbf954-b03f-4802-347e-08da138eebca X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2410 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add lwm(Limit WaterMark) field to Rxq object which indicates the percentage of RX queue size used by HW to raise LWM event to the user. Allow LWM setting in modify_rq command. Allow the LWM configuration dynamically by adding RDY2RDY state change. Signed-off-by: Spike Du --- drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_devx.c | 10 +++++++++- drivers/net/mlx5/mlx5_devx.h | 1 + drivers/net/mlx5/mlx5_rx.h | 1 + 4 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 23a28f6..f3e6682 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1391,6 +1391,7 @@ enum mlx5_rxq_modify_type { MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ + MLX5_RXQ_MOD_RDY2RDY, /* modify state from ready to ready. */ }; enum mlx5_txq_modify_type { diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index af106bd..d6de882 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -62,7 +62,7 @@ * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ -static int +int mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type) { struct mlx5_devx_modify_rq_attr rq_attr; @@ -76,6 +76,8 @@ case MLX5_RXQ_MOD_RST2RDY: rq_attr.rq_state = MLX5_RQC_STATE_RST; rq_attr.state = MLX5_RQC_STATE_RDY; + rq_attr.modify_bitmask |= MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM; + rq_attr.lwm = rxq->lwm; break; case MLX5_RXQ_MOD_RDY2ERR: rq_attr.rq_state = MLX5_RQC_STATE_RDY; @@ -85,6 +87,12 @@ rq_attr.rq_state = MLX5_RQC_STATE_RDY; rq_attr.state = MLX5_RQC_STATE_RST; break; + case MLX5_RXQ_MOD_RDY2RDY: + rq_attr.rq_state = MLX5_RQC_STATE_RDY; + rq_attr.state = MLX5_RQC_STATE_RDY; + rq_attr.modify_bitmask |= MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM; + rq_attr.lwm = rxq->lwm; + break; default: break; } diff --git a/drivers/net/mlx5/mlx5_devx.h b/drivers/net/mlx5/mlx5_devx.h index a95207a..ebd1da4 100644 --- a/drivers/net/mlx5/mlx5_devx.h +++ b/drivers/net/mlx5/mlx5_devx.h @@ -11,6 +11,7 @@ int mlx5_txq_devx_modify(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type, uint8_t dev_port); void mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj); +int mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type); extern struct mlx5_obj_ops devx_obj_ops; diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index acebe33..98d7cae 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -174,6 +174,7 @@ struct mlx5_rxq_priv { struct mlx5_devx_rq devx_rq; struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ uint32_t hairpin_status; /* Hairpin binding status. */ + uint32_t lwm:16; }; /* External RX queue descriptor. */ From patchwork Fri Apr 1 03:22:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Spike Du X-Patchwork-Id: 109053 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B4EF5A0503; Fri, 1 Apr 2022 05:23:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 874BD42914; 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Fri, 1 Apr 2022 03:23:04 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 31 Mar 2022 20:23:02 -0700 From: Spike Du To: , , , CC: , Subject: [RFC 2/6] common/mlx5: share interrupt management Date: Fri, 1 Apr 2022 06:22:28 +0300 Message-ID: <20220401032232.1267376-3-spiked@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220401032232.1267376-1-spiked@nvidia.com> References: <20220401032232.1267376-1-spiked@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3b7499ba-4384-4bdf-7698-08da138eef92 X-MS-TrafficTypeDiagnostic: MWHPR12MB1838:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2022 03:23:05.0421 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b7499ba-4384-4bdf-7698-08da138eef92 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1838 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org There are many duplicate code of creating and initializing rte_intr_handle. Add a new mlx5_os API to do this, replace all PMD related code with this API. Signed-off-by: Spike Du --- drivers/common/mlx5/linux/mlx5_common_os.c | 131 ++++++++++++++++++++++++++ drivers/common/mlx5/linux/mlx5_common_os.h | 11 +++ drivers/common/mlx5/version.map | 3 +- drivers/common/mlx5/windows/mlx5_common_os.h | 24 +++++ drivers/net/mlx5/linux/mlx5_ethdev_os.c | 71 -------------- drivers/net/mlx5/linux/mlx5_os.c | 132 ++++++--------------------- drivers/net/mlx5/linux/mlx5_socket.c | 53 ++--------- drivers/net/mlx5/mlx5.h | 2 - drivers/net/mlx5/mlx5_txpp.c | 28 ++---- drivers/net/mlx5/windows/mlx5_ethdev_os.c | 22 ----- drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 52 ++--------- 11 files changed, 217 insertions(+), 312 deletions(-) diff --git a/drivers/common/mlx5/linux/mlx5_common_os.c b/drivers/common/mlx5/linux/mlx5_common_os.c index 030ceb5..6e7c59b 100644 --- a/drivers/common/mlx5/linux/mlx5_common_os.c +++ b/drivers/common/mlx5/linux/mlx5_common_os.c @@ -11,6 +11,7 @@ #endif #include #include +#include #include #include @@ -952,3 +953,133 @@ claim_zero(mlx5_glue->dereg_mr(pmd_mr->obj)); memset(pmd_mr, 0, sizeof(*pmd_mr)); } + +/** + * Rte_intr_handle create and init helper. + * + * @param[in] mode + * interrupt instance can be shared between primary and secondary + * processes or not. + * @param[in] set_fd_nonblock + * Whether to set fd to O_NONBLOCK. + * @param[in] fd + * Fd to set in created intr_handle. + * @param[in] cb + * Callback to register for intr_handle. + * @param[in] cb_arg + * Callback argument for cb. + * + * @return + * - Interrupt handle on success. + * - NULL on failure, with rte_errno set. + */ +struct rte_intr_handle * +mlx5_os_interrupt_handler_create(int mode, bool set_fd_nonblock, int fd, + rte_intr_callback_fn cb, void *cb_arg) +{ + struct rte_intr_handle *tmp_intr_handle; + int ret, flags; + + tmp_intr_handle = rte_intr_instance_alloc(mode); + if (!tmp_intr_handle) { + rte_errno = ENOMEM; + goto err; + } + if (set_fd_nonblock) { + flags = fcntl(fd, F_GETFL); + ret = fcntl(fd, F_SETFL, flags | O_NONBLOCK); + if (ret) { + rte_errno = errno; + goto err; + } + } + ret = rte_intr_fd_set(tmp_intr_handle, fd); + if (ret) + goto err; + ret = rte_intr_type_set(tmp_intr_handle, RTE_INTR_HANDLE_EXT); + if (ret) + goto err; + ret = rte_intr_callback_register(tmp_intr_handle, cb, cb_arg); + if (ret) { + rte_errno = -ret; + goto err; + } + return tmp_intr_handle; +err: + if (tmp_intr_handle) + rte_intr_instance_free(tmp_intr_handle); + return NULL; +} + +/* Safe unregistration for interrupt callback. */ +static void +mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, + rte_intr_callback_fn cb_fn, void *cb_arg) +{ + uint64_t twait = 0; + uint64_t start = 0; + + do { + int ret; + + ret = rte_intr_callback_unregister(handle, cb_fn, cb_arg); + if (ret >= 0) + return; + if (ret != -EAGAIN) { + DRV_LOG(INFO, "failed to unregister interrupt" + " handler (error: %d)", ret); + MLX5_ASSERT(false); + return; + } + if (twait) { + struct timespec onems; + + /* Wait one millisecond and try again. */ + onems.tv_sec = 0; + onems.tv_nsec = NS_PER_S / MS_PER_S; + nanosleep(&onems, 0); + /* Check whether one second elapsed. */ + if ((rte_get_timer_cycles() - start) <= twait) + continue; + } else { + /* + * We get the amount of timer ticks for one second. + * If this amount elapsed it means we spent one + * second in waiting. This branch is executed once + * on first iteration. + */ + twait = rte_get_timer_hz(); + MLX5_ASSERT(twait); + } + /* + * Timeout elapsed, show message (once a second) and retry. + * We have no other acceptable option here, if we ignore + * the unregistering return code the handler will not + * be unregistered, fd will be closed and we may get the + * crush. Hanging and messaging in the loop seems not to be + * the worst choice. + */ + DRV_LOG(INFO, "Retrying to unregister interrupt handler"); + start = rte_get_timer_cycles(); + } while (true); +} + +/** + * Rte_intr_handle destroy helper. + * + * @param[in] intr_handle + * Rte_intr_handle to destroy. + * @param[in] cb + * Callback which is registered to intr_handle. + * @param[in] cb_arg + * Callback argument for cb. + * + */ +void +mlx5_os_interrupt_handler_destroy(struct rte_intr_handle *intr_handle, + rte_intr_callback_fn cb, void *cb_arg) +{ + if (rte_intr_fd_get(intr_handle) >= 0) + mlx5_intr_callback_unregister(intr_handle, cb, cb_arg); + rte_intr_instance_free(intr_handle); +} diff --git a/drivers/common/mlx5/linux/mlx5_common_os.h b/drivers/common/mlx5/linux/mlx5_common_os.h index 27f1192..479bb3c 100644 --- a/drivers/common/mlx5/linux/mlx5_common_os.h +++ b/drivers/common/mlx5/linux/mlx5_common_os.h @@ -15,6 +15,7 @@ #include #include #include +#include #include "mlx5_autoconf.h" #include "mlx5_glue.h" @@ -299,4 +300,14 @@ int mlx5_get_device_guid(const struct rte_pci_addr *dev, uint8_t *guid, size_t len); +__rte_internal +struct rte_intr_handle * +mlx5_os_interrupt_handler_create(int mode, bool set_fd_nonblock, int fd, + rte_intr_callback_fn cb, void *cb_arg); + +__rte_internal +void +mlx5_os_interrupt_handler_destroy(struct rte_intr_handle *intr_handle, + rte_intr_callback_fn cb, void *cb_arg); + #endif /* RTE_PMD_MLX5_COMMON_OS_H_ */ diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index a23a30a..2900544 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -152,6 +152,7 @@ INTERNAL { mlx5_mp_req_mempool_reg; mlx5_mr_mempool2mr_bh; mlx5_mr_mempool_populate_cache; - + mlx5_os_interrupt_handler_create; # WINDOWS_NO_EXPORT + mlx5_os_interrupt_handler_destroy; # WINDOWS_NO_EXPORT local: *; }; diff --git a/drivers/common/mlx5/windows/mlx5_common_os.h b/drivers/common/mlx5/windows/mlx5_common_os.h index ee7973f..e9e9108 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.h +++ b/drivers/common/mlx5/windows/mlx5_common_os.h @@ -9,6 +9,7 @@ #include #include +#include #include "mlx5_autoconf.h" #include "mlx5_glue.h" @@ -253,4 +254,27 @@ __rte_internal int mlx5_os_umem_dereg(void *pumem); +static inline struct rte_intr_handle * +mlx5_os_interrupt_handler_create(int mode, bool set_fd_nonblock, int fd, + rte_intr_callback_fn cb, void *cb_arg) +{ + (void)mode; + (void)set_fd_nonblock; + (void)fd; + (void)cb; + (void)cb_arg; + rte_errno = ENOTSUP; + return NULL; +} + +static inline void +mlx5_os_interrupt_handler_destroy(struct rte_intr_handle *intr_handle, + rte_intr_callback_fn cb, void *cb_arg) +{ + (void)intr_handle; + (void)cb; + (void)cb_arg; +} + + #endif /* RTE_PMD_MLX5_COMMON_OS_H_ */ diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c index 8fe73f1..a276b2b 100644 --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c @@ -881,77 +881,6 @@ struct ethtool_link_settings { } } -/* - * Unregister callback handler safely. The handler may be active - * while we are trying to unregister it, in this case code -EAGAIN - * is returned by rte_intr_callback_unregister(). This routine checks - * the return code and tries to unregister handler again. - * - * @param handle - * interrupt handle - * @param cb_fn - * pointer to callback routine - * @cb_arg - * opaque callback parameter - */ -void -mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, - rte_intr_callback_fn cb_fn, void *cb_arg) -{ - /* - * Try to reduce timeout management overhead by not calling - * the timer related routines on the first iteration. If the - * unregistering succeeds on first call there will be no - * timer calls at all. - */ - uint64_t twait = 0; - uint64_t start = 0; - - do { - int ret; - - ret = rte_intr_callback_unregister(handle, cb_fn, cb_arg); - if (ret >= 0) - return; - if (ret != -EAGAIN) { - DRV_LOG(INFO, "failed to unregister interrupt" - " handler (error: %d)", ret); - MLX5_ASSERT(false); - return; - } - if (twait) { - struct timespec onems; - - /* Wait one millisecond and try again. */ - onems.tv_sec = 0; - onems.tv_nsec = NS_PER_S / MS_PER_S; - nanosleep(&onems, 0); - /* Check whether one second elapsed. */ - if ((rte_get_timer_cycles() - start) <= twait) - continue; - } else { - /* - * We get the amount of timer ticks for one second. - * If this amount elapsed it means we spent one - * second in waiting. This branch is executed once - * on first iteration. - */ - twait = rte_get_timer_hz(); - MLX5_ASSERT(twait); - } - /* - * Timeout elapsed, show message (once a second) and retry. - * We have no other acceptable option here, if we ignore - * the unregistering return code the handler will not - * be unregistered, fd will be closed and we may get the - * crush. Hanging and messaging in the loop seems not to be - * the worst choice. - */ - DRV_LOG(INFO, "Retrying to unregister interrupt handler"); - start = rte_get_timer_cycles(); - } while (true); -} - /** * Handle DEVX interrupts from the NIC. * This function is probably called from the DPDK host thread. diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index ff65efb..6274a42 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -2494,40 +2494,6 @@ mlx5_pmd_socket_uninit(); } -static int -mlx5_os_dev_shared_handler_install_lsc(struct mlx5_dev_ctx_shared *sh) -{ - int nlsk_fd, flags, ret; - - nlsk_fd = mlx5_nl_init(NETLINK_ROUTE, RTMGRP_LINK); - if (nlsk_fd < 0) { - DRV_LOG(ERR, "Failed to create a socket for Netlink events: %s", - rte_strerror(rte_errno)); - return -1; - } - flags = fcntl(nlsk_fd, F_GETFL); - ret = fcntl(nlsk_fd, F_SETFL, flags | O_NONBLOCK); - if (ret != 0) { - DRV_LOG(ERR, "Failed to make Netlink event socket non-blocking: %s", - strerror(errno)); - rte_errno = errno; - goto error; - } - rte_intr_type_set(sh->intr_handle_nl, RTE_INTR_HANDLE_EXT); - rte_intr_fd_set(sh->intr_handle_nl, nlsk_fd); - if (rte_intr_callback_register(sh->intr_handle_nl, - mlx5_dev_interrupt_handler_nl, - sh) != 0) { - DRV_LOG(ERR, "Failed to register Netlink events interrupt"); - rte_intr_fd_set(sh->intr_handle_nl, -1); - goto error; - } - return 0; -error: - close(nlsk_fd); - return -1; -} - /** * Install shared asynchronous device events handler. * This function is implemented to support event sharing @@ -2539,76 +2505,47 @@ void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) { - int ret; - int flags; struct ibv_context *ctx = sh->cdev->ctx; + int nlsk_fd; - sh->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); - if (sh->intr_handle == NULL) { - DRV_LOG(ERR, "Fail to allocate intr_handle"); - rte_errno = ENOMEM; + sh->intr_handle = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_SHARED, true, + ctx->async_fd, mlx5_dev_interrupt_handler, sh); + if (!sh->intr_handle) { + DRV_LOG(ERR, "Failed to allocate intr_handle."); return; } - rte_intr_fd_set(sh->intr_handle, -1); - - flags = fcntl(ctx->async_fd, F_GETFL); - ret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK); - if (ret) { - DRV_LOG(INFO, "failed to change file descriptor async event" - " queue"); - } else { - rte_intr_fd_set(sh->intr_handle, ctx->async_fd); - rte_intr_type_set(sh->intr_handle, RTE_INTR_HANDLE_EXT); - if (rte_intr_callback_register(sh->intr_handle, - mlx5_dev_interrupt_handler, sh)) { - DRV_LOG(INFO, "Fail to install the shared interrupt."); - rte_intr_fd_set(sh->intr_handle, -1); - } + nlsk_fd = mlx5_nl_init(NETLINK_ROUTE, RTMGRP_LINK); + if (nlsk_fd < 0) { + DRV_LOG(ERR, "Failed to create a socket for Netlink events: %s", + rte_strerror(rte_errno)); + return; } - sh->intr_handle_nl = rte_intr_instance_alloc - (RTE_INTR_INSTANCE_F_SHARED); + sh->intr_handle_nl = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_SHARED, true, + nlsk_fd, mlx5_dev_interrupt_handler_nl, sh); if (sh->intr_handle_nl == NULL) { DRV_LOG(ERR, "Fail to allocate intr_handle"); - rte_errno = ENOMEM; return; } - rte_intr_fd_set(sh->intr_handle_nl, -1); - if (mlx5_os_dev_shared_handler_install_lsc(sh) < 0) { - DRV_LOG(INFO, "Fail to install the shared Netlink event handler."); - rte_intr_fd_set(sh->intr_handle_nl, -1); - } if (sh->cdev->config.devx) { #ifdef HAVE_IBV_DEVX_ASYNC - sh->intr_handle_devx = - rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); - if (!sh->intr_handle_devx) { - DRV_LOG(ERR, "Fail to allocate intr_handle"); - rte_errno = ENOMEM; - return; - } - rte_intr_fd_set(sh->intr_handle_devx, -1); + struct mlx5dv_devx_cmd_comp *devx_comp; + sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx); - struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; + devx_comp = sh->devx_comp; if (!devx_comp) { DRV_LOG(INFO, "failed to allocate devx_comp."); return; } - flags = fcntl(devx_comp->fd, F_GETFL); - ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); - if (ret) { - DRV_LOG(INFO, "failed to change file descriptor" - " devx comp"); + sh->intr_handle_devx = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_SHARED, true, + devx_comp->fd, + mlx5_dev_interrupt_handler_devx, sh); + if (!sh->intr_handle_devx) { + DRV_LOG(ERR, "Failed to allocate intr_handle."); return; } - rte_intr_fd_set(sh->intr_handle_devx, devx_comp->fd); - rte_intr_type_set(sh->intr_handle_devx, - RTE_INTR_HANDLE_EXT); - if (rte_intr_callback_register(sh->intr_handle_devx, - mlx5_dev_interrupt_handler_devx, sh)) { - DRV_LOG(INFO, "Fail to install the devx shared" - " interrupt."); - rte_intr_fd_set(sh->intr_handle_devx, -1); - } #endif /* HAVE_IBV_DEVX_ASYNC */ } } @@ -2624,24 +2561,13 @@ void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) { - int nlsk_fd; - - if (rte_intr_fd_get(sh->intr_handle) >= 0) - mlx5_intr_callback_unregister(sh->intr_handle, - mlx5_dev_interrupt_handler, sh); - rte_intr_instance_free(sh->intr_handle); - nlsk_fd = rte_intr_fd_get(sh->intr_handle_nl); - if (nlsk_fd >= 0) { - mlx5_intr_callback_unregister - (sh->intr_handle_nl, mlx5_dev_interrupt_handler_nl, sh); - close(nlsk_fd); - } - rte_intr_instance_free(sh->intr_handle_nl); + mlx5_os_interrupt_handler_destroy(sh->intr_handle, + mlx5_dev_interrupt_handler, sh); + mlx5_os_interrupt_handler_destroy(sh->intr_handle_nl, + mlx5_dev_interrupt_handler_nl, sh); #ifdef HAVE_IBV_DEVX_ASYNC - if (rte_intr_fd_get(sh->intr_handle_devx) >= 0) - rte_intr_callback_unregister(sh->intr_handle_devx, - mlx5_dev_interrupt_handler_devx, sh); - rte_intr_instance_free(sh->intr_handle_devx); + mlx5_os_interrupt_handler_destroy(sh->intr_handle_devx, + mlx5_dev_interrupt_handler_devx, sh); if (sh->devx_comp) mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); #endif diff --git a/drivers/net/mlx5/linux/mlx5_socket.c b/drivers/net/mlx5/linux/mlx5_socket.c index 4882e5f..0e01aff 100644 --- a/drivers/net/mlx5/linux/mlx5_socket.c +++ b/drivers/net/mlx5/linux/mlx5_socket.c @@ -134,51 +134,6 @@ } /** - * Install interrupt handler. - * - * @param dev - * Pointer to Ethernet device. - * @return - * 0 on success, a negative errno value otherwise. - */ -static int -mlx5_pmd_interrupt_handler_install(void) -{ - MLX5_ASSERT(server_socket != -1); - - server_intr_handle = - rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE); - if (server_intr_handle == NULL) { - DRV_LOG(ERR, "Fail to allocate intr_handle"); - return -ENOMEM; - } - if (rte_intr_fd_set(server_intr_handle, server_socket)) - return -rte_errno; - - if (rte_intr_type_set(server_intr_handle, RTE_INTR_HANDLE_EXT)) - return -rte_errno; - - return rte_intr_callback_register(server_intr_handle, - mlx5_pmd_socket_handle, NULL); -} - -/** - * Uninstall interrupt handler. - */ -static void -mlx5_pmd_interrupt_handler_uninstall(void) -{ - if (server_socket != -1) { - mlx5_intr_callback_unregister(server_intr_handle, - mlx5_pmd_socket_handle, - NULL); - } - rte_intr_fd_set(server_intr_handle, 0); - rte_intr_type_set(server_intr_handle, RTE_INTR_HANDLE_UNKNOWN); - rte_intr_instance_free(server_intr_handle); -} - -/** * Initialise the socket to communicate with external tools. * * @return @@ -224,7 +179,10 @@ strerror(errno)); goto remove; } - if (mlx5_pmd_interrupt_handler_install()) { + server_intr_handle = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_PRIVATE, false, + server_socket, mlx5_pmd_socket_handle, NULL); + if (server_intr_handle == NULL) { DRV_LOG(WARNING, "cannot register interrupt handler for mlx5 socket: %s", strerror(errno)); goto remove; @@ -248,7 +206,8 @@ { if (server_socket == -1) return; - mlx5_pmd_interrupt_handler_uninstall(); + mlx5_os_interrupt_handler_destroy(server_intr_handle, + mlx5_pmd_socket_handle, NULL); claim_zero(close(server_socket)); server_socket = -1; MKSTR(path, MLX5_SOCKET_PATH, getpid()); diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index f3e6682..4821ff0 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1678,8 +1678,6 @@ int mlx5_sysfs_switch_info(unsigned int ifindex, struct mlx5_switch_info *info); void mlx5_translate_port_name(const char *port_name_in, struct mlx5_switch_info *port_info_out); -void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, - rte_intr_callback_fn cb_fn, void *cb_arg); int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex, char *ifname); int mlx5_get_module_info(struct rte_eth_dev *dev, diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c index fe74317..f853a67 100644 --- a/drivers/net/mlx5/mlx5_txpp.c +++ b/drivers/net/mlx5/mlx5_txpp.c @@ -741,11 +741,8 @@ static void mlx5_txpp_stop_service(struct mlx5_dev_ctx_shared *sh) { - if (!rte_intr_fd_get(sh->txpp.intr_handle)) - return; - mlx5_intr_callback_unregister(sh->txpp.intr_handle, - mlx5_txpp_interrupt_handler, sh); - rte_intr_instance_free(sh->txpp.intr_handle); + mlx5_os_interrupt_handler_destroy(sh->txpp.intr_handle, + mlx5_txpp_interrupt_handler, sh); } /* Attach interrupt handler and fires first request to Rearm Queue. */ @@ -769,23 +766,12 @@ rte_errno = errno; return -rte_errno; } - sh->txpp.intr_handle = - rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); - if (sh->txpp.intr_handle == NULL) { - DRV_LOG(ERR, "Fail to allocate intr_handle"); - return -ENOMEM; - } fd = mlx5_os_get_devx_channel_fd(sh->txpp.echan); - if (rte_intr_fd_set(sh->txpp.intr_handle, fd)) - return -rte_errno; - - if (rte_intr_type_set(sh->txpp.intr_handle, RTE_INTR_HANDLE_EXT)) - return -rte_errno; - - if (rte_intr_callback_register(sh->txpp.intr_handle, - mlx5_txpp_interrupt_handler, sh)) { - rte_intr_fd_set(sh->txpp.intr_handle, 0); - DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno); + sh->txpp.intr_handle = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_SHARED, false, + fd, mlx5_txpp_interrupt_handler, sh); + if (!sh->txpp.intr_handle) { + DRV_LOG(ERR, "Fail to allocate intr_handle"); return -rte_errno; } /* Subscribe CQ event to the event channel controlled by the driver. */ diff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c index c6315ce..b52faea 100644 --- a/drivers/net/mlx5/windows/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c @@ -117,28 +117,6 @@ return -ENOTSUP; } -/* - * Unregister callback handler safely. The handler may be active - * while we are trying to unregister it, in this case code -EAGAIN - * is returned by rte_intr_callback_unregister(). This routine checks - * the return code and tries to unregister handler again. - * - * @param handle - * interrupt handle - * @param cb_fn - * pointer to callback routine - * @cb_arg - * opaque callback parameter - */ -void -mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, - rte_intr_callback_fn cb_fn, void *cb_arg) -{ - RTE_SET_USED(handle); - RTE_SET_USED(cb_fn); - RTE_SET_USED(cb_arg); -} - /** * DPDK callback to get flow control status. * diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c index 3416797..2ca48f5 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c @@ -59,26 +59,10 @@ mlx5_vdpa_virtq_unset(struct mlx5_vdpa_virtq *virtq) { unsigned int i; - int retries = MLX5_VDPA_INTR_RETRIES; - int ret = -EAGAIN; - - if (rte_intr_fd_get(virtq->intr_handle) != -1) { - while (retries-- && ret == -EAGAIN) { - ret = rte_intr_callback_unregister(virtq->intr_handle, - mlx5_vdpa_virtq_handler, - virtq); - if (ret == -EAGAIN) { - DRV_LOG(DEBUG, "Try again to unregister fd %d " - "of virtq %d interrupt, retries = %d.", - rte_intr_fd_get(virtq->intr_handle), - (int)virtq->index, retries); - - usleep(MLX5_VDPA_INTR_RETRIES_USEC); - } - } - rte_intr_fd_set(virtq->intr_handle, -1); - } - rte_intr_instance_free(virtq->intr_handle); + int ret; + + mlx5_os_interrupt_handler_destroy(virtq->intr_handle, + mlx5_vdpa_virtq_handler, virtq); if (virtq->virtq) { ret = mlx5_vdpa_virtq_stop(virtq->priv, virtq->index); if (ret) @@ -342,35 +326,13 @@ virtq->priv = priv; rte_write32(virtq->index, priv->virtq_db_addr); /* Setup doorbell mapping. */ - virtq->intr_handle = - rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); + virtq->intr_handle = mlx5_os_interrupt_handler_create( + RTE_INTR_INSTANCE_F_SHARED, false, + vq.kickfd, mlx5_vdpa_virtq_handler, virtq); if (virtq->intr_handle == NULL) { DRV_LOG(ERR, "Fail to allocate intr_handle"); goto error; } - - if (rte_intr_fd_set(virtq->intr_handle, vq.kickfd)) - goto error; - - if (rte_intr_fd_get(virtq->intr_handle) == -1) { - DRV_LOG(WARNING, "Virtq %d kickfd is invalid.", index); - } else { - if (rte_intr_type_set(virtq->intr_handle, RTE_INTR_HANDLE_EXT)) - goto error; - - if (rte_intr_callback_register(virtq->intr_handle, - mlx5_vdpa_virtq_handler, - virtq)) { - rte_intr_fd_set(virtq->intr_handle, -1); - DRV_LOG(ERR, "Failed to register virtq %d interrupt.", - index); - goto error; - } else { - DRV_LOG(DEBUG, "Register fd %d interrupt for virtq %d.", - rte_intr_fd_get(virtq->intr_handle), - index); - } - } /* Subscribe virtq error event. */ virtq->version++; cookie = ((uint64_t)virtq->version << 32) + index; From patchwork Fri Apr 1 03:22:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Spike Du X-Patchwork-Id: 109054 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D7D08A0503; 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Fri, 1 Apr 2022 03:23:07 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 31 Mar 2022 20:23:05 -0700 From: Spike Du To: , , , CC: , Subject: [RFC 3/6] net/mlx5: add LWM event handling support Date: Fri, 1 Apr 2022 06:22:29 +0300 Message-ID: <20220401032232.1267376-4-spiked@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220401032232.1267376-1-spiked@nvidia.com> References: <20220401032232.1267376-1-spiked@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7acbb138-8a48-484e-e9d7-08da138ef154 X-MS-TrafficTypeDiagnostic: DM5PR12MB2533:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2022 03:23:08.0098 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7acbb138-8a48-484e-e9d7-08da138ef154 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2533 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When LWM meets RQ WQE, the kernel driver raises an event to SW. Use devx event_channel to catch this and to notify the user. Allocate this channel per shared device. The channel has a cookie that informs the specific event port and queue. Signed-off-by: Spike Du --- drivers/net/mlx5/mlx5.c | 61 ++++++++++++++++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5.h | 7 +++++ drivers/net/mlx5/mlx5_devx.c | 47 ++++++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_rx.c | 29 +++++++++++++++++++++ drivers/net/mlx5/mlx5_rx.h | 7 +++++ 5 files changed, 151 insertions(+) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 72b1e35..334223e 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include #include @@ -1521,6 +1523,64 @@ struct mlx5_dev_ctx_shared * } /** + * Create LWM event_channel and interrupt handle for shared device + * context. All rxqs sharing the device context share the event_channel. + * A callback is registered in interrupt thread to receive the LWM event. + * + * @param[in] priv + * Pointer to mlx5_priv instance. + * + * @return + * 0 on success, negative with rte_errno set. + */ +int +mlx5_lwm_setup(struct mlx5_priv *priv) +{ + int fd_lwm; + + pthread_mutex_init(&priv->sh->lwm_config_lock, NULL); + priv->sh->devx_channel_lwm = mlx5_os_devx_create_event_channel + (priv->sh->cdev->ctx, + MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA); + if (!priv->sh->devx_channel_lwm) + goto err; + fd_lwm = mlx5_os_get_devx_channel_fd(priv->sh->devx_channel_lwm); + priv->sh->intr_handle_lwm = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_SHARED, true, + fd_lwm, mlx5_dev_interrupt_handler_lwm, priv); + if (!priv->sh->intr_handle_lwm) + goto err; + return 0; +err: + mlx5_lwm_unset(priv->sh); + return -rte_errno; +} + +/** + * Destroy LWM event_channel and interrupt handle for shared device + * context before free this context. The interrupt handler is also + * unregistered. + * + * @param[in] sh + * Pointer to shared device context. + */ +void +mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh) +{ + if (sh->intr_handle_lwm) { + mlx5_os_interrupt_handler_destroy(sh->intr_handle_lwm, + mlx5_dev_interrupt_handler_lwm, (void *)-1); + sh->intr_handle_lwm = NULL; + } + if (sh->devx_channel_lwm) { + mlx5_os_devx_destroy_event_channel + (sh->devx_channel_lwm); + sh->devx_channel_lwm = NULL; + } + pthread_mutex_destroy(&sh->lwm_config_lock); +} + +/** * Free shared IB device context. Decrement counter and if zero free * all allocated resources and close handles. * @@ -1597,6 +1657,7 @@ struct mlx5_dev_ctx_shared * claim_zero(mlx5_devx_cmd_destroy(sh->td)); MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL); pthread_mutex_destroy(&sh->txpp.mutex); + mlx5_lwm_unset(sh); mlx5_free(sh); return; exit: diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 4821ff0..515ff33 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1264,6 +1264,9 @@ struct mlx5_dev_ctx_shared { struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */ unsigned int flow_max_priority; enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; + void *devx_channel_lwm; + struct rte_intr_handle *intr_handle_lwm; + pthread_mutex_t lwm_config_lock; /* Availability of mreg_c's. */ struct mlx5_dev_shared_port port[]; /* per device port data array. */ }; @@ -1401,6 +1404,7 @@ enum mlx5_txq_modify_type { }; struct mlx5_rxq_priv; +struct mlx5_priv; /* HW objects operations structure. */ struct mlx5_obj_ops { @@ -1409,6 +1413,7 @@ struct mlx5_obj_ops { int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); int (*rxq_obj_modify)(struct mlx5_rxq_priv *rxq, uint8_t type); void (*rxq_obj_release)(struct mlx5_rxq_priv *rxq); + int (*rxq_event_get_lwm)(struct mlx5_priv *priv, int *rxq_idx, int *port_id); int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, struct mlx5_ind_table_obj *ind_tbl); int (*ind_table_modify)(struct rte_eth_dev *dev, @@ -1599,6 +1604,8 @@ int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, bool mlx5_is_hpf(struct rte_eth_dev *dev); bool mlx5_is_sf_repr(struct rte_eth_dev *dev); void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); +int mlx5_lwm_setup(struct mlx5_priv *priv); +void mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh); /* Macro to iterate over all valid ports for mlx5 driver. */ #define MLX5_ETH_FOREACH_DEV(port_id, dev) \ diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index d6de882..e1e5d2d 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -230,6 +230,52 @@ } /** + * Get LWM event for shared context, return the correct port/rxq for this event. + * + * @param priv + * Mlx5_priv object. + * @param rxq_idx [out] + * Which rxq gets this event. + * @param port_id [out] + * Which port gets this event. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_rx_devx_get_event_lwm(struct mlx5_priv *priv, int *rxq_idx, int *port_id) +{ +#ifdef HAVE_IBV_DEVX_EVENT + union { + struct mlx5dv_devx_async_event_hdr event_resp; + uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128]; + } out; + int ret; + + memset(&out, 0, sizeof(out)); + ret = mlx5_glue->devx_get_event(priv->sh->devx_channel_lwm, + &out.event_resp, + sizeof(out.buf)); + if (ret < 0) { + rte_errno = errno; + DRV_LOG(WARNING, "%s err\n", __func__); + return -rte_errno; + } + *port_id = (((uint32_t)out.event_resp.cookie) >> + LWM_COOKIE_PORTID_OFFSET) & LWM_COOKIE_PORTID_MASK; + *rxq_idx = (((uint32_t)out.event_resp.cookie) >> + LWM_COOKIE_RXQID_OFFSET) & LWM_COOKIE_RXQID_MASK; + return 0; +#else + (void)priv; + (void)rxq_idx; + (void)port_id; + rte_errno = ENOTSUP; + return -rte_errno; +#endif /* HAVE_IBV_DEVX_EVENT */ +} + +/** * Create a RQ object using DevX. * * @param rxq @@ -1413,6 +1459,7 @@ struct mlx5_obj_ops devx_obj_ops = { .rxq_event_get = mlx5_rx_devx_get_event, .rxq_obj_modify = mlx5_devx_modify_rq, .rxq_obj_release = mlx5_rxq_devx_obj_release, + .rxq_event_get_lwm = mlx5_rx_devx_get_event_lwm, .ind_table_new = mlx5_devx_ind_table_new, .ind_table_modify = mlx5_devx_ind_table_modify, .ind_table_destroy = mlx5_devx_ind_table_destroy, diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c index e5eea0a..f72364e 100644 --- a/drivers/net/mlx5/mlx5_rx.c +++ b/drivers/net/mlx5/mlx5_rx.c @@ -1187,3 +1187,32 @@ int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc) { return -ENOTSUP; } + +/** + * Rte interrupt handler for LWM event. + * It first checks if the event arrives, if so invokes the callback registered + * for LWM event in the rxq. + * + * @param args + * Generic pointer to mlx5_priv. + */ +void +mlx5_dev_interrupt_handler_lwm(void *args) +{ + struct mlx5_priv *priv = args; + struct mlx5_rxq_priv *rxq; + struct rte_eth_dev *dev; + int ret, rxq_idx = 0, port_id = 0; + + ret = priv->obj_ops.rxq_event_get_lwm(priv, &rxq_idx, &port_id); + if (unlikely(ret < 0)) { + DRV_LOG(WARNING, "Cannot get LWM event context."); + return; + } + DRV_LOG(INFO, "%s get LWM event, port_id:%d rxq_id:%d.", __func__, + port_id, rxq_idx); + dev = &rte_eth_devices[port_id]; + rxq = mlx5_rxq_get(dev, rxq_idx); + if (rxq && rxq->lwm_event_rxq_limit_reached) + rxq->lwm_event_rxq_limit_reached(port_id, rxq_idx); +} diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index 98d7cae..bf3c5e1 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -175,6 +175,7 @@ struct mlx5_rxq_priv { struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ uint32_t hairpin_status; /* Hairpin binding status. */ uint32_t lwm:16; + void (*lwm_event_rxq_limit_reached)(uint16_t port_id, uint16_t rxq_id); }; /* External RX queue descriptor. */ @@ -294,6 +295,7 @@ void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, struct rte_eth_burst_mode *mode); int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc); +void mlx5_dev_interrupt_handler_lwm(void *args); /* Vectorized version of mlx5_rx.c */ int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data); @@ -674,4 +676,9 @@ uint16_t mlx5_rx_burst_mprq_vec(void *dpdk_rxq, struct rte_mbuf **pkts, return !!__atomic_load_n(&rxq->refcnt, __ATOMIC_RELAXED); } +#define LWM_COOKIE_RXQID_OFFSET 0 +#define LWM_COOKIE_RXQID_MASK 0xffff +#define LWM_COOKIE_PORTID_OFFSET 16 +#define LWM_COOKIE_PORTID_MASK 0xffff + #endif /* RTE_PMD_MLX5_RX_H_ */ From patchwork Fri Apr 1 03:22:30 2022 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2022 03:23:11.6688 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0de93ee-0a45-4b11-031a-08da138ef388 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3112 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The new API allows setting/unsetting/modifying an LWM(limit watermark) event per Rxq. While the Rx queue fullness reaches the LWM limit, the driver catches an HW event and invokes the user callback. Signed-off-by: Spike Du --- doc/guides/nics/mlx5.rst | 4 ++ doc/guides/rel_notes/release_22_03.rst | 6 +++ drivers/common/mlx5/mlx5_prm.h | 1 + drivers/net/mlx5/mlx5_rx.c | 88 +++++++++++++++++++++++++++++++++- drivers/net/mlx5/mlx5_rx.h | 1 + drivers/net/mlx5/rte_pmd_mlx5.h | 32 +++++++++++++ drivers/net/mlx5/version.map | 1 + 7 files changed, 132 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index a734d10..0e983a6 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -92,6 +92,7 @@ Features - Connection tracking. - Sub-Function representors. - Sub-Function. +- Rx queue LWM (Limit WaterMark) configuration. Limitations @@ -507,6 +508,9 @@ Limitations - The NIC egress flow rules on representor port are not supported. +- LWM: + - Doesn't support shared Rx queue and Hairpin Rx queue. + Statistics ---------- diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst index 60e5b4f..0c9d3b6 100644 --- a/doc/guides/rel_notes/release_22_03.rst +++ b/doc/guides/rel_notes/release_22_03.rst @@ -187,6 +187,12 @@ New Features An API was added to get/set an asymmetric crypto session's user data. +* **Updated Mellanox mlx5 driver.** + + Updated the Mellanox mlx5 driver with new features and improvements, including: + + * Added Rx queue LWM(Limit WaterMark) support. + * **Updated Marvell cnxk crypto PMD.** * Added SHA256-HMAC support in lookaside protocol (IPsec) for CN10K. diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 44b1822..23b13e3 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3290,6 +3290,7 @@ struct mlx5_aso_wqe { enum { MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, + MLX5_EVENT_TYPE_SRQ_LIMIT_REACHED = 0x14, }; enum { diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c index f72364e..0390412 100644 --- a/drivers/net/mlx5/mlx5_rx.c +++ b/drivers/net/mlx5/mlx5_rx.c @@ -19,15 +19,16 @@ #include #include #include +#include #include "mlx5_autoconf.h" #include "mlx5_defs.h" #include "mlx5.h" #include "mlx5_utils.h" #include "mlx5_rxtx.h" +#include "mlx5_devx.h" #include "mlx5_rx.h" - static __rte_always_inline uint32_t rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe, volatile struct mlx5_mini_cqe8 *mcqe); @@ -1216,3 +1217,88 @@ int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc) if (rxq && rxq->lwm_event_rxq_limit_reached) rxq->lwm_event_rxq_limit_reached(port_id, rxq_idx); } + +int +rte_pmd_mlx5_config_rxq_lwm(uint16_t port_id, uint16_t rx_queue_id, + uint8_t lwm, + lwm_event_rxq_limit_reached_t cb) +{ + struct rte_eth_dev *dev = &rte_eth_devices[port_id]; + struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, rx_queue_id); + uint16_t event_nums[1] = {MLX5_EVENT_TYPE_SRQ_LIMIT_REACHED}; + struct mlx5_rxq_data *rxq_data; + struct mlx5_priv *priv; + uint32_t wqe_cnt; + uint64_t cookie; + int ret = 0; + + if (!rxq) { + rte_errno = EINVAL; + return -rte_errno; + } + rxq_data = &rxq->ctrl->rxq; + priv = rxq->priv; + /* Ensure the Rq is created by devx. */ + if (priv->obj_ops.rxq_obj_new != devx_obj_ops.rxq_obj_new) { + rte_errno = EINVAL; + return -rte_errno; + } + if (lwm > 99) { + DRV_LOG(WARNING, "Too big LWM configuration."); + rte_errno = E2BIG; + return -rte_errno; + } + /* Start config LWM. */ + pthread_mutex_lock(&priv->sh->lwm_config_lock); + if (rxq->lwm == 0 && lwm == 0) { + /* Both old/new values are 0, do nothing. */ + ret = 0; + goto end; + } + wqe_cnt = mlx5_rxq_mprq_enabled(rxq_data) + ? RTE_BIT32(rxq_data->cqe_n - rxq_data->log_strd_num) : + RTE_BIT32(rxq_data->cqe_n); + if (lwm) { + if (!priv->sh->devx_channel_lwm) { + ret = mlx5_lwm_setup(priv); + if (ret) { + DRV_LOG(WARNING, + "Failed to create shared_lwm."); + rte_errno = ENOMEM; + ret = -rte_errno; + goto end; + } + } + if (!rxq->lwm_devx_subscribed) { + cookie = ((uint32_t) + (port_id << LWM_COOKIE_PORTID_OFFSET)) | + (rx_queue_id << LWM_COOKIE_RXQID_OFFSET); + ret = mlx5_os_devx_subscribe_devx_event + (priv->sh->devx_channel_lwm, + rxq->devx_rq.rq->obj, + sizeof(event_nums), + event_nums, + cookie); + if (ret) { + rte_errno = rte_errno ? rte_errno : EINVAL; + ret = -rte_errno; + goto end; + } + rxq->lwm_devx_subscribed = 1; + } + } + /* Save LWM to rxq and send modfiy_rq devx command. */ + rxq->lwm = lwm * wqe_cnt / 100; + if (lwm && !rxq->lwm) { + /* With mprq, wqe_cnt may be < 100. */ + DRV_LOG(WARNING, "Too small LWM configuration."); + rte_errno = EINVAL; + ret = -rte_errno; + goto end; + } + rxq->lwm_event_rxq_limit_reached = lwm ? cb : NULL; + ret = mlx5_devx_modify_rq(rxq, MLX5_RXQ_MOD_RDY2RDY); +end: + pthread_mutex_unlock(&priv->sh->lwm_config_lock); + return ret; +} diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index bf3c5e1..5e56258 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -175,6 +175,7 @@ struct mlx5_rxq_priv { struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ uint32_t hairpin_status; /* Hairpin binding status. */ uint32_t lwm:16; + uint32_t lwm_devx_subscribed:1; void (*lwm_event_rxq_limit_reached)(uint16_t port_id, uint16_t rxq_id); }; diff --git a/drivers/net/mlx5/rte_pmd_mlx5.h b/drivers/net/mlx5/rte_pmd_mlx5.h index 6e7907e..4d2fb42 100644 --- a/drivers/net/mlx5/rte_pmd_mlx5.h +++ b/drivers/net/mlx5/rte_pmd_mlx5.h @@ -109,6 +109,38 @@ int rte_pmd_mlx5_external_rx_queue_id_map(uint16_t port_id, uint16_t dpdk_idx, int rte_pmd_mlx5_external_rx_queue_id_unmap(uint16_t port_id, uint16_t dpdk_idx); +typedef void (*lwm_event_rxq_limit_reached_t)(uint16_t port_id, + uint16_t rxq_id); +/** + * Arm an Rx queue LWM(limit watermark) event. + * While the Rx queue fullness reaches the LWM limit, the driver catches + * an HW event and invokes the user event callback. + * After the last event handling, the user needs to call this API again + * to arm an additional event. + * + * @param[in] port_id + * The port identifier of the Ethernet device. + * @param[in] rxq_id + * The rxq id. + * @param[in] lwm + * The LWM value, is defined by a percentage of the Rx queue size. + * [1-99] to set a new LWM (update the old value). + * 0 to unarm the event. + * @param[in] cb + * The LWM event callback. + * + * @return + * 0 : operation success. + * Otherwise: + * - ENOMEM - not enough memory to create LWM event channel. + * - EINVAL - the input Rxq is not created by devx. + * - E2BIG - lwm is bigger than 99. + */ +__rte_experimental +int rte_pmd_mlx5_config_rxq_lwm(uint16_t port_id, uint16_t rxq_id, + uint8_t lwm, + lwm_event_rxq_limit_reached_t cb); + #ifdef __cplusplus } #endif diff --git a/drivers/net/mlx5/version.map b/drivers/net/mlx5/version.map index 79cb79a..8c965dd 100644 --- a/drivers/net/mlx5/version.map +++ b/drivers/net/mlx5/version.map @@ -12,4 +12,5 @@ EXPERIMENTAL { # added in 22.03 rte_pmd_mlx5_external_rx_queue_id_map; rte_pmd_mlx5_external_rx_queue_id_unmap; + rte_pmd_mlx5_config_rxq_lwm; }; From patchwork Fri Apr 1 03:22:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Spike Du X-Patchwork-Id: 109056 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 49C6CA0503; Fri, 1 Apr 2022 05:23:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1D82342921; Fri, 1 Apr 2022 05:23:20 +0200 (CEST) Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam07on2056.outbound.protection.outlook.com [40.107.212.56]) by mails.dpdk.org (Postfix) with ESMTP id BAF3342911 for ; Fri, 1 Apr 2022 05:23:18 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2022 03:23:14.6195 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8344230f-fc40-47e9-3d91-08da138ef54a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3218 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Host port shaper can be configured with QSHR(QoS Shaper Host Register). Add check in build files to enable this function or not. The host shaper configuration affects all the ethdev ports belonging to the same host port. Host shaper can configure shaper rate and lwm-triggered for a host port. The shaper limits the rate of traffic from host port to wire port. If lwm-triggered is enabled, a 100Mbps shaper is enabled automatically when one of the host port's Rx queues receives LWM(Limit Watermark) event. Signed-off-by: Spike Du --- doc/guides/nics/mlx5.rst | 7 +++ doc/guides/rel_notes/release_22_03.rst | 1 + drivers/common/mlx5/linux/meson.build | 21 +++++-- drivers/common/mlx5/mlx5_prm.h | 25 ++++++++ drivers/net/mlx5/mlx5.h | 2 + drivers/net/mlx5/mlx5_rx.c | 104 +++++++++++++++++++++++++++++++++ drivers/net/mlx5/rte_pmd_mlx5.h | 30 ++++++++++ drivers/net/mlx5/version.map | 1 + 8 files changed, 187 insertions(+), 4 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 0e983a6..35210c1 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -93,6 +93,7 @@ Features - Sub-Function representors. - Sub-Function. - Rx queue LWM (Limit WaterMark) configuration. +- Host shaper support. Limitations @@ -511,6 +512,12 @@ Limitations - LWM: - Doesn't support shared Rx queue and Hairpin Rx queue. +- Host shaper: + + - Support BlueField series NIC from BlueField 2. + - When configure host shaper with MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED flag set, + only rate 0 and 100Mbps are supported. + Statistics ---------- diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst index 0c9d3b6..3ab4388 100644 --- a/doc/guides/rel_notes/release_22_03.rst +++ b/doc/guides/rel_notes/release_22_03.rst @@ -192,6 +192,7 @@ New Features Updated the Mellanox mlx5 driver with new features and improvements, including: * Added Rx queue LWM(Limit WaterMark) support. + * Added host shaper support. * **Updated Marvell cnxk crypto PMD.** diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build index ed48245..c88c184 100644 --- a/drivers/common/mlx5/linux/meson.build +++ b/drivers/common/mlx5/linux/meson.build @@ -16,8 +16,9 @@ if dlopen_ibverbs ] endif -libnames = [ 'mlx5', 'ibverbs' ] +libnames = [ 'mlx5', 'ibverbs', 'mtcr_ul' ] libs = [] +libmtcr_ul_found = false foreach libname:libnames lib = dependency('lib' + libname, static:static_ibverbs, required:false, method: 'pkg-config') if not lib.found() and not static_ibverbs @@ -28,10 +29,16 @@ foreach libname:libnames if not static_ibverbs and not dlopen_ibverbs ext_deps += lib endif + if libname == 'mtcr_ul' + libmtcr_ul_found = true + ext_deps += lib + endif else - build = false - reason = 'missing dependency, "' + libname + '"' - subdir_done() + if libname != 'mtcr_ul' + build = false + reason = 'missing dependency, "' + libname + '"' + subdir_done() + endif endif endforeach if static_ibverbs or dlopen_ibverbs @@ -205,6 +212,12 @@ has_sym_args = [ [ 'HAVE_MLX5_IBV_IMPORT_CTX_PD_AND_MR', 'infiniband/verbs.h', 'ibv_import_device' ], ] +if libmtcr_ul_found + has_sym_args += [ + [ 'HAVE_MLX5_MSTFLINT', 'mstflint/mtcr.h', + 'mopen'], + ] +endif config = configuration_data() foreach arg:has_sym_args config.set(arg[0], cc.has_header_symbol(arg[1], arg[2], dependencies: libs)) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 23b13e3..3559927 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3768,6 +3768,7 @@ enum { MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, + MLX5_QSHR_REGISTER_ID = 0x4030, }; struct mlx5_ifc_register_mtutc_bits { @@ -3782,6 +3783,30 @@ struct mlx5_ifc_register_mtutc_bits { u8 time_adjustment[0x20]; }; +struct mlx5_ifc_ets_global_config_register_bits { + u8 reserved_at_0[0x2]; + u8 rate_limit_update[0x1]; + u8 reserved_at_3[0x29]; + u8 max_bw_units[0x4]; + u8 reserved_at_48[0x8]; + u8 max_bw_value[0x8]; +}; + +#define ETS_GLOBAL_CONFIG_BW_UNIT_DISABLED 0x0 +#define ETS_GLOBAL_CONFIG_BW_UNIT_HUNDREDS_MBPS 0x3 +#define ETS_GLOBAL_CONFIG_BW_UNIT_GBPS 0x4 + +struct mlx5_ifc_register_qshr_bits { + u8 reserved_at_0[0x4]; + u8 connected_host[0x1]; + u8 vqos[0x1]; + u8 fast_response[0x1]; + u8 reserved_at_7[0x1]; + u8 local_port[0x8]; + u8 reserved_at_16[0x230]; + struct mlx5_ifc_ets_global_config_register_bits global_config; +}; + #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 515ff33..5dfd375 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1267,6 +1267,8 @@ struct mlx5_dev_ctx_shared { void *devx_channel_lwm; struct rte_intr_handle *intr_handle_lwm; pthread_mutex_t lwm_config_lock; + uint32_t host_shaper_rate:8; + uint32_t lwm_triggered:1; /* Availability of mreg_c's. */ struct mlx5_dev_shared_port port[]; /* per device port data array. */ }; diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c index 0390412..6d5d11b 100644 --- a/drivers/net/mlx5/mlx5_rx.c +++ b/drivers/net/mlx5/mlx5_rx.c @@ -28,6 +28,9 @@ #include "mlx5_rxtx.h" #include "mlx5_devx.h" #include "mlx5_rx.h" +#ifdef HAVE_MLX5_MSTFLINT +#include +#endif static __rte_always_inline uint32_t rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe, @@ -1302,3 +1305,104 @@ int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc) pthread_mutex_unlock(&priv->sh->lwm_config_lock); return ret; } + +/** + * Mlx5 access register function to configure host shaper. + * It calls API in libmtcr_ul to access QSHR(Qos Shaper Host Register) + * in firmware. + * + * @param dev + * Pointer to rte_eth_dev. + * @param lwm_triggered + * Flag to enable/disable lwm_triggered bit in QSHR. + * @param rate + * Host shaper rate, unit is 100Mbps, set to 0 means disable the shaper. + * @return + * 0 : operation success. + * Otherwise: + * - ENOENT - no ibdev interface. + * - EBUSY - the register access unit is busy. + * - EIO - the register access command meets IO error. + */ +static int +mlxreg_config_host_shaper(struct rte_eth_dev *dev, + bool lwm_triggered, uint8_t rate) +{ +#ifdef HAVE_MLX5_MSTFLINT + struct mlx5_priv *priv = dev->data->dev_private; + uint32_t data[MLX5_ST_SZ_DW(register_qshr)] = {0}; + int rc, retry_count = 3; + mfile *mf = NULL; + int status; + void *ptr; + + mf = mopen(priv->sh->ibdev_name); + if (!mf) { + DRV_LOG(WARNING, "mopen failed\n"); + rte_errno = ENOENT; + return -rte_errno; + } + MLX5_SET(register_qshr, data, connected_host, 1); + MLX5_SET(register_qshr, data, fast_response, lwm_triggered ? 1 : 0); + MLX5_SET(register_qshr, data, local_port, 1); + ptr = MLX5_ADDR_OF(register_qshr, data, global_config); + MLX5_SET(ets_global_config_register, ptr, rate_limit_update, 1); + MLX5_SET(ets_global_config_register, ptr, max_bw_units, + rate ? ETS_GLOBAL_CONFIG_BW_UNIT_HUNDREDS_MBPS : + ETS_GLOBAL_CONFIG_BW_UNIT_DISABLED); + MLX5_SET(ets_global_config_register, ptr, max_bw_value, rate); + do { + rc = maccess_reg(mf, + MLX5_QSHR_REGISTER_ID, + MACCESS_REG_METHOD_SET, + (u_int32_t *)&data[0], + sizeof(data), + sizeof(data), + sizeof(data), + &status); + if ((rc != ME_ICMD_STATUS_IFC_BUSY && + status != ME_REG_ACCESS_BAD_PARAM) || + !(mf->flags & MDEVS_REM)) { + break; + } + DRV_LOG(WARNING, "%s retry.", __func__); + usleep(10000); + } while (retry_count-- > 0); + mclose(mf); + rte_errno = (rc == ME_REG_ACCESS_DEV_BUSY) ? EBUSY : EIO; + return rc ? -rte_errno : 0; +#else + (void)dev; + (void)lwm_triggered; + (void)rate; + return -1; +#endif +} + +int rte_pmd_mlx5_config_host_shaper(int port_id, uint8_t rate, + uint32_t flags) +{ + struct rte_eth_dev *dev = &rte_eth_devices[port_id]; + struct mlx5_priv *priv = dev->data->dev_private; + bool lwm_triggered = + !!(flags & RTE_BIT32(MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED)); + + if (!lwm_triggered) { + priv->sh->host_shaper_rate = rate; + } else { + switch (rate) { + case 0: + /* Rate 0 means disable lwm_triggered. */ + priv->sh->lwm_triggered = 0; + break; + case 1: + /* Rate 1 means enable lwm_triggered. */ + priv->sh->lwm_triggered = 1; + break; + default: + return -ENOTSUP; + } + } + return mlxreg_config_host_shaper(dev, priv->sh->lwm_triggered, + priv->sh->host_shaper_rate); +} diff --git a/drivers/net/mlx5/rte_pmd_mlx5.h b/drivers/net/mlx5/rte_pmd_mlx5.h index 4d2fb42..3a32463 100644 --- a/drivers/net/mlx5/rte_pmd_mlx5.h +++ b/drivers/net/mlx5/rte_pmd_mlx5.h @@ -141,6 +141,36 @@ int rte_pmd_mlx5_config_rxq_lwm(uint16_t port_id, uint16_t rxq_id, uint8_t lwm, lwm_event_rxq_limit_reached_t cb); +/** + * The rate of the host port shaper will be updated directly at the next + * LWM event to the rate that comes with this flag set; set rate 0 + * to disable this rate update. + * Unset this flag to update the rate of the host port shaper directly in + * the API call; use rate 0 to disable the current shaper. + */ +#define MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED 0 + +/** + * Configure an HW shaper to limit Rx rate for a host port. + * The configuration will affect all the ethdev ports belonging to + * the same rte_device. + * + * @param[in] port_id + * The port identifier of the Ethernet device. + * @param[in] rate + * Unit is 100Mbps, setting the rate to 0 disables the shaper. + * @param[in] flags + * Host shaper flags. + * @return + * 0 : operation success. + * Otherwise: + * - ENOENT - no ibdev interface. + * - EBUSY - the register access unit is busy. + * - EIO - the register access command meets IO error. + */ +__rte_experimental +int rte_pmd_mlx5_config_host_shaper(int port_id, uint8_t rate, uint32_t flags); + #ifdef __cplusplus } #endif diff --git a/drivers/net/mlx5/version.map b/drivers/net/mlx5/version.map index 8c965dd..5029e19 100644 --- a/drivers/net/mlx5/version.map +++ b/drivers/net/mlx5/version.map @@ -13,4 +13,5 @@ EXPERIMENTAL { rte_pmd_mlx5_external_rx_queue_id_map; rte_pmd_mlx5_external_rx_queue_id_unmap; rte_pmd_mlx5_config_rxq_lwm; + rte_pmd_mlx5_config_host_shaper; }; From patchwork Fri Apr 1 03:22:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Spike Du X-Patchwork-Id: 109057 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 58C83A0503; Fri, 1 Apr 2022 05:23:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0CE604292C; Fri, 1 Apr 2022 05:23:27 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2077.outbound.protection.outlook.com [40.107.244.77]) by mails.dpdk.org (Postfix) with ESMTP id B611242918 for ; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2022 03:23:18.7877 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f1f3473-c213-43af-1d79-08da138ef7bf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT067.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1716 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add command line options to support LWM per-rxq configure. - Command syntax: set port rxq lwm set port host_shaper lwm_triggered <0|1> rate - Example commands: To configure LWM as 30% of rxq size on port 1 rxq 0: testpmd> set port 1 rxq 0 lwm 30 To disable LWM on port 1 rxq 0: testpmd> set port 1 rxq 0 lwm 0 To enable lwm_triggered on port 1 and disable current host shaper: testpmd> set port 1 host_shaper lwm_triggered 1 rate 0 To disable lwm_triggered and current host shaper on port 1: testpmd> set port 1 host_shaper lwm_triggered 0 rate 0 The rate unit is 100Mbps. To disable lwm_triggered and configure a shaper of 5Gbps on port 1: testpmd> set port 1 host_shaper lwm_triggered 0 rate 50 Add sample code to handle rxq LWM event, it delays a while so that rxq empties, then disables host shaper and rearms LWM event. Signed-off-by: Spike Du --- app/test-pmd/cmdline.c | 149 +++++++++++++++++++++++++++++++++++++++++++++++ app/test-pmd/config.c | 122 ++++++++++++++++++++++++++++++++++++++ app/test-pmd/meson.build | 3 + app/test-pmd/testpmd.c | 3 + app/test-pmd/testpmd.h | 5 ++ doc/guides/nics/mlx5.rst | 76 ++++++++++++++++++++++++ 6 files changed, 358 insertions(+) diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c index 7ab0575..8a5fe26 100644 --- a/app/test-pmd/cmdline.c +++ b/app/test-pmd/cmdline.c @@ -17807,6 +17807,151 @@ struct cmd_show_port_flow_transfer_proxy_result { } }; +#ifdef RTE_NET_MLX5 + +/* *** SET LIMIT WARTER MARK FOR A RXQ OF A PORT *** */ +struct cmd_rxq_lwm_result { + cmdline_fixed_string_t set; + cmdline_fixed_string_t port; + uint16_t port_num; + cmdline_fixed_string_t rxq; + uint16_t rxq_num; + cmdline_fixed_string_t lwm; + uint16_t lwm_num; +}; + +static void cmd_rxq_lwm_parsed(void *parsed_result, + __rte_unused struct cmdline *cl, + __rte_unused void *data) +{ + struct cmd_rxq_lwm_result *res = parsed_result; + int ret = 0; + + if ((strcmp(res->set, "set") == 0) && (strcmp(res->port, "port") == 0) + && (strcmp(res->rxq, "rxq") == 0) + && (strcmp(res->lwm, "lwm") == 0)) + ret = set_rxq_lwm(res->port_num, res->rxq_num, + res->lwm_num); + if (ret < 0) + printf("rxq_lwm_cmd error: (%s)\n", strerror(-ret)); + +} + +cmdline_parse_token_string_t cmd_rxq_lwm_set = + TOKEN_STRING_INITIALIZER(struct cmd_rxq_lwm_result, + set, "set"); +cmdline_parse_token_string_t cmd_rxq_lwm_port = + TOKEN_STRING_INITIALIZER(struct cmd_rxq_lwm_result, + port, "port"); +cmdline_parse_token_num_t cmd_rxq_lwm_portnum = + TOKEN_NUM_INITIALIZER(struct cmd_rxq_lwm_result, + port_num, RTE_UINT16); +cmdline_parse_token_string_t cmd_rxq_lwm_rxq = + TOKEN_STRING_INITIALIZER(struct cmd_rxq_lwm_result, + rxq, "rxq"); +cmdline_parse_token_num_t cmd_rxq_lwm_rxqnum = + TOKEN_NUM_INITIALIZER(struct cmd_rxq_lwm_result, + rxq_num, RTE_UINT8); +cmdline_parse_token_string_t cmd_rxq_lwm_lwm = + TOKEN_STRING_INITIALIZER(struct cmd_rxq_lwm_result, + lwm, "lwm"); +cmdline_parse_token_num_t cmd_rxq_lwm_lwmnum = + TOKEN_NUM_INITIALIZER(struct cmd_rxq_lwm_result, + lwm_num, RTE_UINT16); + +cmdline_parse_inst_t cmd_rxq_lwm = { + .f = cmd_rxq_lwm_parsed, + .data = (void *)0, + .help_str = "set port rxq lwm " + "Set lwm for rxq on port_id", + .tokens = { + (void *)&cmd_rxq_lwm_set, + (void *)&cmd_rxq_lwm_port, + (void *)&cmd_rxq_lwm_portnum, + (void *)&cmd_rxq_lwm_rxq, + (void *)&cmd_rxq_lwm_rxqnum, + (void *)&cmd_rxq_lwm_lwm, + (void *)&cmd_rxq_lwm_lwmnum, + NULL, + }, +}; + +/* *** SET HOST_SHAPER LWM TRIGGERED FOR A PORT *** */ +struct cmd_port_host_shaper_result { + cmdline_fixed_string_t set; + cmdline_fixed_string_t port; + uint16_t port_num; + cmdline_fixed_string_t host_shaper; + cmdline_fixed_string_t lwm_triggered; + uint16_t fr; + cmdline_fixed_string_t rate; + uint8_t rate_num; +}; + +static void cmd_port_host_shaper_parsed(void *parsed_result, + __rte_unused struct cmdline *cl, + __rte_unused void *data) +{ + struct cmd_port_host_shaper_result *res = parsed_result; + int ret = 0; + + if ((strcmp(res->set, "set") == 0) && (strcmp(res->port, "port") == 0) + && (strcmp(res->host_shaper, "host_shaper") == 0) + && (strcmp(res->lwm_triggered, "lwm_triggered") == 0) + && (strcmp(res->rate, "rate") == 0)) + ret = set_port_host_shaper(res->port_num, res->fr, + res->rate_num); + if (ret < 0) + printf("cmd_port_host_shaper error: (%s)\n", strerror(-ret)); + +} + +cmdline_parse_token_string_t cmd_port_host_shaper_set = + TOKEN_STRING_INITIALIZER(struct cmd_port_host_shaper_result, + set, "set"); +cmdline_parse_token_string_t cmd_port_host_shaper_port = + TOKEN_STRING_INITIALIZER(struct cmd_port_host_shaper_result, + port, "port"); +cmdline_parse_token_num_t cmd_port_host_shaper_portnum = + TOKEN_NUM_INITIALIZER(struct cmd_port_host_shaper_result, + port_num, RTE_UINT16); +cmdline_parse_token_string_t cmd_port_host_shaper_host_shaper = + TOKEN_STRING_INITIALIZER(struct cmd_port_host_shaper_result, + host_shaper, "host_shaper"); +cmdline_parse_token_string_t cmd_port_host_shaper_lwm_triggered = + TOKEN_STRING_INITIALIZER(struct cmd_port_host_shaper_result, + lwm_triggered, "lwm_triggered"); +cmdline_parse_token_num_t cmd_port_host_shaper_fr = + TOKEN_NUM_INITIALIZER(struct cmd_port_host_shaper_result, + fr, RTE_UINT16); +cmdline_parse_token_string_t cmd_port_host_shaper_rate = + TOKEN_STRING_INITIALIZER(struct cmd_port_host_shaper_result, + rate, "rate"); +cmdline_parse_token_num_t cmd_port_host_shaper_rate_num = + TOKEN_NUM_INITIALIZER(struct cmd_port_host_shaper_result, + rate_num, RTE_UINT8); + + +cmdline_parse_inst_t cmd_port_host_shaper = { + .f = cmd_port_host_shaper_parsed, + .data = (void *)0, + .help_str = "set port host_shaper lwm_triggered <0|1> " + "rate : Set HOST_SHAPER lwm_triggered and rate with port_id", + .tokens = { + (void *)&cmd_port_host_shaper_set, + (void *)&cmd_port_host_shaper_port, + (void *)&cmd_port_host_shaper_portnum, + (void *)&cmd_port_host_shaper_host_shaper, + (void *)&cmd_port_host_shaper_lwm_triggered, + (void *)&cmd_port_host_shaper_fr, + (void *)&cmd_port_host_shaper_rate, + (void *)&cmd_port_host_shaper_rate_num, + NULL, + }, +}; + +#endif + /* ******************************************************************************** */ /* list of instructions */ @@ -18093,6 +18238,10 @@ struct cmd_show_port_flow_transfer_proxy_result { (cmdline_parse_inst_t *)&cmd_show_capability, (cmdline_parse_inst_t *)&cmd_set_flex_is_pattern, (cmdline_parse_inst_t *)&cmd_set_flex_spec_pattern, +#ifdef RTE_NET_MLX5 + (cmdline_parse_inst_t *)&cmd_rxq_lwm, + (cmdline_parse_inst_t *)&cmd_port_host_shaper, +#endif NULL, }; diff --git a/app/test-pmd/config.c b/app/test-pmd/config.c index cc8e7aa..11ef7e3 100644 --- a/app/test-pmd/config.c +++ b/app/test-pmd/config.c @@ -39,6 +39,7 @@ #include #include #include +#include #ifdef RTE_NET_IXGBE #include #endif @@ -52,6 +53,9 @@ #include #endif #include +#ifdef RTE_NET_MLX5 +#include +#endif #include "testpmd.h" #include "cmdline_mtr.h" @@ -6281,3 +6285,121 @@ struct igb_ring_desc_16_bytes { printf(" %s\n", buf); } } + +#ifdef RTE_NET_MLX5 +static uint8_t lwms[RTE_MAX_ETHPORTS][RTE_MAX_QUEUES_PER_PORT+1]; +static uint8_t host_shaper_lwm_triggered[RTE_MAX_ETHPORTS]; + +#define SHAPER_DISABLE_DELAY_US 100000 /* 100ms */ +static void +lwm_event_rxq_limit_reached(uint16_t port_id, uint16_t rxq_id); + +static void +mlx5_shaper_disable(void *args) +{ + uint32_t port_rxq_id = (uint32_t)(uint64_t)args; + uint16_t port_id = port_rxq_id & 0xffff; + unsigned int qid; + + printf("%s disable shaper\n", __func__); + /* Need rearm all previous configured rxqs. */ + for (qid = 0; qid < nb_rxq; qid++) { + /* Configure with rxq's saved LWM value to rearm LWM event */ + if (rte_pmd_mlx5_config_rxq_lwm(port_id, qid, lwms[port_id][qid], + lwm_event_rxq_limit_reached)) + printf("config lwm returns error\n"); + } + /* Only disable the shaper when lwm_triggered is set. */ + if (host_shaper_lwm_triggered[port_id] && + rte_pmd_mlx5_config_host_shaper(port_id, 0, 0)) + printf("%s disable shaper returns error\n", __func__); +} + +static void +lwm_event_rxq_limit_reached(uint16_t port_id, uint16_t rxq_id) +{ + uint32_t port_rxq_id = port_id | (rxq_id << 16); + rte_eal_alarm_set(SHAPER_DISABLE_DELAY_US, + mlx5_shaper_disable, (void *)(uintptr_t)port_rxq_id); + printf("%s port_id:%u rxq_id:%u\n", __func__, port_id, rxq_id); +} + +static void +mlx5_lwm_intr_handle_cancel_alarm(uint16_t port_id, uint16_t qid) +{ + uint32_t port_rxq_id = port_id | (qid << 16); + int retries = 1024; + + rte_errno = 0; + while (--retries) { + rte_eal_alarm_cancel(mlx5_shaper_disable, + (void *)(uintptr_t)port_rxq_id); + if (rte_errno != EINPROGRESS) + break; + rte_pause(); + } +} + +int +set_rxq_lwm(portid_t port_id, uint16_t queue_idx, uint16_t lwm) +{ + struct rte_eth_link link; + int ret; + + if (port_id_is_invalid(port_id, ENABLED_WARN)) + return -EINVAL; + ret = eth_link_get_nowait_print_err(port_id, &link); + if (ret < 0) + return -EINVAL; + if (lwm > 99) + return -EINVAL; + /* When disable LWM, needs cancal alarm. */ + if (!lwm) + mlx5_lwm_intr_handle_cancel_alarm(port_id, queue_idx); + ret = rte_pmd_mlx5_config_rxq_lwm(port_id, queue_idx, lwm, + lwm_event_rxq_limit_reached); + /* Save the input lwm. */ + lwms[port_id][queue_idx] = lwm; + if (ret) + return ret; + return 0; +} + +/** Configure host shaper's lwm_triggered and current rate. + * + * @param[in] lwm_triggered + * Disable/enable lwm_triggered. + * @param[in] rate + * Configure current host shaper rate. + * @return + * On success, returns 0. + * On failure, returns < 0. + */ +int +set_port_host_shaper(portid_t port_id, uint16_t lwm_triggered, uint8_t rate) +{ + struct rte_eth_link link; + int ret; + + if (port_id_is_invalid(port_id, ENABLED_WARN)) + return -EINVAL; + ret = eth_link_get_nowait_print_err(port_id, &link); + if (ret < 0) + return ret; + host_shaper_lwm_triggered[port_id] = lwm_triggered ? 1 : 0; + if (!lwm_triggered) { + ret = rte_pmd_mlx5_config_host_shaper(port_id, 0, + RTE_BIT32(MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED)); + } else { + ret = rte_pmd_mlx5_config_host_shaper(port_id, 1, + RTE_BIT32(MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED)); + } + if (ret) + return ret; + ret = rte_pmd_mlx5_config_host_shaper(port_id, rate, 0); + if (ret) + return ret; + return 0; +} + +#endif diff --git a/app/test-pmd/meson.build b/app/test-pmd/meson.build index 43130c8..c4fd379 100644 --- a/app/test-pmd/meson.build +++ b/app/test-pmd/meson.build @@ -73,3 +73,6 @@ endif if dpdk_conf.has('RTE_NET_DPAA') deps += ['bus_dpaa', 'mempool_dpaa', 'net_dpaa'] endif +if dpdk_conf.has('RTE_NET_MLX5') + deps += 'net_mlx5' +endif diff --git a/app/test-pmd/testpmd.c b/app/test-pmd/testpmd.c index fe2ce19..3b53cd8 100644 --- a/app/test-pmd/testpmd.c +++ b/app/test-pmd/testpmd.c @@ -66,6 +66,9 @@ #ifdef RTE_EXEC_ENV_WINDOWS #include #endif +#ifdef RTE_NET_MLX5 +#include +#endif #include "testpmd.h" diff --git a/app/test-pmd/testpmd.h b/app/test-pmd/testpmd.h index 31f766c..aed2057 100644 --- a/app/test-pmd/testpmd.h +++ b/app/test-pmd/testpmd.h @@ -1163,6 +1163,11 @@ uint16_t tx_pkt_set_dynf(uint16_t port_id, __rte_unused uint16_t queue, void flex_item_create(portid_t port_id, uint16_t flex_id, const char *filename); void flex_item_destroy(portid_t port_id, uint16_t flex_id); void port_flex_item_flush(portid_t port_id); +#ifdef RTE_NET_MLX5 +int set_rxq_lwm(portid_t port_id, uint16_t queue_idx, uint16_t lwm); +int set_port_host_shaper(portid_t port_id, uint16_t lwm_triggered, + uint8_t rate); +#endif extern int flow_parse(const char *src, void *result, unsigned int size, struct rte_flow_attr **attr, diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 35210c1..0df779f 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -1677,3 +1677,79 @@ The procedure below is an example of using a ConnectX-5 adapter card (pf0) with #. For each VF PCIe, using the following command to bind the driver:: $ echo "0000:82:00.2" >> /sys/bus/pci/drivers/mlx5_core/bind + +How to use LWM and Host Shaper +------------------------------ + +LWM introduction +~~~~~~~~~~~~~~~~ + +LWM (Limit WaterMark) is a per Rx queue attribute, it should be configured as +a percentage of the Rx queue size. +When Rx queue's available WQE count is below LWM, an event is sent to PMD. + +Host shaper introduction +~~~~~~~~~~~~~~~~~~~~~~~~ + +Host shaper register is per host port register which sets a shaper +on the host port. +All VF/hostPF representors belonging to one host port share one host shaper. +For example, if representor 0 and representor 1 belong to same host port, +and a host shaper rate of 1Gbps is configured, the shaper throttles both +representors' traffic from host. +Host shaper has two modes for setting the shaper, immediate and deferred to +LWM event trigger. In immediate mode, the rate limit is configured immediately +to host shaper. When deferring to LWM trigger, the shaper is not set until an +LWM event is received by any Rx queue in a VF representor belonging to the host +port. The only rate supported for deferred mode is 100Mbps (there is no limit +on the supported rates for immediate mode). In deferred mode, the shaper is set +on the host port by the firmware upon receiving the LMW event, which allows +throttling host traffic on LWM events at minimum latency, preventing excess +drops in the Rx queue. + +Testpmd CLI examples +~~~~~~~~~~~~~~~~~~~~ + +There are sample command lines to configure LWM in testpmd. +Testpmd also contains sample logic to handle LWM event. +The typical workflow is: testpmd configure LWM for Rx queues, enable +lwm_triggered in host shaper and register a callback, when traffic from host is +too high and available WQE count runs below LWM, PMD receives an event and +firmware configures a 100Mbps shaper on host port automatically, then PMD call +the callback registered previously, which will delay a while to let Rx queue +empty, then disable host shaper. + +Let's assume we have a simple Blue Field 2 setup: port 0 is uplink, port 1 +is VF representor. Each port has 2 Rx queues. +In order to control traffic from host to ARM, we can enable LWM in testpmd by: + +.. code-block:: console + + testpmd> set port 1 host_shaper lwm_triggered 1 rate 0 + testpmd> set port 1 rxq 0 lwm 30 + testpmd> set port 1 rxq 1 lwm 30 + +The first command disables current host shaper, and enables LWM triggered mode. +The left commands configure LWM to 30% of Rx queue size for both Rx queues, +When traffic from host is too high, you can see testpmd console prints log +about LWM event receiving, then host shaper is disabled. +The traffic rate from host is controlled and less drop happens in Rx queues. + +When disable LWM and lwm_triggered, we can invoke below commands in testpmd: + +.. code-block:: console + + testpmd> set port 1 host_shaper lwm_triggered 0 rate 0 + testpmd> set port 1 rxq 0 lwm 0 + testpmd> set port 1 rxq 1 lwm 0 + +It's recommended an application disables LWM and lwm_triggered before exit, +if it enables them before. + +We can also configure the shaper with a value, the rate unit is 100Mbps, below +command sets current shaper to 5Gbps and disables lwm_triggered. + +.. code-block:: console + + testpmd> set port 1 host_shaper lwm_triggered 0 rate 50 +