From patchwork Mon Jun 6 11:20:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112343 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 51F97A0543; Mon, 6 Jun 2022 13:21:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2C5ED427F0; Mon, 6 Jun 2022 13:21:41 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2056.outbound.protection.outlook.com [40.107.220.56]) by mails.dpdk.org (Postfix) with ESMTP id CF15740150; Mon, 6 Jun 2022 13:21:39 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=R3e0Gaw/ohlzrB9tj7jAi6VT+S7Qn2yokj+p+dacjBT9/XPH4VgX/FIctKzGohafl+bqCnnXmD+QGo2WfFNHG5wkm1vKD7sg2JCj6qyB1y+gKFP2njdUKlNM2qFAGcbtk/PtWlhYeNteTETCrX86mLRDEC4V8v+3ULWR2JbiDtX6Akjrp46vr9EIFx46PjEunPbsuQixkfV8ZOmoXbzYwUYyZ0pmkyhBhcY1EbH8LrwR8nLebhLfrCJbBdzBAMfsYLPww8GAuvivpU9JG5pMNFHLhC33ROCXRKM4M1uj3c4f/us3ystYmBwrRaWAjDxUB7mJ8saUkrgHTLuk6eJWYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=RAN/gXubkThMQrVMf7+vEVmRYwtqH62xGWmAZeglDoQ=; b=VWtlJB5v1SaddaiPfdIwJ67RHZm7o0DCUdmbTeg/9w4/H+gDcRD3ECRMw2VKxZZOfV7BvQonU0TizYQKd/XfS9lWb5xH/G+KSE4HKemXWqllRiH5WnBrDfb7FAAH9iZJXrLkysIJAJ6zWKrmqfoJajbO4gFcH3YMxF1Qr74JaU88fhLVAzJHuUChXc8MydqmQ10o1oUdtMOj8GqiqAp7vO1I+qDphPv7AruCLB8zY19ls/Oz7mSVgRPKG5TQ9A/B7zGkqbWfvG/GGqsk4OIKETuW1+iy5YaUwT68pccyN94x1fP61ENu/vkZkTb8oxRFmsjxvteMivJtwnp+1j8OjA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RAN/gXubkThMQrVMf7+vEVmRYwtqH62xGWmAZeglDoQ=; b=IUk2Sq4naNiPFuzAK3/+nOnnpe5znCQnhThXiRgNTu2lL2yLr0iM3GfqkdRr/Ymogtdz9cp9Lz+8ml4V479oNbUf3rIyvKWSVnHc2mDKxI0stcS8pLSOW3egFRIoDew0rpWX6DhuqvVmbF1u1bb5jQQCzm+v59tgwG/GBNlTmT4+DPCLumDumPDiWADpOD9pW8AMwIhiLucPB/zmpUujPL7AYCTxg9vTVAUiDTp0yOlO46gDW9NHlSFk56pjyRZ3j68Dh3HcuzR9lxNYA60FiNb5r+0WSukMMG4tt/82aSyXh/rQ5o/h6lX5ehfbCyMjORihfLr33nvXSO7hK4mj8Q== Received: from BN8PR12CA0014.namprd12.prod.outlook.com (2603:10b6:408:60::27) by MN2PR12MB2861.namprd12.prod.outlook.com (2603:10b6:208:af::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13; Mon, 6 Jun 2022 11:21:37 +0000 Received: from BN8NAM11FT024.eop-nam11.prod.protection.outlook.com (2603:10b6:408:60:cafe::9c) by BN8PR12CA0014.outlook.office365.com (2603:10b6:408:60::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.14 via Frontend Transport; Mon, 6 Jun 2022 11:21:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.236) by BN8NAM11FT024.mail.protection.outlook.com (10.13.177.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:21:36 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:21:36 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:21:32 -0700 From: Li Zhang To: , , , , Maxime Coquelin CC: , , , , Subject: [PATCH v1 01/17] vdpa/mlx5: fix usage of capability for max number of virtqs Date: Mon, 6 Jun 2022 14:20:38 +0300 Message-ID: <20220606112109.208873-2-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a53279e8-be68-4890-1152-08da47aeb85d X-MS-TrafficTypeDiagnostic: MN2PR12MB2861:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: J6aPOr/dav9IfFXYEY+WM2inp0uYmOmoWo62UCdXr1AHEFyG1g/LHcI7ZZ8pLKRpdaoAXftnm2ixBABU5McD45gBA0O6mVKvI1UgUI79C7a9O11IksRgXvzotgfzoyuSpbEgAL/TFhTwbY1JvR78fl1aCEvaaXGx5rmP+cbv2RcGF8SV8xWCGTLvCck5b0Zt6UgIxsXiqt51pCYrq6z9suFdH/PtJFeIGIB7g7QEl6t0LzcutfJhEKWClNZqdXTTNknq8jmzXa27QXtRkxKEAREG+1zzMAg6S+StXsZoBAwwhG4c0JVmgxXqGFDaNPWyYGYajEw8oZuSSfnbWExEdOFM0epHKICr5LzkdCyw5ubF3NC0GCvI46CNtGvsrAM0cQi1b/q/psh83EGT6ikEZj5g7LTLHIS0wejQr7WfU4hrdE0yLNr/fJ3MmI6b3danEyHL12rHm6IMv6BD5P7d3ywvQuuETH/EdKZYUIHPdHW4dI2SPYeGCfUZMuPvRz/AjuigRIeb94csPvub6dHxBTPkcCvdWq1ZNBtzGiWjky5XgP4kyIZzTxFw0LUocrtE63CG2gYz2bUcYl8NH3a3GSukpXhD+oTKe5+WEIJH97ShhmWlxIxpkDVEb9QyAebl+d00NWrApyKomeIJP2oDQIiewhESo4Cm/GnggkTnkLOqxcYmwXjS75p+K0xyfRJ9VX9gCbg0mSVvBOE0aDezjdi2d2eyoN+EeDjdxv1Px6TnN2k+pn6tC9CNHAzZ+OkTHBp6B57e4e9SuppjNWyt2Q== X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(26005)(83380400001)(36756003)(426003)(16526019)(47076005)(2616005)(1076003)(40460700003)(55016003)(186003)(336012)(82310400005)(5660300002)(4326008)(8676002)(86362001)(70586007)(70206006)(36860700001)(2906002)(8936002)(6286002)(356005)(7696005)(54906003)(508600001)(316002)(110136005)(81166007)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:21:36.7616 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a53279e8-be68-4890-1152-08da47aeb85d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB2861 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The driver wrongly takes the capability value for the number of virtq pairs instead of just the number of virtqs. Adjust all the usages of it to be the number of virtqs. Fixes: c2eb33a ("vdpa/mlx5: manage virtqs by array") Cc: stable@dpdk.org Signed-off-by: Li Zhang --- drivers/vdpa/mlx5/mlx5_vdpa.c | 12 ++++++------ drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c index 76fa5d4299..ee71339b78 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa.c @@ -84,7 +84,7 @@ mlx5_vdpa_get_queue_num(struct rte_vdpa_device *vdev, uint32_t *queue_num) DRV_LOG(ERR, "Invalid vDPA device: %s.", vdev->device->name); return -1; } - *queue_num = priv->caps.max_num_virtio_queues; + *queue_num = priv->caps.max_num_virtio_queues / 2; return 0; } @@ -141,7 +141,7 @@ mlx5_vdpa_set_vring_state(int vid, int vring, int state) DRV_LOG(ERR, "Invalid vDPA device: %s.", vdev->device->name); return -EINVAL; } - if (vring >= (int)priv->caps.max_num_virtio_queues * 2) { + if (vring >= (int)priv->caps.max_num_virtio_queues) { DRV_LOG(ERR, "Too big vring id: %d.", vring); return -E2BIG; } @@ -388,7 +388,7 @@ mlx5_vdpa_get_stats(struct rte_vdpa_device *vdev, int qid, DRV_LOG(ERR, "Invalid device: %s.", vdev->device->name); return -ENODEV; } - if (qid >= (int)priv->caps.max_num_virtio_queues * 2) { + if (qid >= (int)priv->caps.max_num_virtio_queues) { DRV_LOG(ERR, "Too big vring id: %d for device %s.", qid, vdev->device->name); return -E2BIG; @@ -411,7 +411,7 @@ mlx5_vdpa_reset_stats(struct rte_vdpa_device *vdev, int qid) DRV_LOG(ERR, "Invalid device: %s.", vdev->device->name); return -ENODEV; } - if (qid >= (int)priv->caps.max_num_virtio_queues * 2) { + if (qid >= (int)priv->caps.max_num_virtio_queues) { DRV_LOG(ERR, "Too big vring id: %d for device %s.", qid, vdev->device->name); return -E2BIG; @@ -624,7 +624,7 @@ mlx5_vdpa_dev_probe(struct mlx5_common_device *cdev, DRV_LOG(DEBUG, "No capability to support virtq statistics."); priv = rte_zmalloc("mlx5 vDPA device private", sizeof(*priv) + sizeof(struct mlx5_vdpa_virtq) * - attr->vdpa.max_num_virtio_queues * 2, + attr->vdpa.max_num_virtio_queues, RTE_CACHE_LINE_SIZE); if (!priv) { DRV_LOG(ERR, "Failed to allocate private memory."); @@ -685,7 +685,7 @@ mlx5_vdpa_release_dev_resources(struct mlx5_vdpa_priv *priv) uint32_t i; mlx5_vdpa_dev_cache_clean(priv); - for (i = 0; i < priv->caps.max_num_virtio_queues * 2; i++) { + for (i = 0; i < priv->caps.max_num_virtio_queues; i++) { if (!priv->virtqs[i].counters) continue; claim_zero(mlx5_devx_cmd_destroy(priv->virtqs[i].counters)); diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c index e025be47d2..c258eb3024 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c @@ -72,7 +72,7 @@ mlx5_vdpa_virtqs_cleanup(struct mlx5_vdpa_priv *priv) { unsigned int i, j; - for (i = 0; i < priv->caps.max_num_virtio_queues * 2; i++) { + for (i = 0; i < priv->caps.max_num_virtio_queues; i++) { struct mlx5_vdpa_virtq *virtq = &priv->virtqs[i]; for (j = 0; j < RTE_DIM(virtq->umems); ++j) { @@ -492,9 +492,9 @@ mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv) DRV_LOG(INFO, "TSO is enabled without CSUM, force CSUM."); priv->features |= (1ULL << VIRTIO_NET_F_CSUM); } - if (nr_vring > priv->caps.max_num_virtio_queues * 2) { + if (nr_vring > priv->caps.max_num_virtio_queues) { DRV_LOG(ERR, "Do not support more than %d virtqs(%d).", - (int)priv->caps.max_num_virtio_queues * 2, + (int)priv->caps.max_num_virtio_queues, (int)nr_vring); return -1; } From patchwork Mon Jun 6 11:20:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112344 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F02E9A0543; Mon, 6 Jun 2022 13:21:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 334E94280B; Mon, 6 Jun 2022 13:21:44 +0200 (CEST) Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam07on2075.outbound.protection.outlook.com [40.107.212.75]) by mails.dpdk.org (Postfix) with ESMTP id 73977415D7; Mon, 6 Jun 2022 13:21:43 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=EeZgGzPyo9oLRGLxElaWul5mgFD4evZbWx3Y2SFGVQyFOhcvRJlOmscJxRpFBvevLevSHfQYJ1mgSUsEUq/gE4sD/qflPbCE7gweNr1AGJNYNq0gzz8A1It6xYy4wKY8vtapaPuk2rxe+SwNLBII/r/MpgBLz6dQE+kjSS6x7Z7w4S2hvqkuDkMyjcymJTSoT7HIn6YRsSKTfgieX3H+/uytHc3GvpDTG79uQr0YxvqOV7WCJOL+QKHv0mhdBfN5wl1HyoJ4fWGtNE9TBS8Jo+E69YOK+hpuo/ORaXVhx/JyCgyZvEuEs/m0xeSIIRkmPPU/xNIurcjpy5cnhQfwnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=GxYjiKxrccCuUfqLT+hVMguof9KBb2t6cO9cFphAuQI=; b=YUirClGwHplGVGgbGDfT1srJvU6i6MYzVRjvhN04MgJXWHZ39TXfYHPk9rPBNfJ9ZJIYV0TgEbLVWzNhYH56cIdSsU+awYSAPRxbixfFtWew94yNXm3gCNVnzWWokMepbi1mIMDqxqbsB20NA1O1dRf/dCjUcyVpf4iepR2633QKbGCj5O7s4otK8h+CyaxTwp3jObDJxDKQg14cELMs3aj/hYhgM8KUArIfcHpdL0zmRJaDIyun6jIsaW53kBqoowM8dUBSaQT77F360IzEm2KCdFd5+/ltOdU9ssvZN2ai/5Bv9V6oWtXV0dRnoc/ch6PpleObMsDpMOj1qEPhNw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GxYjiKxrccCuUfqLT+hVMguof9KBb2t6cO9cFphAuQI=; b=P7uy81Q9eSJkK6T49/+MNlrT/pjPx692tEz4wZUwOM9DZ9ke5JpzJCFdLGPpz648VvLBeEEdbDG0fJE1vsWcv3ihc0vtN0QzB+oMb44X/slXZhI+dNcIIgtl5FMtt5IDGsSLV/terBYV7beZmBCwAzjbpobVIBeVRHTvDUOoqBYRksASMSUWGBNbBCtEbXS64O/n3RQwqhG3ENCFDTDMeTWe7YznvtmyG+UEkD1s8lINFBitsU5qqhjn2NLHpHjl62LryCsHIBhlOwoBDvwQfqIShXPFbNYxkqTZ/+B/3PkdEiIcGwoWUeZs0R1hrtPYz1IDtoFku5hNAKAygHa/Jw== Received: from DM6PR02CA0056.namprd02.prod.outlook.com (2603:10b6:5:177::33) by BN6PR1201MB0161.namprd12.prod.outlook.com (2603:10b6:405:55::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.12; Mon, 6 Jun 2022 11:21:41 +0000 Received: from DM6NAM11FT053.eop-nam11.prod.protection.outlook.com (2603:10b6:5:177:cafe::d3) by DM6PR02CA0056.outlook.office365.com (2603:10b6:5:177::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13 via Frontend Transport; Mon, 6 Jun 2022 11:21:41 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by DM6NAM11FT053.mail.protection.outlook.com (10.13.173.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:21:41 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:21:40 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:21:35 -0700 From: Li Zhang To: , , , , Bruce Richardson , "Dmitry Kozlyuk" , Narcisa Ana Maria Vasile , Dmitry Malloy , Pallavi Kadam CC: , , , , Yajun Wu , Subject: [PATCH v1 02/17] eal: add device removal in rte cleanup Date: Mon, 6 Jun 2022 14:20:39 +0300 Message-ID: <20220606112109.208873-3-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c0f73efc-82af-4fb8-fb56-08da47aebaf7 X-MS-TrafficTypeDiagnostic: BN6PR1201MB0161:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oTdCxXd4OnBkbE/fOQ+qOI5DaXN8fXpLhzeiTEEtmRwqLUj6vPywgZ4YO5NUaxxo3t/QvX/WmLAck96k7uSdewSdVeDq7sA3ZrLlckyARceWXy/ewa3aeGcssRoChKrHm7tWraWpiL+H6p59js0srvQgbNT9/0DSfQByJnrlgwcts/r5K6yRyE5odw22YunNiHk7danR0c+FxGexSmtwDyf2uK6446tceTFqq27+8Am4aad6LGKRBalK7UWsA4uRIlcrzF+4F2xhHYU5MgUAJsATAFrF3hN28u1wm1Awn11AAJo/qka7pjb0/6WgMeW2AN9BAiAeKs6Tmyj9bTU4c3m/I/nevv6MUBERxEt5Dq5PqMd9V/t44bhl60eYR1h3uFK09bD9JYZKS6UOJWVvEulg8S92+KfJdnABXTx1BU6efGKLtWmcMpzsh52RdnPDFg4MfRAUktn+OBeWXoc6VHg9mVyU1zCh78DiI4jsMZXUCN81wnQ6FIYgBlr9HjUNICAKwkypLxzK4QEjER7YifmQMKfAHRBghdqGX2O8gf4kgYyZF+wINWw84xL9ApkarQgV28Rr8fNl/LkIbWI04cQClT15JjUuj+1V0XvkPPZu0/pfDF8j5lk2Z+lLc6DMV1+uFp5JsR3GLMp65k6ROx0k4t/cTQjUKF762cD2s5cS/ZzwOWU0mDhJPBHmJCuwriGTX4DGimPc1Ue/qIxrLA== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(508600001)(47076005)(7696005)(36860700001)(4326008)(86362001)(70586007)(82310400005)(8676002)(186003)(2616005)(8936002)(40460700003)(70206006)(5660300002)(16526019)(6286002)(55016003)(36756003)(2906002)(1076003)(426003)(54906003)(110136005)(356005)(26005)(81166007)(316002)(336012)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:21:41.1167 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c0f73efc-82af-4fb8-fb56-08da47aebaf7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0161 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Yajun Wu Add device removal in function rte_eal_cleanup. This is the last chance device remove get called for sanity. Loop vdev bus first and then all bus for all device, calling rte_dev_remove. Cc: stable@dpdk.org Signed-off-by: Yajun Wu --- lib/eal/freebsd/eal.c | 33 +++++++++++++++++++++++++++++++++ lib/eal/include/rte_dev.h | 6 ++++++ lib/eal/linux/eal.c | 33 +++++++++++++++++++++++++++++++++ lib/eal/windows/eal.c | 33 +++++++++++++++++++++++++++++++++ 4 files changed, 105 insertions(+) diff --git a/lib/eal/freebsd/eal.c b/lib/eal/freebsd/eal.c index a6b20960f2..5ffd9146b6 100644 --- a/lib/eal/freebsd/eal.c +++ b/lib/eal/freebsd/eal.c @@ -886,11 +886,44 @@ rte_eal_init(int argc, char **argv) return fctret; } +static int +bus_match_all(const struct rte_bus *bus, const void *data) +{ + RTE_SET_USED(bus); + RTE_SET_USED(data); + return 0; +} + +static void +remove_all_device(void) +{ + struct rte_bus *start = NULL, *next; + struct rte_dev_iterator dev_iter = {0}; + struct rte_device *dev = NULL; + struct rte_device *tdev = NULL; + char devstr[128]; + + RTE_DEV_FOREACH_SAFE(dev, "bus=vdev", &dev_iter, tdev) { + (void)rte_dev_remove(dev); + } + while ((next = rte_bus_find(start, bus_match_all, NULL)) != NULL) { + start = next; + /* Skip buses that don't have iterate method */ + if (!next->dev_iterate || !next->name) + continue; + snprintf(devstr, sizeof(devstr), "bus=%s", next->name); + RTE_DEV_FOREACH_SAFE(dev, devstr, &dev_iter, tdev) { + (void)rte_dev_remove(dev); + } + }; +} + int rte_eal_cleanup(void) { struct internal_config *internal_conf = eal_get_internal_configuration(); + remove_all_device(); rte_service_finalize(); rte_mp_channel_cleanup(); /* after this point, any DPDK pointers will become dangling */ diff --git a/lib/eal/include/rte_dev.h b/lib/eal/include/rte_dev.h index e6ff1218f9..382d548ea3 100644 --- a/lib/eal/include/rte_dev.h +++ b/lib/eal/include/rte_dev.h @@ -492,6 +492,12 @@ int rte_dev_dma_unmap(struct rte_device *dev, void *addr, uint64_t iova, size_t len); +#define RTE_DEV_FOREACH_SAFE(dev, devstr, it, tdev) \ + for (rte_dev_iterator_init(it, devstr), \ + (dev) = rte_dev_iterator_next(it); \ + (dev) && ((tdev) = rte_dev_iterator_next(it), 1); \ + (dev) = (tdev)) + #ifdef __cplusplus } #endif diff --git a/lib/eal/linux/eal.c b/lib/eal/linux/eal.c index 1ef263434a..30b295916e 100644 --- a/lib/eal/linux/eal.c +++ b/lib/eal/linux/eal.c @@ -1248,6 +1248,38 @@ mark_freeable(const struct rte_memseg_list *msl, const struct rte_memseg *ms, return 0; } +static int +bus_match_all(const struct rte_bus *bus, const void *data) +{ + RTE_SET_USED(bus); + RTE_SET_USED(data); + return 0; +} + +static void +remove_all_device(void) +{ + struct rte_bus *start = NULL, *next; + struct rte_dev_iterator dev_iter = {0}; + struct rte_device *dev = NULL; + struct rte_device *tdev = NULL; + char devstr[128]; + + RTE_DEV_FOREACH_SAFE(dev, "bus=vdev", &dev_iter, tdev) { + (void)rte_dev_remove(dev); + } + while ((next = rte_bus_find(start, bus_match_all, NULL)) != NULL) { + start = next; + /* Skip buses that don't have iterate method */ + if (!next->dev_iterate || !next->name) + continue; + snprintf(devstr, sizeof(devstr), "bus=%s", next->name); + RTE_DEV_FOREACH_SAFE(dev, devstr, &dev_iter, tdev) { + (void)rte_dev_remove(dev); + } + }; +} + int rte_eal_cleanup(void) { @@ -1257,6 +1289,7 @@ rte_eal_cleanup(void) struct internal_config *internal_conf = eal_get_internal_configuration(); + remove_all_device(); if (rte_eal_process_type() == RTE_PROC_PRIMARY && internal_conf->hugepage_file.unlink_existing) rte_memseg_walk(mark_freeable, NULL); diff --git a/lib/eal/windows/eal.c b/lib/eal/windows/eal.c index 122de2a319..3d7d411293 100644 --- a/lib/eal/windows/eal.c +++ b/lib/eal/windows/eal.c @@ -254,12 +254,45 @@ __rte_trace_point_register(rte_trace_point_t *trace, const char *name, return -ENOTSUP; } +static int +bus_match_all(const struct rte_bus *bus, const void *data) +{ + RTE_SET_USED(bus); + RTE_SET_USED(data); + return 0; +} + +static void +remove_all_device(void) +{ + struct rte_bus *start = NULL, *next; + struct rte_dev_iterator dev_iter = {0}; + struct rte_device *dev = NULL; + struct rte_device *tdev = NULL; + char devstr[128]; + + RTE_DEV_FOREACH_SAFE(dev, "bus=vdev", &dev_iter, tdev) { + (void)rte_dev_remove(dev); + } + while ((next = rte_bus_find(start, bus_match_all, NULL)) != NULL) { + start = next; + /* Skip buses that don't have iterate method */ + if (!next->dev_iterate || !next->name) + continue; + snprintf(devstr, sizeof(devstr), "bus=%s", next->name); + RTE_DEV_FOREACH_SAFE(dev, devstr, &dev_iter, tdev) { + (void)rte_dev_remove(dev); + } + }; +} + int rte_eal_cleanup(void) { struct internal_config *internal_conf = eal_get_internal_configuration(); + remove_all_device(); eal_intr_thread_cancel(); eal_mem_virt2iova_cleanup(); /* after this point, any DPDK pointers will become dangling */ From patchwork Mon Jun 6 11:20:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112346 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C6D8FA0543; Mon, 6 Jun 2022 13:22:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A26D042B6C; Mon, 6 Jun 2022 13:21:54 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2081.outbound.protection.outlook.com [40.107.244.81]) by mails.dpdk.org (Postfix) with ESMTP id CD71F42905; Mon, 6 Jun 2022 13:21:53 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=l44o5G0LONuGftfOTkXtdR+a789VGYlnwGlMkEb9FjxgDVq0WodQoeHt63OH74q2WHg3lfFjHgiyZkAGwMY/xTv0XpD0+2h8hUEcwp+HT2+zB4h6Wh6pJ3kPUtXFWfgbNm9qS3HJyMdocH7RJwstGjr2i6qhqgwFpGI1SuK9avJXrNLqGDOzwiPsU8s/BNZ65k0LEUotz0Bt8LyuJvKhYTk8zFp8EFyps8SeGgjjhXT+miAy6pDFF4k5zWgWzI4NEMDYIdMh3JZV13eCj6AwEc1kcojn7KX/I1WI61vvv4qOPKND6PuWX2RzJmnBRwUXbP61CDyK8v+G3up7LB1o3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+ZPVU+1n/X1Ej6xmkv+FiB/jRHtSB9weFEKHydo0p+I=; b=BWalOTbV6WkadaRmVIM2E9zQoeedsouuxoALIayiWSlRZgOv6R7CCyVTal0WB6QzikRol210xTsdh8XtFKbNOaYX6QIcVAqTBlpT/FfV8jRJ+COIwei/xmWtU+vCSWyWm1jcyKkhc7LqigQnA9kcAOpgrpw4jALIsVLJ/FONT+oHFbXdZPTGxaQSy2iHdcPXAGnOEL1U1JIB6WaYw9cjKDG3K4BxAPuizwaq+AUza9OOfUCXmGzUG89Pf00VcAjoslRlTvNGp2ArejKs0jwCywQ4VjOtXC/Q/CT1TQ2FtD5A/rOR5lurVfiHdzIQOZei6DBhgLr/PCXa68NmnCBfPA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+ZPVU+1n/X1Ej6xmkv+FiB/jRHtSB9weFEKHydo0p+I=; b=nUhK4cCInF03ooWqcmPDisWy02q2XaAmCz9G83Sz2AaPN6S1ptgbDc0PW+KDJc1AN04JffmuLdE5ShOE97Y2apgDJjjvUJyo/607clETUI2Vb0+0GHxmT4N/c77813KbXBApFNLSd0SxrmHvIwJyc9LawtojqG22yjAg/Aqs1Z+s5i4bFdZFx5RHyaXxeNTYJ/p2Ij0g4uAp5/LAbnF03nuBiFbkz9JCZia7OcPOGaVLVG36DmjG7lW5nUi+Jwl7sRzg5Sl2/X61hzOMSuKXnAh6WOZrzsKH5S7oe8OdbujW0NKmYiiL3grMtFOOJGv4KVY8fKAQioxCHJnzWVfmnw== Received: from CO2PR18CA0051.namprd18.prod.outlook.com (2603:10b6:104:2::19) by BL1PR12MB5032.namprd12.prod.outlook.com (2603:10b6:208:30a::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.12; Mon, 6 Jun 2022 11:21:50 +0000 Received: from CO1NAM11FT008.eop-nam11.prod.protection.outlook.com (2603:10b6:104:2:cafe::38) by CO2PR18CA0051.outlook.office365.com (2603:10b6:104:2::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.19 via Frontend Transport; Mon, 6 Jun 2022 11:21:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.234) by CO1NAM11FT008.mail.protection.outlook.com (10.13.175.191) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:21:49 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:21:48 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:21:44 -0700 From: Li Zhang To: , , , , Maxime Coquelin , "Chenbo Xia" , Chengchang Tang CC: , , , , Yajun Wu , Subject: [PATCH v1 03/17] examples/vdpa: fix devices cleanup Date: Mon, 6 Jun 2022 14:20:41 +0300 Message-ID: <20220606112109.208873-5-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d30021d4-1984-4c9c-8bef-08da47aebfa2 X-MS-TrafficTypeDiagnostic: BL1PR12MB5032:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nO73RtsCfZ3CBfJ4s/Q1n+3qVhFKD21kha1Gu6VRg5t0sqdKqNZaclHdBAUTNxL2n3j9O27OkrPO5iY4bcPmjPT6saGdPeKc3i88MU/355Jx83WXj0JqlYf2SUIYAsacxba/NG07GG57YP6kznrmxNecNU+iOa7xDoxgK9o8ynR2nBTHQZ6PiHuNPQImqc8oS0EShKNAj0w3tmFBTAJ/JTUuqhyAQZwhNFLPN/rm7V7FuS4nOajZyl4QsoERJghJYTY9quUTbg6nWZhQcHN201Xx7afvxS9UZQnAYL4t3LKGfKfoDY4EL1wtMcWYq9fGZnyPgCcob/9gjuPIQxckCAAHxYIRgVWKzWcfnCpa3GCGs6ft7B5qDp8FCWmoutOGo9SEtSiTXzlbt49NaM9RLJYUZC6PGqvWSOUP10tv6jJHhSAudqkUI57VeOCJXV3XfMfPOZi1KPULwIO0iE3wWX/9O1UKhNOrcQQu1m3vG46G+LnsTwPjRx9Ex5/U5nD2HLraYMMQ11apni2pqz8h8FkwshEdDZ/A6PNrQBZth2WknlObPKLwx82Zt/DYbY7oAUyOxhnTsfCKrYeNKEuaopHSRdsqx7bhW84uyjeHPWynKOBVRxBhIIlylb7QHeWV3QpIZUI7Uz0TE73HPj4D/Iq/sdOVSOY1tIIproL2zfPPBdPjfD8UQpn6YjUULdbmDDHU7suBFFLWUpp204pOZg== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(83380400001)(82310400005)(4326008)(36860700001)(7696005)(1076003)(4744005)(16526019)(508600001)(2906002)(86362001)(186003)(2616005)(40460700003)(6666004)(8676002)(336012)(8936002)(426003)(110136005)(47076005)(36756003)(54906003)(70206006)(26005)(55016003)(6286002)(81166007)(356005)(316002)(5660300002)(70586007)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:21:49.0391 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d30021d4-1984-4c9c-8bef-08da47aebfa2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5032 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Yajun Wu Move rte_eal_cleanup to function vdpa_sample_quit which handling all example app quit. Otherwise rte_eal_cleanup won't be called on receiving signal like SIGINT(control + c). Fixes: 10aa3757 ("examples: add eal cleanup to examples") Cc: stable@dpdk.org Signed-off-by: Yajun Wu --- examples/vdpa/main.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/examples/vdpa/main.c b/examples/vdpa/main.c index 7e11ef4e26..62e32b633d 100644 --- a/examples/vdpa/main.c +++ b/examples/vdpa/main.c @@ -286,6 +286,8 @@ vdpa_sample_quit(void) if (vports[i].ifname[0] != '\0') close_vdpa(&vports[i]); } + /* clean up the EAL */ + rte_eal_cleanup(); } static void @@ -632,8 +634,5 @@ main(int argc, char *argv[]) vdpa_sample_quit(); } - /* clean up the EAL */ - rte_eal_cleanup(); - return 0; } From patchwork Mon Jun 6 11:20:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112347 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9FB40A0543; Mon, 6 Jun 2022 13:22:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B801A427F3; Mon, 6 Jun 2022 13:21:58 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2057.outbound.protection.outlook.com [40.107.223.57]) by mails.dpdk.org (Postfix) with ESMTP id 19642415D7 for ; Mon, 6 Jun 2022 13:21:57 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jwPD8++7UBdYf9nhunqYO82BoZkcumtHfuvIzo95Xp/Ujs25cFBoxVcesRKT7x23ca1MNbjkf6aahKSDqXJxZwzp+rUrETa7HHoJ4IKIht/rKAfJkrzmXbneghChZANpuEjhnWKMr832aVTgZDlvd2o4A/hWQvyP2V+lSxEaUyHlV/GULOxktaPLSZcEdlHoe3EEp9ATzzIJpyrdS5bR3cgQBneEjKARzy2fccN4HDXI8xllfZ7YA7iUopLP0cwNGoOY0CK5Ze46FEl/Tu7vxchwjTqazCHxevODmAbWIXfA53D3P3BPOEtlBvnJPlqYGv4XkFsgfOhfJ9noky6Vhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=We/bsNcpSpBekIWDvBf9E+epWgYn0d2hG5xm0p+Apr4=; b=ST0h/rvc1ChMt1QFlUEWqHcxhz36b9TnjlJ5w5B1Job1v/dcnHkLOWn5nZw2M54LIvndHJ66wR7fhAFaFYN/OBVf1Y4uaOC/OdBnfLlaVrPxlSh28Kcb7SI2A5uF8TfAmQ0gFcBta3FpDl7hTkrgQAz3V6WtTZA+vtgee9cWVs6oRWjmCkCi38YnBi+my/NW5fG7xn7g3uFO+lqrppMN7Qxfu/huJAiUoB6qk/fdna9jAwAt9TIs90J2k/pIwvR4OXrl3/6D/CTKavS7vRd3LYcwqIM3vq33a7tBIJXP5oK8L1PpUbV6Meq/miqsDXslhJOYECRtoJsR3o6bLsVr3w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=We/bsNcpSpBekIWDvBf9E+epWgYn0d2hG5xm0p+Apr4=; b=D3uxj62lRSVYYHPRlYz392KsR15lt6LehVKI8esSDgvmf/QwaJThJTnhVA8ZuhfH1MYjoYx8qDpTxHitW4VHEivCmvCTPbudOTfYVCgvvi+mpXhC2X8j8Ir46sz2hcoLYfsAEIP37OzuBjWgWNfEQcCYfHPsjSOhqYyjDaBACvU/syJH+Ni0zR4z28XfgieFECD4+n5Pam5ZJ7v+k7SZ8eeHQa/sWuuUnSC0BTlu+iGizObRLSR3VH758s/AZi/QOoj4I8OEQpHehg0pWr0SH4h0M9VHqOtCMpV3PZzKuBOb2ger8vHNs9Qzha3tTCCQscwcpzUTA8baSV3BhC0hbg== Received: from MWHPR18CA0029.namprd18.prod.outlook.com (2603:10b6:320:31::15) by BN9PR12MB5067.namprd12.prod.outlook.com (2603:10b6:408:134::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.12; Mon, 6 Jun 2022 11:21:55 +0000 Received: from CO1NAM11FT015.eop-nam11.prod.protection.outlook.com (2603:10b6:320:31:cafe::3d) by MWHPR18CA0029.outlook.office365.com (2603:10b6:320:31::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.19 via Frontend Transport; Mon, 6 Jun 2022 11:21:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.234) by CO1NAM11FT015.mail.protection.outlook.com (10.13.175.130) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:21:55 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:21:54 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:21:51 -0700 From: Li Zhang To: , , , CC: , , , , Yajun Wu Subject: [PATCH 04/16] common/mlx5: add DevX API to move QP to reset state Date: Mon, 6 Jun 2022 14:20:43 +0300 Message-ID: <20220606112109.208873-7-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: af6e4e7c-5fc0-4bc0-bb4a-08da47aec34c X-MS-TrafficTypeDiagnostic: BN9PR12MB5067:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FuNKHvQpcd1zLTQT4sUK4kfx/UytIqoLZb9P1mug8tfRRzJomXljvdWM1zzym6V1iDzQED/g1rEsa5E8yYwzPBDA8mXrd8YvOA9dbeMSa6lEJ17xlqvWRI8SeMkpkcxCtdpqdfbFcS9XZWxPeBMHnkmXIroklz3LWP/KvBl5hfiGjUvcrb//S3+ue88YrKzQZUkvdLuoTKhz7Dj+BwEg6EtanFt+6lUBKhcydV0rM7JatWKGKjpcyw8/AvjdhHgQuuiplnJVAaBxMgrAoxXJD5GtgEyOhobZ2kfsyIWNVxSmiGdE7KCzgdclxFHr/+mCEVt6rZasV/W7Q5iSEYdwKZ7VXJwe4lYjTYmsgfUErkI4gyb4ZbGPaTMHWYsw4mDnG7w6nP85lCvIJ8JoGZkjh/uWUVnGiq8b0kcYJ4FctkaAmjsJgOA/JdxKq29hYJ8NLsP66VRcHYsRHHwgzk13+LV7xNfOV8FJRuqu7aIR5T4b3HDM4WVjj4kpGXZFvjmC9cv45Dzs1LiRg5IDQU3LJsZQTCUiBBefBFaU5R3DfZnYSF61GrIA34ttStuMpVApAXMCUsnD7bFSqFnhvwy/tC7jfrtyMDQG/iHBVet5K8iG1ZRh/oR1/VJc6q6CvQFwOOXGCGKX8s8lET23Mgwiv711TR+EaV/qfnAxqM7v/Rq4XaU3+hoi55FBYPemd3Rkd7Ebqs+LlCegiVN6zrNSmw== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(426003)(6666004)(86362001)(508600001)(336012)(2906002)(316002)(55016003)(107886003)(40460700003)(1076003)(47076005)(186003)(16526019)(2616005)(6636002)(54906003)(110136005)(26005)(6286002)(7696005)(5660300002)(36756003)(36860700001)(8676002)(81166007)(8936002)(4326008)(356005)(70586007)(70206006)(82310400005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:21:55.1720 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af6e4e7c-5fc0-4bc0-bb4a-08da47aec34c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5067 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Yajun Wu Support set QP to RESET state. Signed-off-by: Yajun Wu --- drivers/common/mlx5/mlx5_devx_cmds.c | 7 +++++++ drivers/common/mlx5/mlx5_prm.h | 17 +++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index c6bdbc12bb..1d6d6578d6 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -2264,11 +2264,13 @@ mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; + uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; } in; union { uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; + uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; } out; void *qpc; int ret; @@ -2311,6 +2313,11 @@ mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, inlen = sizeof(in.rtr2rts); outlen = sizeof(out.rtr2rts); break; + case MLX5_CMD_OP_QP_2RST: + MLX5_SET(2rst_qp_in, &in, qpn, qp->id); + inlen = sizeof(in.qp2rst); + outlen = sizeof(out.qp2rst); + break; default: DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", qp_st_mod_op); diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index bc3e70a1d1..8a2f55c33e 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3657,6 +3657,23 @@ struct mlx5_ifc_init2init_qp_in_bits { u8 reserved_at_800[0x80]; }; +struct mlx5_ifc_2rst_qp_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_2rst_qp_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + u8 vhca_tunnel_id[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_80[0x8]; + u8 qpn[0x18]; + u8 reserved_at_a0[0x20]; +}; + struct mlx5_ifc_dealloc_pd_out_bits { u8 status[0x8]; u8 reserved_0[0x18]; From patchwork Mon Jun 6 11:20:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112350 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2CA80A0543; Mon, 6 Jun 2022 13:22:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BCFA342B8B; Mon, 6 Jun 2022 13:22:04 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2089.outbound.protection.outlook.com [40.107.223.89]) by mails.dpdk.org (Postfix) with ESMTP id 977B942B82 for ; Mon, 6 Jun 2022 13:22:03 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lcFzjSKvHwfp+5DjcUfRDuvTWp2H1HqqqvBbetz+xo8ZyLhQJajuwpFpWP18d8PZ7et+Xm9iBqY6Kh9pSsN72g1WKCGi9xL+FNRsZ75M5eDkOwh/CyBcPrkBlTey3QA5h5xZ0G8ervrK6q768bSbiWEyenkpehRqTPH4wep3gBp6M0bTvI7UkZJygh/rU0Q8ifWucOqJfFWvXkPZ2uZGPvBJMH+7X2pdT19DNd3bCQqRNvcq4t9j50hCg2J0vIy8gfWrgDBnc1LajcqgpN0a4TuIPTVF65BY1lUK1d5EsredCi87akVyx8cVDgqTYc2VLRRevp1m44OiwusjCh+e+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=We/bsNcpSpBekIWDvBf9E+epWgYn0d2hG5xm0p+Apr4=; b=Czxzsarw2qLEM1F5yxXBr8jsVZPkp9ewKNIf5EaS+X1ggjYTMgK8iV/q33CcVBFLoebwVQHzL1L5CSikWiRCf37N5/YlIYK+HBEGe9TQOnnk+qIavuOK/CU3hbRIJtf66MQl0B2BgZhTW8MN7rBLGGxTM/ccqBJeV/l3XtcZt/eVBfleh5jUqhPBDoNJsF6AfQFHNHmkijGlESj7MCk/cCvK5MS2bYv4Y0TX26Un+LslVhFSpMpd+mNez1tD8fSVhsWHkwqSIdLREw8LU2F6bpKBVD3Z7xGsrHwElLj5ErMXUBTZH46eKeQ3l5OMaklJs1Rn9jLOFttzG/dG/lyeAg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=We/bsNcpSpBekIWDvBf9E+epWgYn0d2hG5xm0p+Apr4=; b=epXdDzuZXGdgP5vV6h1p2GMfeOYE1fXw0rKxFXmYeRig0PXBxQelNDN33FaJKvK2gtX62lhVsfBffnf8rziij5JNWk7oRBqrIK/2V+MFvLwiZxPlDD028jf3fmVZnW3tfu0+hyXojmT4cUwOn6U/+4diWSK959BqmvlLbziUYpo1kOAUBsabtzqyeyx10pMMPudSPZei/CJMyiklc6a9OH0gTGx4uK1Ezl5FEQuylN1mJEY4nFACmRUMDRz0HjXPysiwPMO/5hENBhOZZERt4Gaww4kAW71oO4PC/S6MoNjhILW3g12jpWS4Rr6IGf9DVXbiXqzCGjaUzRc7vV8Btw== Received: from BN8PR07CA0004.namprd07.prod.outlook.com (2603:10b6:408:ac::17) by CY5PR12MB6407.namprd12.prod.outlook.com (2603:10b6:930:3c::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5293.18; Mon, 6 Jun 2022 11:22:01 +0000 Received: from BN8NAM11FT014.eop-nam11.prod.protection.outlook.com (2603:10b6:408:ac:cafe::db) by BN8PR07CA0004.outlook.office365.com (2603:10b6:408:ac::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.17 via Frontend Transport; Mon, 6 Jun 2022 11:22:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by BN8NAM11FT014.mail.protection.outlook.com (10.13.177.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:01 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:22:00 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:21:57 -0700 From: Li Zhang To: , , , CC: , , , , Yajun Wu Subject: [PATCH v1 05/17] common/mlx5: add DevX API to move QP to reset state Date: Mon, 6 Jun 2022 14:20:45 +0300 Message-ID: <20220606112109.208873-9-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f2dfe36e-b738-4e0e-88c3-08da47aec71a X-MS-TrafficTypeDiagnostic: CY5PR12MB6407:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JDNEc7XmEqeBTmT8R27Qnre+qUkP00EUt0DSNYUPoe17Suzi9a1lHhNWIy0LFsHOUhnwBnPonY8QRfBdh3T7Wx4YS1nFlUMsYOYLj3NMAt0SLWfLJ/HoAi3HPMnMtw+0NrIdv8txMY18RrbJCdGoLNtv+GrULmS59WQLpJXKCGJd+VM8r8/w3N7H3m0Afef8UgLEW3KCn16mvI4Ucm02bVmWjitgy4NC4JgkcbQC7EROGHFFO7Jg4t+/g/zseJ/psMWuZ/zkn8pHrS0VW95NVdGeJPkCAPswdBI771HJ0E4r3zV3FnYsKqQazQPylBJiI2twF1PAT5bjpwffgMomuGMivRgusd3h11J9syqOQVNKTekKEkqYDQ/l1EOrxwy9h7b3cNDm0EigRMXKAJ5uwzc3F2WtS+sGS/VRQ0chIzJcraQ0VT5XxGY/qzEDw31UJ8/da7aHhc/wLo8x03P7VS4U+9sve7DgI9ZtZcWEz0sVJ/ABLoeJRebsJY09SoYqSGEQTzK3wcVYthpb9/2N5AkO+dAAa/SP7M2ZXeIHbTXN5TIdjg3Ch8SAsGV/PMVwS9T5z/hUz9VlRt3WtyDL4mp3pYEfXSoSpgel5T1fY2HNLsAuD0TgItAxOM/VcMFiaQf/GuMDP4x1rUShy4G7ykC8BYLWJ/kjjs663Y8ZnBp9kbFjwMu4BTkYtSyhT3+y3k2nK8mKAv/mtlvRUFIo7Q== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(110136005)(7696005)(16526019)(36860700001)(4326008)(426003)(336012)(186003)(2906002)(26005)(6286002)(5660300002)(2616005)(82310400005)(8936002)(47076005)(40460700003)(54906003)(107886003)(81166007)(70206006)(6666004)(1076003)(55016003)(508600001)(356005)(36756003)(70586007)(86362001)(6636002)(316002)(8676002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:22:01.4914 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2dfe36e-b738-4e0e-88c3-08da47aec71a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6407 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Yajun Wu Support set QP to RESET state. Signed-off-by: Yajun Wu --- drivers/common/mlx5/mlx5_devx_cmds.c | 7 +++++++ drivers/common/mlx5/mlx5_prm.h | 17 +++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index c6bdbc12bb..1d6d6578d6 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -2264,11 +2264,13 @@ mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; + uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; } in; union { uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; + uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; } out; void *qpc; int ret; @@ -2311,6 +2313,11 @@ mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, inlen = sizeof(in.rtr2rts); outlen = sizeof(out.rtr2rts); break; + case MLX5_CMD_OP_QP_2RST: + MLX5_SET(2rst_qp_in, &in, qpn, qp->id); + inlen = sizeof(in.qp2rst); + outlen = sizeof(out.qp2rst); + break; default: DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", qp_st_mod_op); diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index bc3e70a1d1..8a2f55c33e 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3657,6 +3657,23 @@ struct mlx5_ifc_init2init_qp_in_bits { u8 reserved_at_800[0x80]; }; +struct mlx5_ifc_2rst_qp_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_2rst_qp_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + u8 vhca_tunnel_id[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_80[0x8]; + u8 qpn[0x18]; + u8 reserved_at_a0[0x20]; +}; + struct mlx5_ifc_dealloc_pd_out_bits { u8 status[0x8]; u8 reserved_0[0x18]; From patchwork Mon Jun 6 11:20:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112352 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8D0D8A0543; Mon, 6 Jun 2022 13:22:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0438242B92; Mon, 6 Jun 2022 13:22:11 +0200 (CEST) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2058.outbound.protection.outlook.com [40.107.92.58]) by mails.dpdk.org (Postfix) with ESMTP id 888DC42B92 for ; Mon, 6 Jun 2022 13:22:09 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JvdRbQc+fFpRmhp6F8LtiKVz1aI9USmx14iW//gnbuoleEi/EeBtQQdcRZ0QRzDM5PQe1QrWM9oJoRFnfOF9Zt8hXyZxcGWxja86SQbP5e9A3sWjGIOWitROOmUmn+Z7JcQO3yhrEjA4QvpdChwErxqHQ195T9LogSz9OfHaQkxPlhHZOLzIfhyEadMu0X6erVUOlecUmfCgZ72vRRTj6BXGBxAzVJacwt5xU0vJwas0KC7IkAM9kUigQYN0QFVXdq3NDGdeyaGzQHkfkBXuIPg0C2nEHnYdosHBw5Ak/ibwVv3iyeridmUcEkdkONakSk6uYGMDLFuVKBc9EkbkVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ThoE1uZCZkPGeiGhP5FRmVx1hCO8Fk0McFIuFAahjv0=; b=ZarQtYAk8uev49vAT9Behc5UHUkwHGOGxPQnl7tJZHNauh3MonpLTNLVWCzFlRAMMR2ahl9h/Qm03HJhiJTx/9AFs3FBjIytjh8kHY0d/RMy4cfbN+GVxxiQ+Zmsrc414l4y2jdannpLWCDTeIaRvdzKOdQR1w46ueWKOCnm/j47qPTkQ+1mMhDJdr+5XMMHwHIk0VnYwHTklz959H56+KfhkBujJAFiBscnkTL6xJCGCSQUDbL2aRe+/1U/oVy8pUVyL2YQDc9Xgzch3pRYx5FIfacCL4LlmL0Q6rywWAptzkq7HWt6his6uzQHkc/K02azS/ZIz+KDBrLWvKMoUw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ThoE1uZCZkPGeiGhP5FRmVx1hCO8Fk0McFIuFAahjv0=; b=JvZHagcl+6bFmgYKy5QswiuH/PSgLFVW7DaEXVpI2zaSDbytTsRdnoNLI0JHAg18qkKD7eHCjP9Xkrc8rhhMc0XSDD/+mlnfxdVYiFBsy1dOrsfyd42JmCHUA3Hft0sH5k5FClyr88+BGiWHb1iEyXeMIdojMhQo5fYH8GX3Xnp/cOL/PcMvWRrxoRdGOHnRONrRmlaF7LCkqNb5JzTrmlDlvaVf7qlf50UgNPdbYG12WNugOW7EzOY26jesrveP+Kfh8OcWCVL0pcFlwqsKH9PwiNes5gB3CJEVG/OYu7skeGAWlCQ4wfW9XUxPtAx35Wte5SGABd3EJTCL3XmTMQ== Received: from BN1PR12CA0029.namprd12.prod.outlook.com (2603:10b6:408:e1::34) by MWHPR12MB1263.namprd12.prod.outlook.com (2603:10b6:300:f::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13; Mon, 6 Jun 2022 11:22:07 +0000 Received: from BN8NAM11FT058.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e1:cafe::e7) by BN1PR12CA0029.outlook.office365.com (2603:10b6:408:e1::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.17 via Frontend Transport; Mon, 6 Jun 2022 11:22:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.234) by BN8NAM11FT058.mail.protection.outlook.com (10.13.177.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:07 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:22:06 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:22:03 -0700 From: Li Zhang To: , , , CC: , , , Subject: [PATCH 06/16] common/mlx5: extend virtq modifiable fields Date: Mon, 6 Jun 2022 14:20:47 +0300 Message-ID: <20220606112109.208873-11-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ecf3732e-0598-4bc4-eaa7-08da47aeca6b X-MS-TrafficTypeDiagnostic: MWHPR12MB1263:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: F4uPhsFfdVC+NHUNtLTywZ55PdnZItKP7Qb2fNKbgkuyMcY39enm7g+8bjxdEhuA+xubc7dc2Nsi25eBb9eqp0wTXEZ7l3V3S3TBq1sLLseZ4MAaiv7mdQB2lfvpjceXl067bHMRJmONheatxA/7rLrgQ7Qn19JkeZY/AfQRWSRjN5DLl2avBKTfdW+pQX0InugU0UmcamlZM1ZPCO+jfQt7Q5gZLoiiYcHzP6ToV1gKUrLQDHGJUaRRiqRt1sOe+qEF/iuU9Z4vJNspD9E8TnepsjMQGB+7C5Fa6P8cRHN/zr04OCJqnj90unpd9Z4vJOaP4nZx3TgLyvLnKHvjYgs96yXzpY5rdqdNij2ZFIMWbunyuWJOtB1rIorKgYh5wehhls1C8htSJnGqoUpA73dCRwgot1aq/G3IjLPCNf8lEAFba9NzOJUKdJLU/VhdZHSCAjZRpF4AVih+nTjFkdV5+so2DHt5VAK9HTs8RGo1ZRLNkfFjtPRLr+la5DXiHudSJQJGUPQ3jlXFzQIg1yLyOFXY+bgWOB1qvkyUbX+3r9xFR3bY1X2Nu2baOTLjhm9v73kR/K4EIrWWsS27iprwybCdt1OilA1mQTR30p9vOZHkx8u1irHyubiI7kQI+cVewqka5d3XAsRoRxJPvUFi1h594KFsctxmmIW4m0bwNv3EPyk4nNg/WH23zPV3bgQkMXD9YyC61A5rY6apgw== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(40460700003)(336012)(82310400005)(70586007)(70206006)(16526019)(8936002)(186003)(5660300002)(508600001)(110136005)(4326008)(2616005)(8676002)(1076003)(107886003)(7696005)(54906003)(47076005)(426003)(81166007)(26005)(55016003)(356005)(2906002)(6636002)(6666004)(316002)(36756003)(36860700001)(83380400001)(86362001)(6286002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:22:07.0579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ecf3732e-0598-4bc4-eaa7-08da47aeca6b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1263 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org A virtq configuration can be modified after the virtq creation. Added the following modifiable fields: 1.address fields: desc_addr/used_addr/available_addr 2.hw_available_index 3.hw_used_index 4.virtio_q_type 5.version type 6.queue mkey 7.feature bit mask: tso_ipv4/tso_ipv6/tx_csum/rx_csum 8.event mode: event_mode/event_qpn_or_msix Signed-off-by: Li Zhang --- drivers/common/mlx5/mlx5_devx_cmds.c | 70 +++++++++++++++++++++++----- drivers/common/mlx5/mlx5_devx_cmds.h | 6 ++- drivers/common/mlx5/mlx5_prm.h | 13 +++++- 3 files changed, 76 insertions(+), 13 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 1d6d6578d6..1b68c37092 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -545,6 +545,15 @@ mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, vdpa_attr->log_doorbell_stride = MLX5_GET(virtio_emulation_cap, hcattr, log_doorbell_stride); + vdpa_attr->vnet_modify_ext = + MLX5_GET(virtio_emulation_cap, hcattr, + vnet_modify_ext); + vdpa_attr->virtio_net_q_addr_modify = + MLX5_GET(virtio_emulation_cap, hcattr, + virtio_net_q_addr_modify); + vdpa_attr->virtio_q_index_modify = + MLX5_GET(virtio_emulation_cap, hcattr, + virtio_q_index_modify); vdpa_attr->log_doorbell_bar_size = MLX5_GET(virtio_emulation_cap, hcattr, log_doorbell_bar_size); @@ -2074,27 +2083,66 @@ mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, MLX5_GENERAL_OBJ_TYPE_VIRTQ); MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); - MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); + MLX5_SET64(virtio_net_q, virtq, modify_field_select, + attr->mod_fields_bitmap); MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); - switch (attr->type) { - case MLX5_VIRTQ_MODIFY_TYPE_STATE: + if (!attr->mod_fields_bitmap) { + DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); + rte_errno = EINVAL; + return -rte_errno; + } + if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) MLX5_SET16(virtio_net_q, virtq, state, attr->state); - break; - case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: + if (attr->mod_fields_bitmap & + MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, attr->dirty_bitmap_mkey); MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, attr->dirty_bitmap_addr); MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, attr->dirty_bitmap_size); - break; - case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: + } + if (attr->mod_fields_bitmap & + MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, attr->dirty_bitmap_dump_enable); - break; - default: - rte_errno = EINVAL; - return -rte_errno; + if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { + MLX5_SET(virtio_q, virtctx, queue_period_mode, + attr->hw_latency_mode); + MLX5_SET(virtio_q, virtctx, queue_period_us, + attr->hw_max_latency_us); + MLX5_SET(virtio_q, virtctx, queue_max_count, + attr->hw_max_pending_comp); + } + if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { + MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); + MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); + MLX5_SET64(virtio_q, virtctx, available_addr, + attr->available_addr); + } + if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) + MLX5_SET16(virtio_net_q, virtq, hw_available_index, + attr->hw_available_index); + if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) + MLX5_SET16(virtio_net_q, virtq, hw_used_index, + attr->hw_used_index); + if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) + MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); + if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) + MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, + attr->virtio_version_1_0); + if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) + MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); + if (attr->mod_fields_bitmap & + MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { + MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); + MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); + MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); + MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); + } + if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { + MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); + MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); } ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), out, sizeof(out)); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 3747ef9e33..ec6467d927 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -74,6 +74,9 @@ struct mlx5_hca_vdpa_attr { uint32_t log_doorbell_stride:5; uint32_t log_doorbell_bar_size:5; uint32_t queue_counters_valid:1; + uint32_t vnet_modify_ext:1; + uint32_t virtio_net_q_addr_modify:1; + uint32_t virtio_q_index_modify:1; uint32_t max_num_virtio_queues; struct { uint32_t a; @@ -465,7 +468,7 @@ struct mlx5_devx_virtq_attr { uint32_t tis_id; uint32_t counters_obj_id; uint64_t dirty_bitmap_addr; - uint64_t type; + uint64_t mod_fields_bitmap; uint64_t desc_addr; uint64_t used_addr; uint64_t available_addr; @@ -475,6 +478,7 @@ struct mlx5_devx_virtq_attr { uint64_t offset; } umems[3]; uint8_t error_type; + uint8_t q_type; }; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 8a2f55c33e..5f58a6ee1d 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1802,7 +1802,9 @@ struct mlx5_ifc_virtio_emulation_cap_bits { u8 virtio_queue_type[0x8]; u8 reserved_at_20[0x13]; u8 log_doorbell_stride[0x5]; - u8 reserved_at_3b[0x3]; + u8 vnet_modify_ext[0x1]; + u8 virtio_net_q_addr_modify[0x1]; + u8 virtio_q_index_modify[0x1]; u8 log_doorbell_bar_size[0x5]; u8 doorbell_bar_offset[0x40]; u8 reserved_at_80[0x8]; @@ -3024,6 +3026,15 @@ enum { MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0), MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3), MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4), + MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD = (1UL << 5), + MLX5_VIRTQ_MODIFY_TYPE_ADDR = (1UL << 6), + MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX = (1UL << 7), + MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX = (1UL << 8), + MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE = (1UL << 9), + MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0 = (1UL << 10), + MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY = (1UL << 11), + MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK = (1UL << 12), + MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE = (1UL << 13), }; struct mlx5_ifc_virtio_q_bits { From patchwork Mon Jun 6 11:20:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112354 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7B649A0543; Mon, 6 Jun 2022 13:23:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8F6B542B75; Mon, 6 Jun 2022 13:22:19 +0200 (CEST) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2089.outbound.protection.outlook.com [40.107.243.89]) by mails.dpdk.org (Postfix) with ESMTP id 3BEFD40A7F for ; Mon, 6 Jun 2022 13:22:18 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jh3zcu3KiAcPBSgylppN2G76GSOxa/2sktcPTpS/GTEj/ABVIvsLdgR5EpxXTL9p16sWsMYuepmPVIEx65l9Sc7WtLK+cJhyaqZVPAJbZVRe5XtacEkTfoJN33g9EhHFnvfLi+oVs7CxS1+avNdoZZt5v41fUvGoNMi9CeudAV+ShSaJCHDjLQmqJWvosljGHdhtIC2zyN+Xh5QKpIv9K6hO3GgmY7hjlOMMKFtDZHUQRwMm74ZIoVHsjYiDP7WHnWt5o+0dUQxVv6y/6dz221lZL8lTGabPCI2k3Wa2AUcV3NnWoAzjkizlOuPRBpRlQLH8hmzROLLRigGzoJcQbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=//TCfW2+w1eAVfja1DoKg8YmRkJwwGXbi0BAHQBxa6I=; b=QligIL+cwejlX/LG/yuxnz1JWY1VrBfMt8qBjh9uJT6FW+jHrxsJ9Q+75vehXfpfaChFor7aB7eMyaZhfU9+APd/Abn8cXcig9Dm73B9OuIXniUD8zFjiKusXTi4j8O8QBegKOZr1gBcmcGIXC46ewCo6d9mlg9A0knpsD76I2Gwtq8LqZRBGoqEZppzlJ0PEQm9JUvlqBYKBDOPCMHAfE/U1YlSvspxpWLKKrHhoN464/Cm0mYbLcXbi6fEPUsucep/UjpusB/NUDZkcV9K4czCtwa8bnGsvx1c3UzOKJExAr+pfA59eGq3NXxqK8E+7IqJSXQcF2o1hKzfkCKqZw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.238) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=//TCfW2+w1eAVfja1DoKg8YmRkJwwGXbi0BAHQBxa6I=; b=jsR1tp2tL/aD1G8eBAZtzY+b4pO90hB1zkCy1YPvluQ55JwQqXPVzXlvaI58S9DTEueDE/9kbCeLdZsfNUZ3WIABET8vdhKpkdpIidYlGwUoqQpR1xOGH0GOWWt/ONwbsrQFe591zJ2jEHttsrKVUXl9urCEUpHT3+Mn7wlGTfkD2xies2pclit9bKN4gETB/cS6TLkjzdLTAfu3V+Vk32RQGylMiLA3WQo9WjqF/7lQ/JZcsuH3pK09vXcR1i6+NyrS05xcPhm05YxFxzX7Zq7tgXNMRd1YGmlQMecsNNYjMA9QSGgmQLK2Zl2Yh3bROg7HMcK3NHViWyFNESkT/w== Received: from DS7P222CA0015.NAMP222.PROD.OUTLOOK.COM (2603:10b6:8:2e::27) by BYAPR12MB3208.namprd12.prod.outlook.com (2603:10b6:a03:13b::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13; Mon, 6 Jun 2022 11:22:16 +0000 Received: from DM6NAM11FT033.eop-nam11.prod.protection.outlook.com (2603:10b6:8:2e:cafe::1e) by DS7P222CA0015.outlook.office365.com (2603:10b6:8:2e::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13 via Frontend Transport; Mon, 6 Jun 2022 11:22:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.238) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.238) by DM6NAM11FT033.mail.protection.outlook.com (10.13.172.221) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:15 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:22:15 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:22:12 -0700 From: Li Zhang To: , , , CC: , , , Subject: [PATCH 07/16] vdpa/mlx5: pre-create virtq in the prob Date: Mon, 6 Jun 2022 14:20:50 +0300 Message-ID: <20220606112109.208873-14-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3da35416-007c-4594-97f6-08da47aecfa7 X-MS-TrafficTypeDiagnostic: BYAPR12MB3208:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mvrFF4qiu1hvKmDg7aiSGkvqUc7t8tz8TVkK0HwSfUwGWZDqM0EdAWTEiwxzVLEHo2tAH0zxTGo7f9Ffs8B0ZRR63iTYarFsiLnC/sPOldHaWtAy2oG+1dh/JXOJqfLSz1O1TB+CQe6duj3pcTIDXUJv8txiniMASIe1605QJ1rqm6mRHYsCB8FRKU1q6CP0ho+BBMGzetSV3KObcBZpmCVYoocuwld5HYJKdJvDlOb4NnHuxu5DwK/Wuzbj/JoIg8uV0lVEw4Tg+LUk4NjXPOleD8CmlH4qAuBlgJAvH4akHjzAIPFoMoitvJYMC21CIiQqdT4Fzd2/bvTqBn/MYmFFfg2onylf2Z/QTn+Ijm8FJO/OiRRVHmNJJlD5Ll+HqgavXsIIslXS8aA2K9Igp6uYX6b0MVGSHIhSHR9Br0WroPQHvZyoN3jD+R/k9hJ0tSF08oQm4/m9jb9xNPrBWEpF94TASvGKQa86xQwxuf29EElIietej63ogNzMxrFx9A4A/BOSGVUi63LLkQ3LpVRDdHCWr17bUyfX/tJSFLD+I5LmztWN3P2s/mZOT71CyZd+cDmq5T1pf4JHi59zDQXffQgGDmVt5cjqnaLJgSZeK1f789QsuD07wzXUguyQ9AYnvfT9nFh/jrcSvtVHe8shC0WOORRsfBIFhnEYpmkLAKJBiD/9kUivxfgm20dM2Urm0/qGFHE4qTQ7kXLsjQ== X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(16526019)(186003)(110136005)(316002)(6636002)(107886003)(55016003)(4326008)(54906003)(70586007)(70206006)(6286002)(83380400001)(86362001)(1076003)(40460700003)(36756003)(426003)(36860700001)(6666004)(82310400005)(508600001)(356005)(26005)(7696005)(8936002)(8676002)(2616005)(336012)(2906002)(47076005)(5660300002)(81166007)(30864003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:22:15.8376 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3da35416-007c-4594-97f6-08da47aecfa7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3208 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org dev_config operation is called in LM progress. LM time is very critical because all the VM packets are dropped directly at that time. Move the virtq creation to probe time and only modify the configuration later in the dev_config stage using the new ability to modify virtq. This optimization accelerates the LM process and reduces its time by 70%. Signed-off-by: Li Zhang --- drivers/vdpa/mlx5/mlx5_vdpa.h | 4 + drivers/vdpa/mlx5/mlx5_vdpa_lm.c | 13 +- drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 257 +++++++++++++++++----------- 3 files changed, 170 insertions(+), 104 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index bf82026e37..e5553079fe 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -80,6 +80,7 @@ struct mlx5_vdpa_virtq { uint16_t vq_size; uint8_t notifier_state; bool stopped; + uint32_t configured:1; uint32_t version; struct mlx5_vdpa_priv *priv; struct mlx5_devx_obj *virtq; @@ -489,4 +490,7 @@ mlx5_vdpa_virtq_stats_reset(struct mlx5_vdpa_priv *priv, int qid); */ void mlx5_vdpa_drain_cq(struct mlx5_vdpa_priv *priv); + +bool +mlx5_vdpa_is_modify_virtq_supported(struct mlx5_vdpa_priv *priv); #endif /* RTE_PMD_MLX5_VDPA_H_ */ diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_lm.c b/drivers/vdpa/mlx5/mlx5_vdpa_lm.c index 43a2b98255..a8faf0c116 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_lm.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_lm.c @@ -12,14 +12,17 @@ int mlx5_vdpa_logging_enable(struct mlx5_vdpa_priv *priv, int enable) { struct mlx5_devx_virtq_attr attr = { - .type = MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE, + .mod_fields_bitmap = + MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE, .dirty_bitmap_dump_enable = enable, }; + struct mlx5_vdpa_virtq *virtq; int i; for (i = 0; i < priv->nr_virtqs; ++i) { attr.queue_index = i; - if (!priv->virtqs[i].virtq) { + virtq = &priv->virtqs[i]; + if (!virtq->configured) { DRV_LOG(DEBUG, "virtq %d is invalid for dirty bitmap " "enabling.", i); } else if (mlx5_devx_cmd_modify_virtq(priv->virtqs[i].virtq, @@ -37,10 +40,11 @@ mlx5_vdpa_dirty_bitmap_set(struct mlx5_vdpa_priv *priv, uint64_t log_base, uint64_t log_size) { struct mlx5_devx_virtq_attr attr = { - .type = MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS, + .mod_fields_bitmap = MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS, .dirty_bitmap_addr = log_base, .dirty_bitmap_size = log_size, }; + struct mlx5_vdpa_virtq *virtq; int i; int ret = mlx5_os_wrapped_mkey_create(priv->cdev->ctx, priv->cdev->pd, priv->cdev->pdn, @@ -54,7 +58,8 @@ mlx5_vdpa_dirty_bitmap_set(struct mlx5_vdpa_priv *priv, uint64_t log_base, attr.dirty_bitmap_mkey = priv->lm_mr.lkey; for (i = 0; i < priv->nr_virtqs; ++i) { attr.queue_index = i; - if (!priv->virtqs[i].virtq) { + virtq = &priv->virtqs[i]; + if (!virtq->configured) { DRV_LOG(DEBUG, "virtq %d is invalid for LM.", i); } else if (mlx5_devx_cmd_modify_virtq(priv->virtqs[i].virtq, &attr)) { diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c index 6637ba1503..55cbc9fad2 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c @@ -75,6 +75,7 @@ mlx5_vdpa_virtqs_cleanup(struct mlx5_vdpa_priv *priv) for (i = 0; i < priv->caps.max_num_virtio_queues; i++) { struct mlx5_vdpa_virtq *virtq = &priv->virtqs[i]; + virtq->configured = 0; for (j = 0; j < RTE_DIM(virtq->umems); ++j) { if (virtq->umems[j].obj) { claim_zero(mlx5_glue->devx_umem_dereg @@ -111,11 +112,12 @@ mlx5_vdpa_virtq_unset(struct mlx5_vdpa_virtq *virtq) rte_intr_fd_set(virtq->intr_handle, -1); } rte_intr_instance_free(virtq->intr_handle); - if (virtq->virtq) { + if (virtq->configured) { ret = mlx5_vdpa_virtq_stop(virtq->priv, virtq->index); if (ret) DRV_LOG(WARNING, "Failed to stop virtq %d.", virtq->index); + virtq->configured = 0; claim_zero(mlx5_devx_cmd_destroy(virtq->virtq)); } virtq->virtq = NULL; @@ -138,7 +140,7 @@ int mlx5_vdpa_virtq_modify(struct mlx5_vdpa_virtq *virtq, int state) { struct mlx5_devx_virtq_attr attr = { - .type = MLX5_VIRTQ_MODIFY_TYPE_STATE, + .mod_fields_bitmap = MLX5_VIRTQ_MODIFY_TYPE_STATE, .state = state ? MLX5_VIRTQ_STATE_RDY : MLX5_VIRTQ_STATE_SUSPEND, .queue_index = virtq->index, @@ -153,7 +155,7 @@ mlx5_vdpa_virtq_stop(struct mlx5_vdpa_priv *priv, int index) struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index]; int ret; - if (virtq->stopped) + if (virtq->stopped || !virtq->configured) return 0; ret = mlx5_vdpa_virtq_modify(virtq, 0); if (ret) @@ -209,51 +211,54 @@ mlx5_vdpa_hva_to_gpa(struct rte_vhost_memory *mem, uint64_t hva) } static int -mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index) +mlx5_vdpa_virtq_sub_objs_prepare(struct mlx5_vdpa_priv *priv, + struct mlx5_devx_virtq_attr *attr, + struct rte_vhost_vring *vq, int index) { struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index]; - struct rte_vhost_vring vq; - struct mlx5_devx_virtq_attr attr = {0}; uint64_t gpa; int ret; unsigned int i; - uint16_t last_avail_idx; - uint16_t last_used_idx; - uint16_t event_num = MLX5_EVENT_TYPE_OBJECT_CHANGE; - uint64_t cookie; - - ret = rte_vhost_get_vhost_vring(priv->vid, index, &vq); - if (ret) - return -1; - if (vq.size == 0) - return 0; - virtq->index = index; - virtq->vq_size = vq.size; - attr.tso_ipv4 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO4)); - attr.tso_ipv6 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO6)); - attr.tx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_CSUM)); - attr.rx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_GUEST_CSUM)); - attr.virtio_version_1_0 = !!(priv->features & (1ULL << - VIRTIO_F_VERSION_1)); - attr.type = (priv->features & (1ULL << VIRTIO_F_RING_PACKED)) ? + uint16_t last_avail_idx = 0; + uint16_t last_used_idx = 0; + + if (virtq->virtq) + attr->mod_fields_bitmap = MLX5_VIRTQ_MODIFY_TYPE_STATE | + MLX5_VIRTQ_MODIFY_TYPE_ADDR | + MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX | + MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX | + MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0 | + MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE | + MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY | + MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK | + MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE; + attr->tso_ipv4 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO4)); + attr->tso_ipv6 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO6)); + attr->tx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_CSUM)); + attr->rx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_GUEST_CSUM)); + attr->virtio_version_1_0 = + !!(priv->features & (1ULL << VIRTIO_F_VERSION_1)); + attr->q_type = + (priv->features & (1ULL << VIRTIO_F_RING_PACKED)) ? MLX5_VIRTQ_TYPE_PACKED : MLX5_VIRTQ_TYPE_SPLIT; /* * No need event QPs creation when the guest in poll mode or when the * capability allows it. */ - attr.event_mode = vq.callfd != -1 || !(priv->caps.event_mode & (1 << - MLX5_VIRTQ_EVENT_MODE_NO_MSIX)) ? - MLX5_VIRTQ_EVENT_MODE_QP : - MLX5_VIRTQ_EVENT_MODE_NO_MSIX; - if (attr.event_mode == MLX5_VIRTQ_EVENT_MODE_QP) { - ret = mlx5_vdpa_event_qp_prepare(priv, vq.size, vq.callfd, - &virtq->eqp); + attr->event_mode = vq->callfd != -1 || + !(priv->caps.event_mode & (1 << MLX5_VIRTQ_EVENT_MODE_NO_MSIX)) ? + MLX5_VIRTQ_EVENT_MODE_QP : MLX5_VIRTQ_EVENT_MODE_NO_MSIX; + if (attr->event_mode == MLX5_VIRTQ_EVENT_MODE_QP) { + ret = mlx5_vdpa_event_qp_prepare(priv, + vq->size, vq->callfd, &virtq->eqp); if (ret) { - DRV_LOG(ERR, "Failed to create event QPs for virtq %d.", + DRV_LOG(ERR, + "Failed to create event QPs for virtq %d.", index); return -1; } - attr.qp_id = virtq->eqp.fw_qp->id; + attr->mod_fields_bitmap |= MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE; + attr->qp_id = virtq->eqp.fw_qp->id; } else { DRV_LOG(INFO, "Virtq %d is, for sure, working by poll mode, no" " need event QPs and event mechanism.", index); @@ -265,77 +270,82 @@ mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index) if (!virtq->counters) { DRV_LOG(ERR, "Failed to create virtq couners for virtq" " %d.", index); - goto error; + return -1; } - attr.counters_obj_id = virtq->counters->id; + attr->counters_obj_id = virtq->counters->id; } /* Setup 3 UMEMs for each virtq. */ - for (i = 0; i < RTE_DIM(virtq->umems); ++i) { - uint32_t size; - void *buf; - struct mlx5dv_devx_umem *obj; - - size = priv->caps.umems[i].a * vq.size + priv->caps.umems[i].b; - if (virtq->umems[i].size == size && - virtq->umems[i].obj != NULL) { - /* Reuse registered memory. */ - memset(virtq->umems[i].buf, 0, size); - goto reuse; - } - if (virtq->umems[i].obj) - claim_zero(mlx5_glue->devx_umem_dereg + if (virtq->virtq) { + for (i = 0; i < RTE_DIM(virtq->umems); ++i) { + uint32_t size; + void *buf; + struct mlx5dv_devx_umem *obj; + + size = + priv->caps.umems[i].a * vq->size + priv->caps.umems[i].b; + if (virtq->umems[i].size == size && + virtq->umems[i].obj != NULL) { + /* Reuse registered memory. */ + memset(virtq->umems[i].buf, 0, size); + goto reuse; + } + if (virtq->umems[i].obj) + claim_zero(mlx5_glue->devx_umem_dereg (virtq->umems[i].obj)); - if (virtq->umems[i].buf) - rte_free(virtq->umems[i].buf); - virtq->umems[i].size = 0; - virtq->umems[i].obj = NULL; - virtq->umems[i].buf = NULL; - buf = rte_zmalloc(__func__, size, 4096); - if (buf == NULL) { - DRV_LOG(ERR, "Cannot allocate umem %d memory for virtq" + if (virtq->umems[i].buf) + rte_free(virtq->umems[i].buf); + virtq->umems[i].size = 0; + virtq->umems[i].obj = NULL; + virtq->umems[i].buf = NULL; + buf = rte_zmalloc(__func__, + size, 4096); + if (buf == NULL) { + DRV_LOG(ERR, "Cannot allocate umem %d memory for virtq" " %u.", i, index); - goto error; - } - obj = mlx5_glue->devx_umem_reg(priv->cdev->ctx, buf, size, - IBV_ACCESS_LOCAL_WRITE); - if (obj == NULL) { - DRV_LOG(ERR, "Failed to register umem %d for virtq %u.", + return -1; + } + obj = mlx5_glue->devx_umem_reg(priv->cdev->ctx, + buf, size, IBV_ACCESS_LOCAL_WRITE); + if (obj == NULL) { + DRV_LOG(ERR, "Failed to register umem %d for virtq %u.", i, index); - goto error; - } - virtq->umems[i].size = size; - virtq->umems[i].buf = buf; - virtq->umems[i].obj = obj; + rte_free(buf); + return -1; + } + virtq->umems[i].size = size; + virtq->umems[i].buf = buf; + virtq->umems[i].obj = obj; reuse: - attr.umems[i].id = virtq->umems[i].obj->umem_id; - attr.umems[i].offset = 0; - attr.umems[i].size = virtq->umems[i].size; + attr->umems[i].id = virtq->umems[i].obj->umem_id; + attr->umems[i].offset = 0; + attr->umems[i].size = virtq->umems[i].size; + } } - if (attr.type == MLX5_VIRTQ_TYPE_SPLIT) { + if (attr->q_type == MLX5_VIRTQ_TYPE_SPLIT) { gpa = mlx5_vdpa_hva_to_gpa(priv->vmem, - (uint64_t)(uintptr_t)vq.desc); + (uint64_t)(uintptr_t)vq->desc); if (!gpa) { DRV_LOG(ERR, "Failed to get descriptor ring GPA."); - goto error; + return -1; } - attr.desc_addr = gpa; + attr->desc_addr = gpa; gpa = mlx5_vdpa_hva_to_gpa(priv->vmem, - (uint64_t)(uintptr_t)vq.used); + (uint64_t)(uintptr_t)vq->used); if (!gpa) { DRV_LOG(ERR, "Failed to get GPA for used ring."); - goto error; + return -1; } - attr.used_addr = gpa; + attr->used_addr = gpa; gpa = mlx5_vdpa_hva_to_gpa(priv->vmem, - (uint64_t)(uintptr_t)vq.avail); + (uint64_t)(uintptr_t)vq->avail); if (!gpa) { DRV_LOG(ERR, "Failed to get GPA for available ring."); - goto error; + return -1; } - attr.available_addr = gpa; + attr->available_addr = gpa; } - ret = rte_vhost_get_vring_base(priv->vid, index, &last_avail_idx, - &last_used_idx); + ret = rte_vhost_get_vring_base(priv->vid, + index, &last_avail_idx, &last_used_idx); if (ret) { last_avail_idx = 0; last_used_idx = 0; @@ -345,24 +355,71 @@ mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index) "virtq %d.", priv->vid, last_avail_idx, last_used_idx, index); } - attr.hw_available_index = last_avail_idx; - attr.hw_used_index = last_used_idx; - attr.q_size = vq.size; - attr.mkey = priv->gpa_mkey_index; - attr.tis_id = priv->tiss[(index / 2) % priv->num_lag_ports]->id; - attr.queue_index = index; - attr.pd = priv->cdev->pdn; - attr.hw_latency_mode = priv->hw_latency_mode; - attr.hw_max_latency_us = priv->hw_max_latency_us; - attr.hw_max_pending_comp = priv->hw_max_pending_comp; - virtq->virtq = mlx5_devx_cmd_create_virtq(priv->cdev->ctx, &attr); + attr->hw_available_index = last_avail_idx; + attr->hw_used_index = last_used_idx; + attr->q_size = vq->size; + attr->mkey = priv->gpa_mkey_index; + attr->tis_id = priv->tiss[(index / 2) % priv->num_lag_ports]->id; + attr->queue_index = index; + attr->pd = priv->cdev->pdn; + attr->hw_latency_mode = priv->hw_latency_mode; + attr->hw_max_latency_us = priv->hw_max_latency_us; + attr->hw_max_pending_comp = priv->hw_max_pending_comp; + if (attr->hw_latency_mode || attr->hw_max_latency_us || + attr->hw_max_pending_comp) + attr->mod_fields_bitmap |= MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD; + return 0; +} + +bool +mlx5_vdpa_is_modify_virtq_supported(struct mlx5_vdpa_priv *priv) +{ + return (priv->caps.vnet_modify_ext && + priv->caps.virtio_net_q_addr_modify && + priv->caps.virtio_q_index_modify) ? true : false; +} + +static int +mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index) +{ + struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index]; + struct rte_vhost_vring vq; + struct mlx5_devx_virtq_attr attr = {0}; + int ret; + uint16_t event_num = MLX5_EVENT_TYPE_OBJECT_CHANGE; + uint64_t cookie; + + ret = rte_vhost_get_vhost_vring(priv->vid, index, &vq); + if (ret) + return -1; + if (vq.size == 0) + return 0; virtq->priv = priv; - if (!virtq->virtq) + virtq->stopped = 0; + ret = mlx5_vdpa_virtq_sub_objs_prepare(priv, &attr, + &vq, index); + if (ret) { + DRV_LOG(ERR, "Failed to setup update virtq attr" + " %d.", index); goto error; - claim_zero(rte_vhost_enable_guest_notification(priv->vid, index, 1)); - if (mlx5_vdpa_virtq_modify(virtq, 1)) + } + if (!virtq->virtq) { + virtq->index = index; + virtq->vq_size = vq.size; + virtq->virtq = mlx5_devx_cmd_create_virtq(priv->cdev->ctx, + &attr); + if (!virtq->virtq) + goto error; + attr.mod_fields_bitmap = MLX5_VIRTQ_MODIFY_TYPE_STATE; + } + attr.state = MLX5_VIRTQ_STATE_RDY; + ret = mlx5_devx_cmd_modify_virtq(virtq->virtq, &attr); + if (ret) { + DRV_LOG(ERR, "Failed to modify virtq %d.", index); goto error; - virtq->priv = priv; + } + claim_zero(rte_vhost_enable_guest_notification(priv->vid, index, 1)); + virtq->configured = 1; rte_write32(virtq->index, priv->virtq_db_addr); /* Setup doorbell mapping. */ virtq->intr_handle = @@ -553,7 +610,7 @@ mlx5_vdpa_virtq_enable(struct mlx5_vdpa_priv *priv, int index, int enable) return 0; DRV_LOG(INFO, "Virtq %d was modified, recreate it.", index); } - if (virtq->virtq) { + if (virtq->configured) { virtq->enable = 0; if (is_virtq_recvq(virtq->index, priv->nr_virtqs)) { ret = mlx5_vdpa_steer_update(priv); From patchwork Mon Jun 6 11:20:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112356 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4A769A0543; Mon, 6 Jun 2022 13:23:28 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A541142826; Mon, 6 Jun 2022 13:22:27 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2069.outbound.protection.outlook.com [40.107.220.69]) by mails.dpdk.org (Postfix) with ESMTP id A564D427F0 for ; Mon, 6 Jun 2022 13:22:25 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GmLEZLeD01TbP94q3WC+l92RgRGkeVniLOU8lStUils1ACoTAvUViM9TNlzqYugcsGEDkUx6DmNjpbx2KOi8MUnvoOacms8/6DEkfKnqEaaOHiTwPO/AUNHvTBQ+FgZ4+j0KBZ4biwK42+jGfHJxTaObTlFkpeig57Wk/8b5m04kG85A4qtqttp0gdE5mCMQDXBJSojzXm84wLPxeTctttSvQ5y/smJcrczqS17tWuxOf9JIqz379KETOFWdJB8CjZo5ioro5LkKELxrkfK6OJccEA2dtYvhXSbgVYFeWWcVC8hP+QvMJ+4s/zY1cVTKlZl9pxCAK+L8v2akoseGsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=//TCfW2+w1eAVfja1DoKg8YmRkJwwGXbi0BAHQBxa6I=; b=aFF5EUYfhPFNqS7uiFVLDBLd4O7wtRwOcz490aq+2Czoh+1xIj74ATyDwQnWVp3vMyMKQM+SikxwktJFjU+PAYH5e2agWNe7Bim6FWCNg43OdN/PqwVtm7BYmL75zrqmvqXFcvuJoyDFjnLDDn29h+xOgBbqu2gTgIzeiJP5tqn5Y/c+yr6Njl7D+8/ZOK0WXa46DFx/vVodMltxmPy2Wd7CZm6JVIky6bOm55TyWFuclv++QywCZNmkVyHNFdOtaIeTekNlF6BB1u4e2SRgTK9NyY772o83BOy8jgd7yBaJZIK/aRuhpvrMJwTlaZkYmGINVUsCwV20KhaI69vq2A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=//TCfW2+w1eAVfja1DoKg8YmRkJwwGXbi0BAHQBxa6I=; b=dRWCQXAiqx63R5fQ90yH5qhU/CGdMW62eFyreo0P/xpjljjDyO4+mSCsflHenWQgT9Zq+FnIF1rYdJBk9xetbADDV3faWLhP4fO5F7gGCKZr5aR0PwYlyWbyAuILB+SievXqrtbXFKAw5cTtYjrwFUpfGGKlfG4+ndd38aKdtoA+UDy6WF2CPcQMFO6z1shKPDVjUAEZ08gqA89nicEWkWZw1DNep5loOHyMAPF2A3xTrlBBQ1iDAGYxLyQ94sNKEz8a/y/a+gfZ/7C7n9Qb/jdldZQ1m2ig+vtjHTGkLk9/OgV/eiWREpDHJX2b6vGuxpQGk1D1KIiohNEIjkpagA== Received: from BN6PR16CA0044.namprd16.prod.outlook.com (2603:10b6:405:14::30) by MWHPR12MB1727.namprd12.prod.outlook.com (2603:10b6:300:107::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13; Mon, 6 Jun 2022 11:22:22 +0000 Received: from BN8NAM11FT061.eop-nam11.prod.protection.outlook.com (2603:10b6:405:14:cafe::38) by BN6PR16CA0044.outlook.office365.com (2603:10b6:405:14::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.19 via Frontend Transport; Mon, 6 Jun 2022 11:22:21 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by BN8NAM11FT061.mail.protection.outlook.com (10.13.177.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:21 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:22:20 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:22:18 -0700 From: Li Zhang To: , , , CC: , , , Subject: [PATCH v1 08/17] vdpa/mlx5: pre-create virtq in the prob Date: Mon, 6 Jun 2022 14:20:52 +0300 Message-ID: <20220606112109.208873-16-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d7b3e2a2-931e-485d-a540-08da47aed32b X-MS-TrafficTypeDiagnostic: MWHPR12MB1727:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: O/X2ah0+d4iBGdLNXuxUCxRd3B4dfaUNXXj1dpHrrFt+U4q1g2ob9yOUu6mVgOV5feTRhA0rz04sDIjsq08xgEglyfyY+dt2K9Q8m8fXkp4I6GZ0w0d/vE5gkftN97YaQ842ztuhJ/BI0HcQE2hcyukrxLUfDVlKF2ACKXSZs2u0cBDV7wL52m5HvUwgEqAp/P5HliiaqkJALOhZVFczMbmriKnVItmuVM8aNOrzxSwgB1/+WTYeKhp8kMMUnai0W4ENiPeLDB0mDEc5el3zIBubDxsRHEwwBtRIXOlBTjECN02UnW7X9Qu+kHMbtkgafODkafgroAUz9JvMAp21QzN4gRzxnopqs+3NDDzHAvo0AK28zF1y4iaO/Fu/aj8smVpl6OmJKa8pirAaMXBYImvS7TbimOIYYhrunRXPXUvxAQvS416/3V/e34gOX5CVW/h9smaQxiKEqZ0rFSoYUL9dVdCZhpN+NeBj1LDV/i92hhF8tJy6w+gJn+o+xFt2CoDGnDxbMU2+j6xqIQxMHuoM23NP+rfaGIxssg23Wp7DgfcwWurC+MbgmJel4d2n6YL2mkr6iX3OFLhvGojQzKe6nVHpxLHyJZ/nY7zqEDuCUhGr1iUXbn20BKjpv+5GsP6VJSsa0L4wRbmFwGSVhExfV38A4hlCSuLdlyHjKj+i85+9D0rxn0R+2Uk1Ae2Vrup62nRBcp/S+Ds0tKwJ8A== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(30864003)(4326008)(8676002)(81166007)(8936002)(2616005)(5660300002)(36756003)(36860700001)(82310400005)(356005)(70586007)(70206006)(2906002)(55016003)(316002)(86362001)(6666004)(83380400001)(47076005)(426003)(336012)(508600001)(54906003)(110136005)(6636002)(6286002)(7696005)(26005)(40460700003)(107886003)(1076003)(16526019)(186003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:22:21.6581 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d7b3e2a2-931e-485d-a540-08da47aed32b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1727 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org dev_config operation is called in LM progress. LM time is very critical because all the VM packets are dropped directly at that time. Move the virtq creation to probe time and only modify the configuration later in the dev_config stage using the new ability to modify virtq. This optimization accelerates the LM process and reduces its time by 70%. Signed-off-by: Li Zhang --- drivers/vdpa/mlx5/mlx5_vdpa.h | 4 + drivers/vdpa/mlx5/mlx5_vdpa_lm.c | 13 +- drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 257 +++++++++++++++++----------- 3 files changed, 170 insertions(+), 104 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index bf82026e37..e5553079fe 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -80,6 +80,7 @@ struct mlx5_vdpa_virtq { uint16_t vq_size; uint8_t notifier_state; bool stopped; + uint32_t configured:1; uint32_t version; struct mlx5_vdpa_priv *priv; struct mlx5_devx_obj *virtq; @@ -489,4 +490,7 @@ mlx5_vdpa_virtq_stats_reset(struct mlx5_vdpa_priv *priv, int qid); */ void mlx5_vdpa_drain_cq(struct mlx5_vdpa_priv *priv); + +bool +mlx5_vdpa_is_modify_virtq_supported(struct mlx5_vdpa_priv *priv); #endif /* RTE_PMD_MLX5_VDPA_H_ */ diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_lm.c b/drivers/vdpa/mlx5/mlx5_vdpa_lm.c index 43a2b98255..a8faf0c116 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_lm.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_lm.c @@ -12,14 +12,17 @@ int mlx5_vdpa_logging_enable(struct mlx5_vdpa_priv *priv, int enable) { struct mlx5_devx_virtq_attr attr = { - .type = MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE, + .mod_fields_bitmap = + MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE, .dirty_bitmap_dump_enable = enable, }; + struct mlx5_vdpa_virtq *virtq; int i; for (i = 0; i < priv->nr_virtqs; ++i) { attr.queue_index = i; - if (!priv->virtqs[i].virtq) { + virtq = &priv->virtqs[i]; + if (!virtq->configured) { DRV_LOG(DEBUG, "virtq %d is invalid for dirty bitmap " "enabling.", i); } else if (mlx5_devx_cmd_modify_virtq(priv->virtqs[i].virtq, @@ -37,10 +40,11 @@ mlx5_vdpa_dirty_bitmap_set(struct mlx5_vdpa_priv *priv, uint64_t log_base, uint64_t log_size) { struct mlx5_devx_virtq_attr attr = { - .type = MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS, + .mod_fields_bitmap = MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS, .dirty_bitmap_addr = log_base, .dirty_bitmap_size = log_size, }; + struct mlx5_vdpa_virtq *virtq; int i; int ret = mlx5_os_wrapped_mkey_create(priv->cdev->ctx, priv->cdev->pd, priv->cdev->pdn, @@ -54,7 +58,8 @@ mlx5_vdpa_dirty_bitmap_set(struct mlx5_vdpa_priv *priv, uint64_t log_base, attr.dirty_bitmap_mkey = priv->lm_mr.lkey; for (i = 0; i < priv->nr_virtqs; ++i) { attr.queue_index = i; - if (!priv->virtqs[i].virtq) { + virtq = &priv->virtqs[i]; + if (!virtq->configured) { DRV_LOG(DEBUG, "virtq %d is invalid for LM.", i); } else if (mlx5_devx_cmd_modify_virtq(priv->virtqs[i].virtq, &attr)) { diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c index 6637ba1503..55cbc9fad2 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c @@ -75,6 +75,7 @@ mlx5_vdpa_virtqs_cleanup(struct mlx5_vdpa_priv *priv) for (i = 0; i < priv->caps.max_num_virtio_queues; i++) { struct mlx5_vdpa_virtq *virtq = &priv->virtqs[i]; + virtq->configured = 0; for (j = 0; j < RTE_DIM(virtq->umems); ++j) { if (virtq->umems[j].obj) { claim_zero(mlx5_glue->devx_umem_dereg @@ -111,11 +112,12 @@ mlx5_vdpa_virtq_unset(struct mlx5_vdpa_virtq *virtq) rte_intr_fd_set(virtq->intr_handle, -1); } rte_intr_instance_free(virtq->intr_handle); - if (virtq->virtq) { + if (virtq->configured) { ret = mlx5_vdpa_virtq_stop(virtq->priv, virtq->index); if (ret) DRV_LOG(WARNING, "Failed to stop virtq %d.", virtq->index); + virtq->configured = 0; claim_zero(mlx5_devx_cmd_destroy(virtq->virtq)); } virtq->virtq = NULL; @@ -138,7 +140,7 @@ int mlx5_vdpa_virtq_modify(struct mlx5_vdpa_virtq *virtq, int state) { struct mlx5_devx_virtq_attr attr = { - .type = MLX5_VIRTQ_MODIFY_TYPE_STATE, + .mod_fields_bitmap = MLX5_VIRTQ_MODIFY_TYPE_STATE, .state = state ? MLX5_VIRTQ_STATE_RDY : MLX5_VIRTQ_STATE_SUSPEND, .queue_index = virtq->index, @@ -153,7 +155,7 @@ mlx5_vdpa_virtq_stop(struct mlx5_vdpa_priv *priv, int index) struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index]; int ret; - if (virtq->stopped) + if (virtq->stopped || !virtq->configured) return 0; ret = mlx5_vdpa_virtq_modify(virtq, 0); if (ret) @@ -209,51 +211,54 @@ mlx5_vdpa_hva_to_gpa(struct rte_vhost_memory *mem, uint64_t hva) } static int -mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index) +mlx5_vdpa_virtq_sub_objs_prepare(struct mlx5_vdpa_priv *priv, + struct mlx5_devx_virtq_attr *attr, + struct rte_vhost_vring *vq, int index) { struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index]; - struct rte_vhost_vring vq; - struct mlx5_devx_virtq_attr attr = {0}; uint64_t gpa; int ret; unsigned int i; - uint16_t last_avail_idx; - uint16_t last_used_idx; - uint16_t event_num = MLX5_EVENT_TYPE_OBJECT_CHANGE; - uint64_t cookie; - - ret = rte_vhost_get_vhost_vring(priv->vid, index, &vq); - if (ret) - return -1; - if (vq.size == 0) - return 0; - virtq->index = index; - virtq->vq_size = vq.size; - attr.tso_ipv4 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO4)); - attr.tso_ipv6 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO6)); - attr.tx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_CSUM)); - attr.rx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_GUEST_CSUM)); - attr.virtio_version_1_0 = !!(priv->features & (1ULL << - VIRTIO_F_VERSION_1)); - attr.type = (priv->features & (1ULL << VIRTIO_F_RING_PACKED)) ? + uint16_t last_avail_idx = 0; + uint16_t last_used_idx = 0; + + if (virtq->virtq) + attr->mod_fields_bitmap = MLX5_VIRTQ_MODIFY_TYPE_STATE | + MLX5_VIRTQ_MODIFY_TYPE_ADDR | + MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX | + MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX | + MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0 | + MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE | + MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY | + MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK | + MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE; + attr->tso_ipv4 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO4)); + attr->tso_ipv6 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO6)); + attr->tx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_CSUM)); + attr->rx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_GUEST_CSUM)); + attr->virtio_version_1_0 = + !!(priv->features & (1ULL << VIRTIO_F_VERSION_1)); + attr->q_type = + (priv->features & (1ULL << VIRTIO_F_RING_PACKED)) ? MLX5_VIRTQ_TYPE_PACKED : MLX5_VIRTQ_TYPE_SPLIT; /* * No need event QPs creation when the guest in poll mode or when the * capability allows it. */ - attr.event_mode = vq.callfd != -1 || !(priv->caps.event_mode & (1 << - MLX5_VIRTQ_EVENT_MODE_NO_MSIX)) ? - MLX5_VIRTQ_EVENT_MODE_QP : - MLX5_VIRTQ_EVENT_MODE_NO_MSIX; - if (attr.event_mode == MLX5_VIRTQ_EVENT_MODE_QP) { - ret = mlx5_vdpa_event_qp_prepare(priv, vq.size, vq.callfd, - &virtq->eqp); + attr->event_mode = vq->callfd != -1 || + !(priv->caps.event_mode & (1 << MLX5_VIRTQ_EVENT_MODE_NO_MSIX)) ? + MLX5_VIRTQ_EVENT_MODE_QP : MLX5_VIRTQ_EVENT_MODE_NO_MSIX; + if (attr->event_mode == MLX5_VIRTQ_EVENT_MODE_QP) { + ret = mlx5_vdpa_event_qp_prepare(priv, + vq->size, vq->callfd, &virtq->eqp); if (ret) { - DRV_LOG(ERR, "Failed to create event QPs for virtq %d.", + DRV_LOG(ERR, + "Failed to create event QPs for virtq %d.", index); return -1; } - attr.qp_id = virtq->eqp.fw_qp->id; + attr->mod_fields_bitmap |= MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE; + attr->qp_id = virtq->eqp.fw_qp->id; } else { DRV_LOG(INFO, "Virtq %d is, for sure, working by poll mode, no" " need event QPs and event mechanism.", index); @@ -265,77 +270,82 @@ mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index) if (!virtq->counters) { DRV_LOG(ERR, "Failed to create virtq couners for virtq" " %d.", index); - goto error; + return -1; } - attr.counters_obj_id = virtq->counters->id; + attr->counters_obj_id = virtq->counters->id; } /* Setup 3 UMEMs for each virtq. */ - for (i = 0; i < RTE_DIM(virtq->umems); ++i) { - uint32_t size; - void *buf; - struct mlx5dv_devx_umem *obj; - - size = priv->caps.umems[i].a * vq.size + priv->caps.umems[i].b; - if (virtq->umems[i].size == size && - virtq->umems[i].obj != NULL) { - /* Reuse registered memory. */ - memset(virtq->umems[i].buf, 0, size); - goto reuse; - } - if (virtq->umems[i].obj) - claim_zero(mlx5_glue->devx_umem_dereg + if (virtq->virtq) { + for (i = 0; i < RTE_DIM(virtq->umems); ++i) { + uint32_t size; + void *buf; + struct mlx5dv_devx_umem *obj; + + size = + priv->caps.umems[i].a * vq->size + priv->caps.umems[i].b; + if (virtq->umems[i].size == size && + virtq->umems[i].obj != NULL) { + /* Reuse registered memory. */ + memset(virtq->umems[i].buf, 0, size); + goto reuse; + } + if (virtq->umems[i].obj) + claim_zero(mlx5_glue->devx_umem_dereg (virtq->umems[i].obj)); - if (virtq->umems[i].buf) - rte_free(virtq->umems[i].buf); - virtq->umems[i].size = 0; - virtq->umems[i].obj = NULL; - virtq->umems[i].buf = NULL; - buf = rte_zmalloc(__func__, size, 4096); - if (buf == NULL) { - DRV_LOG(ERR, "Cannot allocate umem %d memory for virtq" + if (virtq->umems[i].buf) + rte_free(virtq->umems[i].buf); + virtq->umems[i].size = 0; + virtq->umems[i].obj = NULL; + virtq->umems[i].buf = NULL; + buf = rte_zmalloc(__func__, + size, 4096); + if (buf == NULL) { + DRV_LOG(ERR, "Cannot allocate umem %d memory for virtq" " %u.", i, index); - goto error; - } - obj = mlx5_glue->devx_umem_reg(priv->cdev->ctx, buf, size, - IBV_ACCESS_LOCAL_WRITE); - if (obj == NULL) { - DRV_LOG(ERR, "Failed to register umem %d for virtq %u.", + return -1; + } + obj = mlx5_glue->devx_umem_reg(priv->cdev->ctx, + buf, size, IBV_ACCESS_LOCAL_WRITE); + if (obj == NULL) { + DRV_LOG(ERR, "Failed to register umem %d for virtq %u.", i, index); - goto error; - } - virtq->umems[i].size = size; - virtq->umems[i].buf = buf; - virtq->umems[i].obj = obj; + rte_free(buf); + return -1; + } + virtq->umems[i].size = size; + virtq->umems[i].buf = buf; + virtq->umems[i].obj = obj; reuse: - attr.umems[i].id = virtq->umems[i].obj->umem_id; - attr.umems[i].offset = 0; - attr.umems[i].size = virtq->umems[i].size; + attr->umems[i].id = virtq->umems[i].obj->umem_id; + attr->umems[i].offset = 0; + attr->umems[i].size = virtq->umems[i].size; + } } - if (attr.type == MLX5_VIRTQ_TYPE_SPLIT) { + if (attr->q_type == MLX5_VIRTQ_TYPE_SPLIT) { gpa = mlx5_vdpa_hva_to_gpa(priv->vmem, - (uint64_t)(uintptr_t)vq.desc); + (uint64_t)(uintptr_t)vq->desc); if (!gpa) { DRV_LOG(ERR, "Failed to get descriptor ring GPA."); - goto error; + return -1; } - attr.desc_addr = gpa; + attr->desc_addr = gpa; gpa = mlx5_vdpa_hva_to_gpa(priv->vmem, - (uint64_t)(uintptr_t)vq.used); + (uint64_t)(uintptr_t)vq->used); if (!gpa) { DRV_LOG(ERR, "Failed to get GPA for used ring."); - goto error; + return -1; } - attr.used_addr = gpa; + attr->used_addr = gpa; gpa = mlx5_vdpa_hva_to_gpa(priv->vmem, - (uint64_t)(uintptr_t)vq.avail); + (uint64_t)(uintptr_t)vq->avail); if (!gpa) { DRV_LOG(ERR, "Failed to get GPA for available ring."); - goto error; + return -1; } - attr.available_addr = gpa; + attr->available_addr = gpa; } - ret = rte_vhost_get_vring_base(priv->vid, index, &last_avail_idx, - &last_used_idx); + ret = rte_vhost_get_vring_base(priv->vid, + index, &last_avail_idx, &last_used_idx); if (ret) { last_avail_idx = 0; last_used_idx = 0; @@ -345,24 +355,71 @@ mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index) "virtq %d.", priv->vid, last_avail_idx, last_used_idx, index); } - attr.hw_available_index = last_avail_idx; - attr.hw_used_index = last_used_idx; - attr.q_size = vq.size; - attr.mkey = priv->gpa_mkey_index; - attr.tis_id = priv->tiss[(index / 2) % priv->num_lag_ports]->id; - attr.queue_index = index; - attr.pd = priv->cdev->pdn; - attr.hw_latency_mode = priv->hw_latency_mode; - attr.hw_max_latency_us = priv->hw_max_latency_us; - attr.hw_max_pending_comp = priv->hw_max_pending_comp; - virtq->virtq = mlx5_devx_cmd_create_virtq(priv->cdev->ctx, &attr); + attr->hw_available_index = last_avail_idx; + attr->hw_used_index = last_used_idx; + attr->q_size = vq->size; + attr->mkey = priv->gpa_mkey_index; + attr->tis_id = priv->tiss[(index / 2) % priv->num_lag_ports]->id; + attr->queue_index = index; + attr->pd = priv->cdev->pdn; + attr->hw_latency_mode = priv->hw_latency_mode; + attr->hw_max_latency_us = priv->hw_max_latency_us; + attr->hw_max_pending_comp = priv->hw_max_pending_comp; + if (attr->hw_latency_mode || attr->hw_max_latency_us || + attr->hw_max_pending_comp) + attr->mod_fields_bitmap |= MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD; + return 0; +} + +bool +mlx5_vdpa_is_modify_virtq_supported(struct mlx5_vdpa_priv *priv) +{ + return (priv->caps.vnet_modify_ext && + priv->caps.virtio_net_q_addr_modify && + priv->caps.virtio_q_index_modify) ? true : false; +} + +static int +mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index) +{ + struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index]; + struct rte_vhost_vring vq; + struct mlx5_devx_virtq_attr attr = {0}; + int ret; + uint16_t event_num = MLX5_EVENT_TYPE_OBJECT_CHANGE; + uint64_t cookie; + + ret = rte_vhost_get_vhost_vring(priv->vid, index, &vq); + if (ret) + return -1; + if (vq.size == 0) + return 0; virtq->priv = priv; - if (!virtq->virtq) + virtq->stopped = 0; + ret = mlx5_vdpa_virtq_sub_objs_prepare(priv, &attr, + &vq, index); + if (ret) { + DRV_LOG(ERR, "Failed to setup update virtq attr" + " %d.", index); goto error; - claim_zero(rte_vhost_enable_guest_notification(priv->vid, index, 1)); - if (mlx5_vdpa_virtq_modify(virtq, 1)) + } + if (!virtq->virtq) { + virtq->index = index; + virtq->vq_size = vq.size; + virtq->virtq = mlx5_devx_cmd_create_virtq(priv->cdev->ctx, + &attr); + if (!virtq->virtq) + goto error; + attr.mod_fields_bitmap = MLX5_VIRTQ_MODIFY_TYPE_STATE; + } + attr.state = MLX5_VIRTQ_STATE_RDY; + ret = mlx5_devx_cmd_modify_virtq(virtq->virtq, &attr); + if (ret) { + DRV_LOG(ERR, "Failed to modify virtq %d.", index); goto error; - virtq->priv = priv; + } + claim_zero(rte_vhost_enable_guest_notification(priv->vid, index, 1)); + virtq->configured = 1; rte_write32(virtq->index, priv->virtq_db_addr); /* Setup doorbell mapping. */ virtq->intr_handle = @@ -553,7 +610,7 @@ mlx5_vdpa_virtq_enable(struct mlx5_vdpa_priv *priv, int index, int enable) return 0; DRV_LOG(INFO, "Virtq %d was modified, recreate it.", index); } - if (virtq->virtq) { + if (virtq->configured) { virtq->enable = 0; if (is_virtq_recvq(virtq->index, priv->nr_virtqs)) { ret = mlx5_vdpa_steer_update(priv); From patchwork Mon Jun 6 11:20:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112357 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 177ABA0543; Mon, 6 Jun 2022 13:23:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D08C042BB0; Mon, 6 Jun 2022 13:22:29 +0200 (CEST) Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam07on2042.outbound.protection.outlook.com [40.107.212.42]) by mails.dpdk.org (Postfix) with ESMTP id D56C442847 for ; Mon, 6 Jun 2022 13:22:27 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jnkyVDNuOlZA7Ke4ofyhybt8BScNW6E6Y09KGKSGI/5OW8hPybnGuzqVUPjm3pBjtE7jFbPx2SQKxxydBqUNasTRnG7Y04ed/ld+xy6l0wA22SOfbEzDrdSGIe+ukq2WQevq6sMFfMBXr4twlf7IgYaruZPblHU2hGXDZn3o5Uh0ZqmTLd5btOM0HZNhGSqw/pngrgn3k2EboMhpzAgAh9+WD1kl3KiIy26XDZN5hVrC/MRNetpQCub01gG30/s9BIbSqONqoCSbKkL9bELAWCkXFiD5exUrGVTSMcbBWint61491QYcTYQaVgk+NWlkfpZ3i5rTtiskGeM3OSdKzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=XqNbWRPHMsXACs/uazvCCyzyqWQJ9s88f+cJ+vO9Xjc=; b=IQthvaon0yg4Ltr63ajXnYHlFV4YL4iHlqf26udumZQJ3sSX1ddLh6cgYU5t9JgwRGtZSi5lcFLUSDeU/4prdlteuBFz1nIw2F136lxlfRJiStc+633rTrmg/FeDBm07JSz8K4QiObYHO0PUXNXNw4fMmXX/e3VIHMw2Wo9bwI/L4kUHUMVg7ohak9QG509/ZGDNKdnqRtNd13suSN/NC4DFBmRUzrgemmNsu1R3EeZsaQHGg6jHfjrJJOKf6y73CL/dWALqyTCnYS4PH+W8IXy5oVsYFyVcNSbdhRvPuzSG2fZXZ+xu0e/2jTrsmJ433NiXL2zntEvSfi2MdDourg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.238) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XqNbWRPHMsXACs/uazvCCyzyqWQJ9s88f+cJ+vO9Xjc=; b=S8kTftDIuW8dl9a/jXnFfNRlV3rE5aC7yfZFWU+gJIfnIKVI6gbh8C8TMq8AUUJUN2jtDuAEojKpXXDLZxvo2EA1X+GsTy6S1SlTs/iqHpWvqUXsKUmWeTjXpMIZrI2/CXmsUY9PrrYSgsEdKrjSSrfN6enwX/Qhy4Ti7l6rkTJbnty2v9IfdKiyVfTX41QLI+xZDZZuEwwyyYrGBa16yZnfMF8Hz80LFmqbbTJgmwj1cPdzCVDB1H6nV2BzAfXG7ygOMzfcKNNd8h6rgFYN6NN0BdigY+z6GYcFLVn0nQOvlHnDNkuLQqTJWXNnJBhUvVYiQcZB+mecU9BP7JmLUw== Received: from DS7P222CA0004.NAMP222.PROD.OUTLOOK.COM (2603:10b6:8:2e::14) by BN6PR12MB1922.namprd12.prod.outlook.com (2603:10b6:404:106::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13; Mon, 6 Jun 2022 11:22:25 +0000 Received: from DM6NAM11FT030.eop-nam11.prod.protection.outlook.com (2603:10b6:8:2e:cafe::7) by DS7P222CA0004.outlook.office365.com (2603:10b6:8:2e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.238) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.238) by DM6NAM11FT030.mail.protection.outlook.com (10.13.172.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:24 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:22:23 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:22:20 -0700 From: Li Zhang To: , , , CC: , , , Subject: [PATCH 09/16] vdpa/mlx5: add multi-thread management for configuration Date: Mon, 6 Jun 2022 14:20:53 +0300 Message-ID: <20220606112109.208873-17-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 275e16fa-3a0f-4e98-b2dc-08da47aed4c1 X-MS-TrafficTypeDiagnostic: BN6PR12MB1922:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: M9s8l+y7ucv+VDO5xeqHSXcIO5i2i3QQADrhpG7xlEF+OzeqG8HKb6SfU/BZqCev3U9frZW6pDWLyxsu2Pp/SKEnKPSX+PvULsYnRt0MoftFWDQzb9QzunMQkU2yAmwXgsoY+uduRBSCsgR4t+oyVEGYCoOKLzwPxPkB0MPgBexPq6oQF5Asp7Bs58rQvivGhfeBDBzWrdfpiJKrOgLig+WwI4cOej/RKXJVFtRVl1Tjdpod1gfW9imlhT8Ml3nNi0uNkHWNDG3QXon5lo0GLyVkySqToYDbHBsGDgESAWqzoUGcTF75hfo/Z5rESlWQgDhnTwKO5P3q6hRJLxkhg3Awqv3BNIX9Xh27NAZZTbGFX+fSPhZ+dboEAqW2PyvKdivWNMgTzjpBMIJd52YbP7tEZizFiugzvjMJ1uHA/LIBlgtz4UXixWV3+1rodEEvM6RaYQYuq/mfowdUGAl6w/TAj+K3sOsIowqT4rHzly883oeht7mx4fSIGiBVY0mkT0VrLWmqSi5uQu2ccOGoHeaLB6QirjrXeIRV27U+dPz7r/AtEWpfFUxzGb4dyFeyuR2zZSdMMAWf8ihOiNZY6kVYo0wTO46v6Pc3eB5/4Kh2Uh4KbucLlWbiWzaZW+gINuAfRMftqF8TEe1Nn7u+0B+CDUdAevzCMndID3VwMBtIaC+cghwqdcj4tAYXybHlFie3Qg3xg9YtVXoS525X8Q== X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(6666004)(55016003)(82310400005)(36860700001)(7696005)(83380400001)(6286002)(26005)(107886003)(508600001)(186003)(1076003)(16526019)(47076005)(426003)(2616005)(336012)(8936002)(86362001)(40460700003)(4326008)(8676002)(30864003)(70586007)(70206006)(81166007)(5660300002)(2906002)(356005)(6636002)(54906003)(36756003)(316002)(110136005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:22:24.4129 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 275e16fa-3a0f-4e98-b2dc-08da47aed4c1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1922 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The LM process includes a lot of objects creations and destructions in the source and the destination servers. As much as LM time increases, the packet drop of the VM increases. To improve LM time need to parallel the configurations for mlx5 FW. Add internal multi-thread management in the driver for it. A new devarg defines the number of threads and their CPU. The management is shared between all the devices of the driver. Since the event_core also affects the datapath events thread, reduce the priority of the datapath event thread to allow fast configuration of the devices doing the LM. Signed-off-by: Li Zhang --- doc/guides/vdpadevs/mlx5.rst | 11 +++ drivers/vdpa/mlx5/meson.build | 1 + drivers/vdpa/mlx5/mlx5_vdpa.c | 41 ++++++++ drivers/vdpa/mlx5/mlx5_vdpa.h | 36 +++++++ drivers/vdpa/mlx5/mlx5_vdpa_cthread.c | 129 ++++++++++++++++++++++++++ drivers/vdpa/mlx5/mlx5_vdpa_event.c | 2 +- drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 8 +- 7 files changed, 223 insertions(+), 5 deletions(-) create mode 100644 drivers/vdpa/mlx5/mlx5_vdpa_cthread.c diff --git a/doc/guides/vdpadevs/mlx5.rst b/doc/guides/vdpadevs/mlx5.rst index 0ad77bf535..b75a01688d 100644 --- a/doc/guides/vdpadevs/mlx5.rst +++ b/doc/guides/vdpadevs/mlx5.rst @@ -78,6 +78,17 @@ for an additional list of options shared with other mlx5 drivers. CPU core number to set polling thread affinity to, default to control plane cpu. +- ``max_conf_threads`` parameter [int] + + Allow the driver to use internal threads to obtain fast configuration. + All the threads will be open on the same core of the event completion queue scheduling thread. + + - 0, default, don't use internal threads for configuration. + + - 1 - 256, number of internal threads in addition to the caller thread (8 is suggested). + This value, if not 0, should be the same for all the devices; + the first prob will take it with the event_core for all the multi-thread configurations in the driver. + - ``hw_latency_mode`` parameter [int] The completion queue moderation mode: diff --git a/drivers/vdpa/mlx5/meson.build b/drivers/vdpa/mlx5/meson.build index 0fa82ad257..9d8dbb1a82 100644 --- a/drivers/vdpa/mlx5/meson.build +++ b/drivers/vdpa/mlx5/meson.build @@ -15,6 +15,7 @@ sources = files( 'mlx5_vdpa_virtq.c', 'mlx5_vdpa_steer.c', 'mlx5_vdpa_lm.c', + 'mlx5_vdpa_cthread.c', ) cflags_options = [ '-std=c11', diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c index e5a11f72fd..a9d023ed08 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa.c @@ -50,6 +50,8 @@ TAILQ_HEAD(mlx5_vdpa_privs, mlx5_vdpa_priv) priv_list = TAILQ_HEAD_INITIALIZER(priv_list); static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER; +struct mlx5_vdpa_conf_thread_mng conf_thread_mng; + static void mlx5_vdpa_dev_release(struct mlx5_vdpa_priv *priv); static struct mlx5_vdpa_priv * @@ -493,6 +495,29 @@ mlx5_vdpa_args_check_handler(const char *key, const char *val, void *opaque) DRV_LOG(WARNING, "Invalid event_core %s.", val); else priv->event_core = tmp; + } else if (strcmp(key, "max_conf_threads") == 0) { + if (tmp) { + priv->use_c_thread = true; + if (!conf_thread_mng.initializer_priv) { + conf_thread_mng.initializer_priv = priv; + if (tmp > MLX5_VDPA_MAX_C_THRD) { + DRV_LOG(WARNING, + "Invalid max_conf_threads %s " + "and set max_conf_threads to %d", + val, MLX5_VDPA_MAX_C_THRD); + tmp = MLX5_VDPA_MAX_C_THRD; + } + conf_thread_mng.max_thrds = tmp; + } else if (tmp != conf_thread_mng.max_thrds) { + DRV_LOG(WARNING, + "max_conf_threads is PMD argument and not per device, " + "only the first device configuration set it, current value is %d " + "and will not be changed to %d.", + conf_thread_mng.max_thrds, (int)tmp); + } + } else { + priv->use_c_thread = false; + } } else if (strcmp(key, "hw_latency_mode") == 0) { priv->hw_latency_mode = (uint32_t)tmp; } else if (strcmp(key, "hw_max_latency_us") == 0) { @@ -521,6 +546,9 @@ mlx5_vdpa_config_get(struct mlx5_kvargs_ctrl *mkvlist, "hw_max_latency_us", "hw_max_pending_comp", "no_traffic_time", + "queue_size", + "queues", + "max_conf_threads", NULL, }; @@ -725,6 +753,13 @@ mlx5_vdpa_dev_probe(struct mlx5_common_device *cdev, pthread_mutex_init(&priv->steer_update_lock, NULL); priv->cdev = cdev; mlx5_vdpa_config_get(mkvlist, priv); + if (priv->use_c_thread) { + if (conf_thread_mng.initializer_priv == priv) + if (mlx5_vdpa_mult_threads_create(priv->event_core)) + goto error; + __atomic_fetch_add(&conf_thread_mng.refcnt, 1, + __ATOMIC_RELAXED); + } if (mlx5_vdpa_create_dev_resources(priv)) goto error; priv->vdev = rte_vdpa_register_device(cdev->dev, &mlx5_vdpa_ops); @@ -739,6 +774,8 @@ mlx5_vdpa_dev_probe(struct mlx5_common_device *cdev, pthread_mutex_unlock(&priv_list_lock); return 0; error: + if (conf_thread_mng.initializer_priv == priv) + mlx5_vdpa_mult_threads_destroy(false); if (priv) mlx5_vdpa_dev_release(priv); return -rte_errno; @@ -806,6 +843,10 @@ mlx5_vdpa_dev_release(struct mlx5_vdpa_priv *priv) mlx5_vdpa_release_dev_resources(priv); if (priv->vdev) rte_vdpa_unregister_device(priv->vdev); + if (priv->use_c_thread) + if (__atomic_fetch_sub(&conf_thread_mng.refcnt, + 1, __ATOMIC_RELAXED) == 1) + mlx5_vdpa_mult_threads_destroy(true); rte_free(priv); } diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index 3fd5eefc5e..4e7c2557b7 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -73,6 +73,22 @@ enum { MLX5_VDPA_NOTIFIER_STATE_ERR }; +#define MLX5_VDPA_MAX_C_THRD 256 + +/* Generic mlx5_vdpa_c_thread information. */ +struct mlx5_vdpa_c_thread { + pthread_t tid; +}; + +struct mlx5_vdpa_conf_thread_mng { + void *initializer_priv; + uint32_t refcnt; + uint32_t max_thrds; + pthread_mutex_t cthrd_lock; + struct mlx5_vdpa_c_thread cthrd[MLX5_VDPA_MAX_C_THRD]; +}; +extern struct mlx5_vdpa_conf_thread_mng conf_thread_mng; + struct mlx5_vdpa_virtq { SLIST_ENTRY(mlx5_vdpa_virtq) next; uint8_t enable; @@ -126,6 +142,7 @@ enum mlx5_dev_state { struct mlx5_vdpa_priv { TAILQ_ENTRY(mlx5_vdpa_priv) next; bool connected; + bool use_c_thread; enum mlx5_dev_state state; rte_spinlock_t db_lock; pthread_mutex_t steer_update_lock; @@ -496,4 +513,23 @@ mlx5_vdpa_drain_cq(struct mlx5_vdpa_priv *priv); bool mlx5_vdpa_is_modify_virtq_supported(struct mlx5_vdpa_priv *priv); + +/** + * Create configuration multi-threads resource + * + * @param[in] cpu_core + * CPU core number to set configuration threads affinity to. + * + * @return + * 0 on success, a negative value otherwise. + */ +int +mlx5_vdpa_mult_threads_create(int cpu_core); + +/** + * Destroy configuration multi-threads resource + * + */ +void +mlx5_vdpa_mult_threads_destroy(bool need_unlock); #endif /* RTE_PMD_MLX5_VDPA_H_ */ diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c new file mode 100644 index 0000000000..ba7d8b63b3 --- /dev/null +++ b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2022 NVIDIA Corporation & Affiliates + */ +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "mlx5_vdpa_utils.h" +#include "mlx5_vdpa.h" + +static void * +mlx5_vdpa_c_thread_handle(void *arg) +{ + /* To be added later. */ + return arg; +} + +static void +mlx5_vdpa_c_thread_destroy(uint32_t thrd_idx, bool need_unlock) +{ + if (conf_thread_mng.cthrd[thrd_idx].tid) { + pthread_cancel(conf_thread_mng.cthrd[thrd_idx].tid); + pthread_join(conf_thread_mng.cthrd[thrd_idx].tid, NULL); + conf_thread_mng.cthrd[thrd_idx].tid = 0; + if (need_unlock) + pthread_mutex_init(&conf_thread_mng.cthrd_lock, NULL); + } +} + +static int +mlx5_vdpa_c_thread_create(int cpu_core) +{ + const struct sched_param sp = { + .sched_priority = sched_get_priority_max(SCHED_RR), + }; + rte_cpuset_t cpuset; + pthread_attr_t attr; + uint32_t thrd_idx; + char name[32]; + int ret; + + pthread_mutex_lock(&conf_thread_mng.cthrd_lock); + pthread_attr_init(&attr); + ret = pthread_attr_setschedpolicy(&attr, SCHED_RR); + if (ret) { + DRV_LOG(ERR, "Failed to set thread sched policy = RR."); + goto c_thread_err; + } + ret = pthread_attr_setschedparam(&attr, &sp); + if (ret) { + DRV_LOG(ERR, "Failed to set thread priority."); + goto c_thread_err; + } + for (thrd_idx = 0; thrd_idx < conf_thread_mng.max_thrds; + thrd_idx++) { + ret = pthread_create(&conf_thread_mng.cthrd[thrd_idx].tid, + &attr, mlx5_vdpa_c_thread_handle, + (void *)&conf_thread_mng); + if (ret) { + DRV_LOG(ERR, "Failed to create vdpa multi-threads %d.", + thrd_idx); + goto c_thread_err; + } + CPU_ZERO(&cpuset); + if (cpu_core != -1) + CPU_SET(cpu_core, &cpuset); + else + cpuset = rte_lcore_cpuset(rte_get_main_lcore()); + ret = pthread_setaffinity_np( + conf_thread_mng.cthrd[thrd_idx].tid, + sizeof(cpuset), &cpuset); + if (ret) { + DRV_LOG(ERR, "Failed to set thread affinity for " + "vdpa multi-threads %d.", thrd_idx); + goto c_thread_err; + } + snprintf(name, sizeof(name), "vDPA-mthread-%d", thrd_idx); + ret = pthread_setname_np( + conf_thread_mng.cthrd[thrd_idx].tid, name); + if (ret) + DRV_LOG(ERR, "Failed to set vdpa multi-threads name %s.", + name); + else + DRV_LOG(DEBUG, "Thread name: %s.", name); + } + pthread_mutex_unlock(&conf_thread_mng.cthrd_lock); + return 0; +c_thread_err: + for (thrd_idx = 0; thrd_idx < conf_thread_mng.max_thrds; + thrd_idx++) + mlx5_vdpa_c_thread_destroy(thrd_idx, false); + pthread_mutex_unlock(&conf_thread_mng.cthrd_lock); + return -1; +} + +int +mlx5_vdpa_mult_threads_create(int cpu_core) +{ + pthread_mutex_init(&conf_thread_mng.cthrd_lock, NULL); + if (mlx5_vdpa_c_thread_create(cpu_core)) { + DRV_LOG(ERR, "Cannot create vDPA configuration threads."); + mlx5_vdpa_mult_threads_destroy(false); + return -1; + } + return 0; +} + +void +mlx5_vdpa_mult_threads_destroy(bool need_unlock) +{ + uint32_t thrd_idx; + + if (!conf_thread_mng.initializer_priv) + return; + for (thrd_idx = 0; thrd_idx < conf_thread_mng.max_thrds; + thrd_idx++) + mlx5_vdpa_c_thread_destroy(thrd_idx, need_unlock); + pthread_mutex_destroy(&conf_thread_mng.cthrd_lock); + memset(&conf_thread_mng, 0, sizeof(struct mlx5_vdpa_conf_thread_mng)); +} diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c index 2b0f5936d1..b45fbac146 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c @@ -507,7 +507,7 @@ mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv) pthread_attr_t attr; char name[16]; const struct sched_param sp = { - .sched_priority = sched_get_priority_max(SCHED_RR), + .sched_priority = sched_get_priority_max(SCHED_RR) - 1, }; if (!priv->eventc) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c index 138b7bdbc5..599809b09b 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c @@ -43,7 +43,7 @@ mlx5_vdpa_virtq_kick_handler(void *cb_arg) errno == EWOULDBLOCK || errno == EAGAIN) continue; - DRV_LOG(ERR, "Failed to read kickfd of virtq %d: %s", + DRV_LOG(ERR, "Failed to read kickfd of virtq %d: %s.", virtq->index, strerror(errno)); } break; @@ -57,7 +57,7 @@ mlx5_vdpa_virtq_kick_handler(void *cb_arg) rte_spinlock_unlock(&priv->db_lock); pthread_mutex_unlock(&virtq->virtq_lock); if (priv->state != MLX5_VDPA_STATE_CONFIGURED && !virtq->enable) { - DRV_LOG(ERR, "device %d queue %d down, skip kick handling", + DRV_LOG(ERR, "device %d queue %d down, skip kick handling.", priv->vid, virtq->index); return; } @@ -218,7 +218,7 @@ mlx5_vdpa_virtq_query(struct mlx5_vdpa_priv *priv, int index) return -1; } if (attr.state == MLX5_VIRTQ_STATE_ERROR) - DRV_LOG(WARNING, "vid %d vring %d hw error=%hhu", + DRV_LOG(WARNING, "vid %d vring %d hw error=%hhu.", priv->vid, index, attr.error_type); return 0; } @@ -380,7 +380,7 @@ mlx5_vdpa_virtq_sub_objs_prepare(struct mlx5_vdpa_priv *priv, if (ret) { last_avail_idx = 0; last_used_idx = 0; - DRV_LOG(WARNING, "Couldn't get vring base, idx are set to 0"); + DRV_LOG(WARNING, "Couldn't get vring base, idx are set to 0."); } else { DRV_LOG(INFO, "vid %d: Init last_avail_idx=%d, last_used_idx=%d for " "virtq %d.", priv->vid, last_avail_idx, From patchwork Mon Jun 6 11:20:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112360 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 89208A0543; Mon, 6 Jun 2022 13:24:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1B03942B78; Mon, 6 Jun 2022 13:22:37 +0200 (CEST) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2087.outbound.protection.outlook.com [40.107.93.87]) by mails.dpdk.org (Postfix) with ESMTP id 7506B4280B for ; Mon, 6 Jun 2022 13:22:35 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=G1+UFtgFqBJXyv2uiKOfRVZg5Wq7fvRKabZEgdhTZPKsk36wSd4bOfIA2VOsWWRsR05BX4wtX/hhWAXdU14ndlDgXC+6PnDoAORnpfETTq4RB5cXmn1T19gziLR2mCH/3HbaGLkx6IVXAgk6NPgzELtl10hmrnf/xzG+lPPgmxyguW9NFcu35SOKoz+jdc8cRQwhtQw+5XsG5sXT514drPIAWn2VJXub4KB+70XEK6RGjXVp/C74gHaB6cbTstjyoBVIX4luMOKBviya3NptYc02/TZYBmkdiiaanugNIzomLJoPhG7qpEnBT0JlJRPt/QAvgQoJ5NHQFY7uacJuZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=WPeiYEKr8Xl0aU3ahh2E84TguKGVfhqJFiY6ZoKAkqw=; b=OJjVIrlXxMKdwJW9mO36Qdyk1lQh9pqaglnmhQKySpEitc4HYNT2Rc8NiBqS6fopjy37lbAre2apVl6GHVxtaH9vowdYbAJog3fTGnmYbknKcfQPe4Z1a9mzsz2m4oYVGE4wlgCeCYS/WezE0pzMGIa9AeyQIjaGNJmBhdkKLQydK53/BP0NFAXOmxCf0q35mJuWpqjxskHQ8zE1T+iVEzSD5mrPqaGPrK/MdQvQqCFUvDrsYbPrHFvp7Ft5aqaKi/Q9Dcd2WMZtVPR4s/MxeZCKtTL+4LBajtOAJmd18XH/V0db+azkAcOnKKqD8OWBJLmmGaZAQ2mIR/Cx5lJ+6A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=WPeiYEKr8Xl0aU3ahh2E84TguKGVfhqJFiY6ZoKAkqw=; b=MxrG+YzcwVu6ZFtXQLQv8N46oP1asU8TLQV6gFEDRK1rUQqW61EP2Tsc9/5kz/z3BduxjMgxV21+FAJ8oenaxu8iAXtBk3Cr+eiAYRVgQ5wj7bpDryDlHZET0eb2dK3PaMnHTYw6cHQlqd3gCx9yhFtedQKPraZiatptUHfiT61saQN4XB37B5Tb1hMb+pXVlRdeKODT8G+f4FmubhiGNEVr0dhUtyfGi/aG8tx605Le8o+ix2EpD5AKAiiV3x6hcBQUdCEKIYE03ae4DpeG2tVG6czwkZZfrx5OetagrSmSiCDwpKM/GtqsghY8Do39Rn0+Yfze7pM80YjgHrsOSA== Received: from BN9PR03CA0548.namprd03.prod.outlook.com (2603:10b6:408:138::13) by CY4PR12MB1861.namprd12.prod.outlook.com (2603:10b6:903:11e::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13; Mon, 6 Jun 2022 11:22:34 +0000 Received: from BN8NAM11FT047.eop-nam11.prod.protection.outlook.com (2603:10b6:408:138:cafe::9) by BN9PR03CA0548.outlook.office365.com (2603:10b6:408:138::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.15 via Frontend Transport; Mon, 6 Jun 2022 11:22:33 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by BN8NAM11FT047.mail.protection.outlook.com (10.13.177.220) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:33 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:22:32 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:22:29 -0700 From: Li Zhang To: , , , CC: , , , Subject: [PATCH 10/16] vdpa/mlx5: add task ring for MT management Date: Mon, 6 Jun 2022 14:20:56 +0300 Message-ID: <20220606112109.208873-20-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c58c214c-7f62-4e89-5463-08da47aeda13 X-MS-TrafficTypeDiagnostic: CY4PR12MB1861:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: a8ltreDOQl7MvXScu9Q2F3ChC/n4Iq5mC3tKrFgRUxtPBn+edY7CP1RgBjlqfyM3r8pBjY1MNLECzOweo9S9DhagcA4O8UbDJTNHBdZSGacZ2pPmoudsB5NC5NaeyQoCeQ2XGPfJW0Yc3qLQ21bD8675Z2HnthxaiRAO7BkChUHO23xhy7e2df9yHvM/SCPKO8J7QHOwx8uTBVlAczEZXEwpacb3L+jUa4nDAN1gYgIoKtW/pMNskB7tRCckrKfK7hYKCueX80basi2Lr+f9eczjVWGvC8HX26W5SrI8y/jqMyw1Fs1YuwmKqIKegd5NWfW9+6BkYBcoQbCPvVLJw2pJ2ZC/HLEdyJ0I3AUk9ioIS4ARKewdJmzUVCN2ZDM2X2GR4bHJoZBBjfX/VbSHLSxh9MTb/Zky2n1XH300iyrBPcYh3qeMim0x7q5X5c25WkiCC+8X7bXqc96m6sYgEhyWQvMFd3WyQty3T0dqoiYw7zeJSCbpuHB+E+IpTDZnHUm8g0SmJ+JUDGYMzb9PhV/XDRQiJYF6C9Gk5sNbaR0qOl5o0kd4QWbrHaxv6YCyUkaIp2fWf2gjVEJhDE0PBib0ua4we6Azy7gUC1rs7nUuuB6pyfD64bhJ4yyfoJzpfWozYK1EmrBCnXx1OIdouxSqX7gpIRmn8OBSuvAbtR31RuwyaoBBHJb0uHSC7vflHbQVN175wO2Lkd97iT4rnw== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(16526019)(186003)(5660300002)(82310400005)(7696005)(316002)(4326008)(8676002)(70206006)(2906002)(81166007)(110136005)(2616005)(70586007)(1076003)(508600001)(356005)(336012)(40460700003)(107886003)(54906003)(6636002)(86362001)(26005)(36860700001)(6286002)(55016003)(83380400001)(36756003)(47076005)(426003)(6666004)(8936002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:22:33.2740 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c58c214c-7f62-4e89-5463-08da47aeda13 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1861 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The configuration threads tasks need a container to support multiple tasks assigned to a thread in parallel. Use rte_ring container per thread to manage the thread tasks without locks. The caller thread from the user context opens a task to a thread and enqueue it to the thread ring. The thread polls its ring and dequeue tasks. That’s why the ring should be in multi-producer and single consumer mode. Anatomic counter manages the tasks completion notification. The threads report errors to the caller by a dedicated error counter per task. Signed-off-by: Li Zhang --- drivers/vdpa/mlx5/mlx5_vdpa.h | 17 ++++ drivers/vdpa/mlx5/mlx5_vdpa_cthread.c | 115 +++++++++++++++++++++++++- 2 files changed, 130 insertions(+), 2 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index 4e7c2557b7..2bbb868ec6 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -74,10 +74,22 @@ enum { }; #define MLX5_VDPA_MAX_C_THRD 256 +#define MLX5_VDPA_MAX_TASKS_PER_THRD 4096 +#define MLX5_VDPA_TASKS_PER_DEV 64 + +/* Generic task information and size must be multiple of 4B. */ +struct mlx5_vdpa_task { + struct mlx5_vdpa_priv *priv; + uint32_t *remaining_cnt; + uint32_t *err_cnt; + uint32_t idx; +} __rte_packed __rte_aligned(4); /* Generic mlx5_vdpa_c_thread information. */ struct mlx5_vdpa_c_thread { pthread_t tid; + struct rte_ring *rng; + pthread_cond_t c_cond; }; struct mlx5_vdpa_conf_thread_mng { @@ -532,4 +544,9 @@ mlx5_vdpa_mult_threads_create(int cpu_core); */ void mlx5_vdpa_mult_threads_destroy(bool need_unlock); + +bool +mlx5_vdpa_task_add(struct mlx5_vdpa_priv *priv, + uint32_t thrd_idx, + uint32_t num); #endif /* RTE_PMD_MLX5_VDPA_H_ */ diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c index ba7d8b63b3..1fdc92d3ad 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c @@ -11,17 +11,103 @@ #include #include #include +#include #include #include "mlx5_vdpa_utils.h" #include "mlx5_vdpa.h" +static inline uint32_t +mlx5_vdpa_c_thrd_ring_dequeue_bulk(struct rte_ring *r, + void **obj, uint32_t n, uint32_t *avail) +{ + uint32_t m; + + m = rte_ring_dequeue_bulk_elem_start(r, obj, + sizeof(struct mlx5_vdpa_task), n, avail); + n = (m == n) ? n : 0; + rte_ring_dequeue_elem_finish(r, n); + return n; +} + +static inline uint32_t +mlx5_vdpa_c_thrd_ring_enqueue_bulk(struct rte_ring *r, + void * const *obj, uint32_t n, uint32_t *free) +{ + uint32_t m; + + m = rte_ring_enqueue_bulk_elem_start(r, n, free); + n = (m == n) ? n : 0; + rte_ring_enqueue_elem_finish(r, obj, + sizeof(struct mlx5_vdpa_task), n); + return n; +} + +bool +mlx5_vdpa_task_add(struct mlx5_vdpa_priv *priv, + uint32_t thrd_idx, + uint32_t num) +{ + struct rte_ring *rng = conf_thread_mng.cthrd[thrd_idx].rng; + struct mlx5_vdpa_task task[MLX5_VDPA_TASKS_PER_DEV]; + uint32_t i; + + MLX5_ASSERT(num <= MLX5_VDPA_TASKS_PER_DEV); + for (i = 0 ; i < num; i++) { + task[i].priv = priv; + /* To be added later. */ + } + if (!mlx5_vdpa_c_thrd_ring_enqueue_bulk(rng, (void **)&task, num, NULL)) + return -1; + for (i = 0 ; i < num; i++) + if (task[i].remaining_cnt) + __atomic_fetch_add(task[i].remaining_cnt, 1, + __ATOMIC_RELAXED); + /* wake up conf thread. */ + pthread_mutex_lock(&conf_thread_mng.cthrd_lock); + pthread_cond_signal(&conf_thread_mng.cthrd[thrd_idx].c_cond); + pthread_mutex_unlock(&conf_thread_mng.cthrd_lock); + return 0; +} + static void * mlx5_vdpa_c_thread_handle(void *arg) { - /* To be added later. */ - return arg; + struct mlx5_vdpa_conf_thread_mng *multhrd = arg; + pthread_t thread_id = pthread_self(); + struct mlx5_vdpa_priv *priv; + struct mlx5_vdpa_task task; + struct rte_ring *rng; + uint32_t thrd_idx; + uint32_t task_num; + + for (thrd_idx = 0; thrd_idx < multhrd->max_thrds; + thrd_idx++) + if (multhrd->cthrd[thrd_idx].tid == thread_id) + break; + if (thrd_idx >= multhrd->max_thrds) + return NULL; + rng = multhrd->cthrd[thrd_idx].rng; + while (1) { + task_num = mlx5_vdpa_c_thrd_ring_dequeue_bulk(rng, + (void **)&task, 1, NULL); + if (!task_num) { + /* No task and condition wait. */ + pthread_mutex_lock(&multhrd->cthrd_lock); + pthread_cond_wait( + &multhrd->cthrd[thrd_idx].c_cond, + &multhrd->cthrd_lock); + pthread_mutex_unlock(&multhrd->cthrd_lock); + } + priv = task.priv; + if (priv == NULL) + continue; + __atomic_fetch_sub(task.remaining_cnt, + 1, __ATOMIC_RELAXED); + /* To be added later. */ + } + return NULL; } static void @@ -34,6 +120,10 @@ mlx5_vdpa_c_thread_destroy(uint32_t thrd_idx, bool need_unlock) if (need_unlock) pthread_mutex_init(&conf_thread_mng.cthrd_lock, NULL); } + if (conf_thread_mng.cthrd[thrd_idx].rng) { + rte_ring_free(conf_thread_mng.cthrd[thrd_idx].rng); + conf_thread_mng.cthrd[thrd_idx].rng = NULL; + } } static int @@ -45,6 +135,7 @@ mlx5_vdpa_c_thread_create(int cpu_core) rte_cpuset_t cpuset; pthread_attr_t attr; uint32_t thrd_idx; + uint32_t ring_num; char name[32]; int ret; @@ -60,8 +151,26 @@ mlx5_vdpa_c_thread_create(int cpu_core) DRV_LOG(ERR, "Failed to set thread priority."); goto c_thread_err; } + ring_num = MLX5_VDPA_MAX_TASKS_PER_THRD / conf_thread_mng.max_thrds; + if (!ring_num) { + DRV_LOG(ERR, "Invalid ring number for thread."); + goto c_thread_err; + } for (thrd_idx = 0; thrd_idx < conf_thread_mng.max_thrds; thrd_idx++) { + snprintf(name, sizeof(name), "vDPA-mthread-ring-%d", + thrd_idx); + conf_thread_mng.cthrd[thrd_idx].rng = rte_ring_create_elem(name, + sizeof(struct mlx5_vdpa_task), ring_num, + rte_socket_id(), + RING_F_MP_HTS_ENQ | RING_F_MC_HTS_DEQ | + RING_F_EXACT_SZ); + if (!conf_thread_mng.cthrd[thrd_idx].rng) { + DRV_LOG(ERR, + "Failed to create vdpa multi-threads %d ring.", + thrd_idx); + goto c_thread_err; + } ret = pthread_create(&conf_thread_mng.cthrd[thrd_idx].tid, &attr, mlx5_vdpa_c_thread_handle, (void *)&conf_thread_mng); @@ -91,6 +200,8 @@ mlx5_vdpa_c_thread_create(int cpu_core) name); else DRV_LOG(DEBUG, "Thread name: %s.", name); + pthread_cond_init(&conf_thread_mng.cthrd[thrd_idx].c_cond, + NULL); } pthread_mutex_unlock(&conf_thread_mng.cthrd_lock); return 0; From patchwork Mon Jun 6 11:20:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112362 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 900A0A0543; Mon, 6 Jun 2022 13:24:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4B98441181; Mon, 6 Jun 2022 13:22:41 +0200 (CEST) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2063.outbound.protection.outlook.com [40.107.243.63]) by mails.dpdk.org (Postfix) with ESMTP id 21EA642BC7 for ; Mon, 6 Jun 2022 13:22:38 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UH8+xJyeIkM1/e4yO/iVEsKCfo0MwEWB40cG1m0jc+0pf1/YdIhgGkt2DictfmY4ilLcQb7kETImP5Vh7rV0RwgBj+NQnqsINStQYwefrFVLFG+plvXvmN1oH4teEK9aesrg0L5NpUOHoQw2iF4O6tBa/KSH10GwBlq/T0YhQ6cgZZrgfVhVKH5105R7t8TSNYcJvdsP9gwFW185oj+9lSaW5vnOD6aTte1EuKcTA5nscvb5MqZ3bgsnle74mv76kUq46o2puENelwEjUGNWLZXu0WGk2DjdB1LC93NcC58sy/v7Pi5iAQOvzXcqAvPeT5Su60WLXekGawhwV2zUlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=CVRcS2uqZd9Wh3g830a87N53PYxY8F6zN7aoMgp2IRU=; b=XRDFNBAp4aNLJqYwTPbBBZc+s/C1iiHRwNjRz/W3YZieNVyhuxdcwpossKy0f1S9LLzGtJVxTParEqsy3h8woZUBPcG5vPYsuROlCHUPfApPXzumdzA4kUzTRfOlxajIgbgWF2TSSlM/KzLHK65TsmPvwgh87BBjqiGoLtB6vt32w3su5Dy75OkuOGImUcFMMF41B+CgK3rfGVSbJf2kPA85pbyo6aFWxbTMlMRmH5tmzRco0eOtcr0fALX4CXps/EEalR23i5KSHvciWsqMgzbcrB3xBeQk72ZKSXevTXv7hV60AQ83z+zYyFtzLgHkFyvdoY43o15IMiwdncGpOA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.238) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CVRcS2uqZd9Wh3g830a87N53PYxY8F6zN7aoMgp2IRU=; b=ffzNBncaG4YUvzKaIh0I7tY8rSNs29Er0wRxyvPlye/1kUFlGNTzmp7MnWuHSc/lqMQrCc+38BdFxgDmZsyBjV1RMe2SdqX4Jae3UELdZrEPqNEie/38wpomUAs3Q/Jb5FbAufruWiv8EElg+VhBWEZG6irj21Cv/QdoA6jigzrIinnAosSX1FJZp/j15EzSeF0py+RqeDtiQ2hIO+ytuuLexp+LCedS1qgqW9esv/DwmUYvEHwyZ4wq8EplQs5NvJ40Vh1YzAWRGfzUXvivROYtJzBYWWlsIWLnrEIMSZKjFj3wVSYBephwkugHKrNnCp6XxV7bcEMr3UESukk0aA== Received: from DM6PR17CA0019.namprd17.prod.outlook.com (2603:10b6:5:1b3::32) by BN6PR12MB1363.namprd12.prod.outlook.com (2603:10b6:404:1f::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.12; Mon, 6 Jun 2022 11:22:36 +0000 Received: from DM6NAM11FT016.eop-nam11.prod.protection.outlook.com (2603:10b6:5:1b3:cafe::1b) by DM6PR17CA0019.outlook.office365.com (2603:10b6:5:1b3::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.18 via Frontend Transport; Mon, 6 Jun 2022 11:22:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.238) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.238) by DM6NAM11FT016.mail.protection.outlook.com (10.13.173.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:35 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:22:35 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:22:32 -0700 From: Li Zhang To: , , , CC: , , , Subject: [PATCH 11/16] vdpa/mlx5: add MT task for VM memory registration Date: Mon, 6 Jun 2022 14:20:57 +0300 Message-ID: <20220606112109.208873-21-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6a2a2d9c-1b13-4b52-2a7f-08da47aedb9b X-MS-TrafficTypeDiagnostic: BN6PR12MB1363:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: j1n+RxYwZaYtWCLxkpVhJreYpK6usF+uH/g2wv2GGazewcM486/E8/Y3KcNGjLMTneOwxi3XXJ+RZ1mRXH0q9zCvDNU78khMbFaqb6V1gqqG4viFmUO3vFKedklXmxPdqj0PJR7PMsL12Ixbc8/fkXso2AaCmmqnahdx9m4k5DDyXaJ8oBr8LRtIjpZED+ClPAKS2V0wwddrsEXFGa2vZaddQn2Ms4GTl5XS5+0LtKdlHegj+SfFqoZaduHUM+3RkU3Bqnon53ytQoRS9LglsYT22igpnIiB/UCdgOWz27DbgRdhJ92+OKH7sH5+72IRugl7/BQT7hlNAB84tFVWE4cC/mSn7VgEyU0WhFpcZ6L2vrvAHgE7m47x41eMVDdd9TagVqSvV5+QwEwsLrDNri2BiuZdk0YHZNyOy9d0VDLAqd1Igf8v9/BAhLJeyZNU/Z9ZBpDEjZG3Sg5KIgcyJSvw9VBL2ZTzJbAwLUy319uGkHX3kFGxRnNmyWqLo1qPqVtoZTyzbV6L9v60Qp9tL/gAedfmQWTqdt81khDxCY04ufYLPYWOKNlP7pONTs6cLcsUWxw8iYJ+x2j8BtkQ2igV721hnVeaXDvRXDwLg2DZ7Qw09Cj459MmmJuCieBvMlImtG7dQ4LZsAmjrzwK+JcXvpwx0o9UAAb8Liocn85W4SmypUAE0lxYLfLEE1q87x7FnNHekl0IxcDNQmykVA== X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(6286002)(426003)(16526019)(36860700001)(110136005)(82310400005)(6636002)(1076003)(186003)(107886003)(2906002)(40460700003)(508600001)(47076005)(83380400001)(54906003)(336012)(2616005)(70586007)(70206006)(55016003)(6666004)(36756003)(81166007)(356005)(8676002)(4326008)(7696005)(30864003)(26005)(5660300002)(86362001)(316002)(8936002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:22:35.9044 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a2a2d9c-1b13-4b52-2a7f-08da47aedb9b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT016.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1363 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The driver creates a direct MR object of the HW for each VM memory region, which maps the VM physical address to the actual physical address. Later, after all the MRs are ready, the driver creates an indirect MR to group all the direct MRs into one virtual space from the HW perspective. Create direct MRs in parallel using the MT mechanism. After completion, the primary thread creates the indirect MR needed for the following virtqs configurations. This optimization accelerrate the LM process and reduce its time by 5%. Signed-off-by: Li Zhang --- drivers/vdpa/mlx5/mlx5_vdpa.c | 1 - drivers/vdpa/mlx5/mlx5_vdpa.h | 31 ++- drivers/vdpa/mlx5/mlx5_vdpa_cthread.c | 47 ++++- drivers/vdpa/mlx5/mlx5_vdpa_mem.c | 270 ++++++++++++++++++-------- drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 6 +- 5 files changed, 258 insertions(+), 97 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c index a9d023ed08..e3b32fa087 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa.c @@ -768,7 +768,6 @@ mlx5_vdpa_dev_probe(struct mlx5_common_device *cdev, rte_errno = rte_errno ? rte_errno : EINVAL; goto error; } - SLIST_INIT(&priv->mr_list); pthread_mutex_lock(&priv_list_lock); TAILQ_INSERT_TAIL(&priv_list, priv, next); pthread_mutex_unlock(&priv_list_lock); diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index 2bbb868ec6..3316ce42be 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -59,7 +59,6 @@ struct mlx5_vdpa_event_qp { }; struct mlx5_vdpa_query_mr { - SLIST_ENTRY(mlx5_vdpa_query_mr) next; union { struct ibv_mr *mr; struct mlx5_devx_obj *mkey; @@ -76,10 +75,17 @@ enum { #define MLX5_VDPA_MAX_C_THRD 256 #define MLX5_VDPA_MAX_TASKS_PER_THRD 4096 #define MLX5_VDPA_TASKS_PER_DEV 64 +#define MLX5_VDPA_MAX_MRS 0xFFFF + +/* Vdpa task types. */ +enum mlx5_vdpa_task_type { + MLX5_VDPA_TASK_REG_MR = 1, +}; /* Generic task information and size must be multiple of 4B. */ struct mlx5_vdpa_task { struct mlx5_vdpa_priv *priv; + enum mlx5_vdpa_task_type type; uint32_t *remaining_cnt; uint32_t *err_cnt; uint32_t idx; @@ -101,6 +107,14 @@ struct mlx5_vdpa_conf_thread_mng { }; extern struct mlx5_vdpa_conf_thread_mng conf_thread_mng; +struct mlx5_vdpa_vmem_info { + struct rte_vhost_memory *vmem; + uint32_t entries_num; + uint64_t gcd; + uint64_t size; + uint8_t mode; +}; + struct mlx5_vdpa_virtq { SLIST_ENTRY(mlx5_vdpa_virtq) next; uint8_t enable; @@ -176,7 +190,7 @@ struct mlx5_vdpa_priv { struct mlx5_hca_vdpa_attr caps; uint32_t gpa_mkey_index; struct ibv_mr *null_mr; - struct rte_vhost_memory *vmem; + struct mlx5_vdpa_vmem_info vmem_info; struct mlx5dv_devx_event_channel *eventc; struct mlx5dv_devx_event_channel *err_chnl; struct mlx5_uar uar; @@ -187,11 +201,13 @@ struct mlx5_vdpa_priv { uint8_t num_lag_ports; uint64_t features; /* Negotiated features. */ uint16_t log_max_rqt_size; + uint16_t last_c_thrd_idx; + uint16_t num_mrs; /* Number of memory regions. */ struct mlx5_vdpa_steer steer; struct mlx5dv_var *var; void *virtq_db_addr; struct mlx5_pmd_wrapped_mr lm_mr; - SLIST_HEAD(mr_list, mlx5_vdpa_query_mr) mr_list; + struct mlx5_vdpa_query_mr **mrs; struct mlx5_vdpa_virtq virtqs[]; }; @@ -548,5 +564,12 @@ mlx5_vdpa_mult_threads_destroy(bool need_unlock); bool mlx5_vdpa_task_add(struct mlx5_vdpa_priv *priv, uint32_t thrd_idx, - uint32_t num); + enum mlx5_vdpa_task_type task_type, + uint32_t *bulk_refcnt, uint32_t *bulk_err_cnt, + void **task_data, uint32_t num); +int +mlx5_vdpa_register_mr(struct mlx5_vdpa_priv *priv, uint32_t idx); +bool +mlx5_vdpa_c_thread_wait_bulk_tasks_done(uint32_t *remaining_cnt, + uint32_t *err_cnt, uint32_t sleep_time); #endif /* RTE_PMD_MLX5_VDPA_H_ */ diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c index 1fdc92d3ad..10391931ae 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c @@ -47,16 +47,23 @@ mlx5_vdpa_c_thrd_ring_enqueue_bulk(struct rte_ring *r, bool mlx5_vdpa_task_add(struct mlx5_vdpa_priv *priv, uint32_t thrd_idx, - uint32_t num) + enum mlx5_vdpa_task_type task_type, + uint32_t *remaining_cnt, uint32_t *err_cnt, + void **task_data, uint32_t num) { struct rte_ring *rng = conf_thread_mng.cthrd[thrd_idx].rng; struct mlx5_vdpa_task task[MLX5_VDPA_TASKS_PER_DEV]; + uint32_t *data = (uint32_t *)task_data; uint32_t i; MLX5_ASSERT(num <= MLX5_VDPA_TASKS_PER_DEV); for (i = 0 ; i < num; i++) { task[i].priv = priv; /* To be added later. */ + task[i].type = task_type; + task[i].remaining_cnt = remaining_cnt; + task[i].err_cnt = err_cnt; + task[i].idx = data[i]; } if (!mlx5_vdpa_c_thrd_ring_enqueue_bulk(rng, (void **)&task, num, NULL)) return -1; @@ -71,6 +78,23 @@ mlx5_vdpa_task_add(struct mlx5_vdpa_priv *priv, return 0; } +bool +mlx5_vdpa_c_thread_wait_bulk_tasks_done(uint32_t *remaining_cnt, + uint32_t *err_cnt, uint32_t sleep_time) +{ + /* Check and wait all tasks done. */ + while (__atomic_load_n(remaining_cnt, + __ATOMIC_RELAXED) != 0) { + rte_delay_us_sleep(sleep_time); + } + if (__atomic_load_n(err_cnt, + __ATOMIC_RELAXED)) { + DRV_LOG(ERR, "Tasks done with error."); + return true; + } + return false; +} + static void * mlx5_vdpa_c_thread_handle(void *arg) { @@ -81,6 +105,7 @@ mlx5_vdpa_c_thread_handle(void *arg) struct rte_ring *rng; uint32_t thrd_idx; uint32_t task_num; + int ret; for (thrd_idx = 0; thrd_idx < multhrd->max_thrds; thrd_idx++) @@ -99,13 +124,29 @@ mlx5_vdpa_c_thread_handle(void *arg) &multhrd->cthrd[thrd_idx].c_cond, &multhrd->cthrd_lock); pthread_mutex_unlock(&multhrd->cthrd_lock); + continue; } priv = task.priv; if (priv == NULL) continue; - __atomic_fetch_sub(task.remaining_cnt, + switch (task.type) { + case MLX5_VDPA_TASK_REG_MR: + ret = mlx5_vdpa_register_mr(priv, task.idx); + if (ret) { + DRV_LOG(ERR, + "Failed to register mr %d.", task.idx); + __atomic_fetch_add(task.err_cnt, 1, + __ATOMIC_RELAXED); + } + break; + default: + DRV_LOG(ERR, "Invalid vdpa task type %d.", + task.type); + break; + } + if (task.remaining_cnt) + __atomic_fetch_sub(task.remaining_cnt, 1, __ATOMIC_RELAXED); - /* To be added later. */ } return NULL; } diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_mem.c b/drivers/vdpa/mlx5/mlx5_vdpa_mem.c index d6e3dd664b..e333f0bca6 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_mem.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_mem.c @@ -17,25 +17,33 @@ void mlx5_vdpa_mem_dereg(struct mlx5_vdpa_priv *priv) { + struct mlx5_vdpa_query_mr *mrs = + (struct mlx5_vdpa_query_mr *)priv->mrs; struct mlx5_vdpa_query_mr *entry; - struct mlx5_vdpa_query_mr *next; + int i; - entry = SLIST_FIRST(&priv->mr_list); - while (entry) { - next = SLIST_NEXT(entry, next); - if (entry->is_indirect) - claim_zero(mlx5_devx_cmd_destroy(entry->mkey)); - else - claim_zero(mlx5_glue->dereg_mr(entry->mr)); - SLIST_REMOVE(&priv->mr_list, entry, mlx5_vdpa_query_mr, next); - rte_free(entry); - entry = next; + if (priv->mrs) { + for (i = priv->num_mrs - 1; i >= 0; i--) { + entry = &mrs[i]; + if (entry->is_indirect) { + if (entry->mkey) + claim_zero( + mlx5_devx_cmd_destroy(entry->mkey)); + } else { + if (entry->mr) + claim_zero( + mlx5_glue->dereg_mr(entry->mr)); + } + } + rte_free(priv->mrs); + priv->mrs = NULL; + priv->num_mrs = 0; } - SLIST_INIT(&priv->mr_list); - if (priv->vmem) { - free(priv->vmem); - priv->vmem = NULL; + if (priv->vmem_info.vmem) { + free(priv->vmem_info.vmem); + priv->vmem_info.vmem = NULL; } + priv->gpa_mkey_index = 0; } static int @@ -167,72 +175,29 @@ mlx5_vdpa_mem_cmp(struct rte_vhost_memory *mem1, struct rte_vhost_memory *mem2) #define KLM_SIZE_MAX_ALIGN(sz) ((sz) > MLX5_MAX_KLM_BYTE_COUNT ? \ MLX5_MAX_KLM_BYTE_COUNT : (sz)) -/* - * The target here is to group all the physical memory regions of the - * virtio device in one indirect mkey. - * For KLM Fixed Buffer Size mode (HW find the translation entry in one - * read according to the guest physical address): - * All the sub-direct mkeys of it must be in the same size, hence, each - * one of them should be in the GCD size of all the virtio memory - * regions and the holes between them. - * For KLM mode (each entry may be in different size so HW must iterate - * the entries): - * Each virtio memory region and each hole between them have one entry, - * just need to cover the maximum allowed size(2G) by splitting entries - * which their associated memory regions are bigger than 2G. - * It means that each virtio memory region may be mapped to more than - * one direct mkey in the 2 modes. - * All the holes of invalid memory between the virtio memory regions - * will be mapped to the null memory region for security. - */ -int -mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv) +static int +mlx5_vdpa_create_indirect_mkey(struct mlx5_vdpa_priv *priv) { struct mlx5_devx_mkey_attr mkey_attr; - struct mlx5_vdpa_query_mr *entry = NULL; - struct rte_vhost_mem_region *reg = NULL; - uint8_t mode = 0; - uint32_t entries_num = 0; - uint32_t i; - uint64_t gcd = 0; + struct mlx5_vdpa_query_mr *mrs = + (struct mlx5_vdpa_query_mr *)priv->mrs; + struct mlx5_vdpa_query_mr *entry; + struct rte_vhost_mem_region *reg; + uint8_t mode = priv->vmem_info.mode; + uint32_t entries_num = priv->vmem_info.entries_num; + struct rte_vhost_memory *mem = priv->vmem_info.vmem; + struct mlx5_klm klm_array[entries_num]; + uint64_t gcd = priv->vmem_info.gcd; + int ret = -rte_errno; uint64_t klm_size; - uint64_t mem_size; - uint64_t k; int klm_index = 0; - int ret; - struct rte_vhost_memory *mem = mlx5_vdpa_vhost_mem_regions_prepare - (priv->vid, &mode, &mem_size, &gcd, &entries_num); - struct mlx5_klm klm_array[entries_num]; + uint64_t k; + uint32_t i; - if (!mem) - return -rte_errno; - if (priv->vmem != NULL) { - if (mlx5_vdpa_mem_cmp(mem, priv->vmem) == 0) { - /* VM memory not changed, reuse resources. */ - free(mem); - return 0; - } - mlx5_vdpa_mem_dereg(priv); - } - priv->vmem = mem; + /* If it is the last entry, create indirect mkey. */ for (i = 0; i < mem->nregions; i++) { + entry = &mrs[i]; reg = &mem->regions[i]; - entry = rte_zmalloc(__func__, sizeof(*entry), 0); - if (!entry) { - ret = -ENOMEM; - DRV_LOG(ERR, "Failed to allocate mem entry memory."); - goto error; - } - entry->mr = mlx5_glue->reg_mr_iova(priv->cdev->pd, - (void *)(uintptr_t)(reg->host_user_addr), - reg->size, reg->guest_phys_addr, - IBV_ACCESS_LOCAL_WRITE); - if (!entry->mr) { - DRV_LOG(ERR, "Failed to create direct Mkey."); - ret = -rte_errno; - goto error; - } - entry->is_indirect = 0; if (i > 0) { uint64_t sadd; uint64_t empty_region_sz = reg->guest_phys_addr - @@ -265,11 +230,10 @@ mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv) klm_array[klm_index].address = reg->guest_phys_addr + k; klm_index++; } - SLIST_INSERT_HEAD(&priv->mr_list, entry, next); } memset(&mkey_attr, 0, sizeof(mkey_attr)); mkey_attr.addr = (uintptr_t)(mem->regions[0].guest_phys_addr); - mkey_attr.size = mem_size; + mkey_attr.size = priv->vmem_info.size; mkey_attr.pd = priv->cdev->pdn; mkey_attr.umem_id = 0; /* Must be zero for KLM mode. */ @@ -278,25 +242,159 @@ mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv) mkey_attr.pg_access = 0; mkey_attr.klm_array = klm_array; mkey_attr.klm_num = klm_index; - entry = rte_zmalloc(__func__, sizeof(*entry), 0); - if (!entry) { - DRV_LOG(ERR, "Failed to allocate memory for indirect entry."); - ret = -ENOMEM; - goto error; - } + entry = &mrs[mem->nregions]; entry->mkey = mlx5_devx_cmd_mkey_create(priv->cdev->ctx, &mkey_attr); if (!entry->mkey) { DRV_LOG(ERR, "Failed to create indirect Mkey."); - ret = -rte_errno; - goto error; + rte_errno = -ret; + return ret; } entry->is_indirect = 1; - SLIST_INSERT_HEAD(&priv->mr_list, entry, next); priv->gpa_mkey_index = entry->mkey->id; return 0; +} + +/* + * The target here is to group all the physical memory regions of the + * virtio device in one indirect mkey. + * For KLM Fixed Buffer Size mode (HW find the translation entry in one + * read according to the guest phisical address): + * All the sub-direct mkeys of it must be in the same size, hence, each + * one of them should be in the GCD size of all the virtio memory + * regions and the holes between them. + * For KLM mode (each entry may be in different size so HW must iterate + * the entries): + * Each virtio memory region and each hole between them have one entry, + * just need to cover the maximum allowed size(2G) by splitting entries + * which their associated memory regions are bigger than 2G. + * It means that each virtio memory region may be mapped to more than + * one direct mkey in the 2 modes. + * All the holes of invalid memory between the virtio memory regions + * will be mapped to the null memory region for security. + */ +int +mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv) +{ + void *mrs; + uint8_t mode = 0; + int ret = -rte_errno; + uint32_t i, thrd_idx, data[1]; + uint32_t remaining_cnt = 0, err_cnt = 0, task_num = 0; + struct rte_vhost_memory *mem = mlx5_vdpa_vhost_mem_regions_prepare + (priv->vid, &mode, &priv->vmem_info.size, + &priv->vmem_info.gcd, &priv->vmem_info.entries_num); + + if (!mem) + return -rte_errno; + if (priv->vmem_info.vmem != NULL) { + if (mlx5_vdpa_mem_cmp(mem, priv->vmem_info.vmem) == 0) { + /* VM memory not changed, reuse resources. */ + free(mem); + return 0; + } + mlx5_vdpa_mem_dereg(priv); + } + priv->vmem_info.vmem = mem; + priv->vmem_info.mode = mode; + priv->num_mrs = mem->nregions; + if (!priv->num_mrs || priv->num_mrs >= MLX5_VDPA_MAX_MRS) { + DRV_LOG(ERR, + "Invalid number of memory regions."); + goto error; + } + /* The last one is indirect mkey entry. */ + priv->num_mrs++; + mrs = rte_zmalloc("mlx5 vDPA memory regions", + sizeof(struct mlx5_vdpa_query_mr) * priv->num_mrs, 0); + priv->mrs = mrs; + if (!priv->mrs) { + DRV_LOG(ERR, "Failed to allocate private memory regions."); + goto error; + } + if (priv->use_c_thread) { + uint32_t main_task_idx[mem->nregions]; + + for (i = 0; i < mem->nregions; i++) { + thrd_idx = i % (conf_thread_mng.max_thrds + 1); + if (!thrd_idx) { + main_task_idx[task_num] = i; + task_num++; + continue; + } + thrd_idx = priv->last_c_thrd_idx + 1; + if (thrd_idx >= conf_thread_mng.max_thrds) + thrd_idx = 0; + priv->last_c_thrd_idx = thrd_idx; + data[0] = i; + if (mlx5_vdpa_task_add(priv, thrd_idx, + MLX5_VDPA_TASK_REG_MR, + &remaining_cnt, &err_cnt, + (void **)&data, 1)) { + DRV_LOG(ERR, + "Fail to add task mem region (%d)", i); + main_task_idx[task_num] = i; + task_num++; + } + } + for (i = 0; i < task_num; i++) { + ret = mlx5_vdpa_register_mr(priv, + main_task_idx[i]); + if (ret) { + DRV_LOG(ERR, + "Failed to register mem region %d.", i); + goto error; + } + } + if (mlx5_vdpa_c_thread_wait_bulk_tasks_done(&remaining_cnt, + &err_cnt, 100)) { + DRV_LOG(ERR, + "Failed to wait register mem region tasks ready."); + goto error; + } + } else { + for (i = 0; i < mem->nregions; i++) { + ret = mlx5_vdpa_register_mr(priv, i); + if (ret) { + DRV_LOG(ERR, + "Failed to register mem region %d.", i); + goto error; + } + } + } + ret = mlx5_vdpa_create_indirect_mkey(priv); + if (ret) { + DRV_LOG(ERR, "Failed to create indirect mkey ."); + goto error; + } + return 0; error: - rte_free(entry); mlx5_vdpa_mem_dereg(priv); rte_errno = -ret; return ret; } + +int +mlx5_vdpa_register_mr(struct mlx5_vdpa_priv *priv, uint32_t idx) +{ + struct rte_vhost_memory *mem = priv->vmem_info.vmem; + struct mlx5_vdpa_query_mr *mrs = + (struct mlx5_vdpa_query_mr *)priv->mrs; + struct mlx5_vdpa_query_mr *entry; + struct rte_vhost_mem_region *reg; + int ret; + + reg = &mem->regions[idx]; + entry = &mrs[idx]; + entry->mr = mlx5_glue->reg_mr_iova + (priv->cdev->pd, + (void *)(uintptr_t)(reg->host_user_addr), + reg->size, reg->guest_phys_addr, + IBV_ACCESS_LOCAL_WRITE); + if (!entry->mr) { + DRV_LOG(ERR, "Failed to create direct Mkey."); + ret = -rte_errno; + return ret; + } + entry->is_indirect = 0; + return 0; +} diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c index 599809b09b..0b317655db 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c @@ -353,21 +353,21 @@ mlx5_vdpa_virtq_sub_objs_prepare(struct mlx5_vdpa_priv *priv, } } if (attr->q_type == MLX5_VIRTQ_TYPE_SPLIT) { - gpa = mlx5_vdpa_hva_to_gpa(priv->vmem, + gpa = mlx5_vdpa_hva_to_gpa(priv->vmem_info.vmem, (uint64_t)(uintptr_t)vq->desc); if (!gpa) { DRV_LOG(ERR, "Failed to get descriptor ring GPA."); return -1; } attr->desc_addr = gpa; - gpa = mlx5_vdpa_hva_to_gpa(priv->vmem, + gpa = mlx5_vdpa_hva_to_gpa(priv->vmem_info.vmem, (uint64_t)(uintptr_t)vq->used); if (!gpa) { DRV_LOG(ERR, "Failed to get GPA for used ring."); return -1; } attr->used_addr = gpa; - gpa = mlx5_vdpa_hva_to_gpa(priv->vmem, + gpa = mlx5_vdpa_hva_to_gpa(priv->vmem_info.vmem, (uint64_t)(uintptr_t)vq->avail); if (!gpa) { DRV_LOG(ERR, "Failed to get GPA for available ring."); From patchwork Mon Jun 6 11:21:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112364 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 766F2A0543; Mon, 6 Jun 2022 13:24:33 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AD02B41611; Mon, 6 Jun 2022 13:22:48 +0200 (CEST) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2041.outbound.protection.outlook.com [40.107.93.41]) by mails.dpdk.org (Postfix) with ESMTP id C62C141156 for ; Mon, 6 Jun 2022 13:22:47 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=eQNY53XSSCSgHQ7MgAniGLmyXDzyHhHuMcz2GGg63E/iIp9jawBb6c0WbGZrah8Q8COrX/T4BKZsxQLFUYWAr+uIoW9O5ejucCOWP4CSlXbigr785pZEXsGlP8jSNUIlLkHrl3OTDHzfoWZevIwYlSV4557c7YI7ODheWXgKiM59vSnGqgAQ9iynkGxF2jtPF1+uOoqCOieMs17E7DnRySqKW05fJ4qx3fboyVa5GGSEx4IF4f6+osbq+19xNuIh29BKCZrwfRLZ75x5s/65VeMNeB2YIBwxB39pY7fVxstLRbnoJODON2BDdyLncQR7ZaM3w80YFE5SqB1xfIRe9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=D0Zy9/Tg4z8XhCWAE1gPUw8MnOBjkfQd3cdsZE+Y7cw=; b=KX2CMefSHOYC8dTwoc37dgyJRQ/OdppeY66Kp50sLEm0V+xZux3WzQmaVb0xRONQUJNn7aHb/q8c4D6qtOnfbAD23ZMnvOPh/s7jfri2L/ZFlDSPVByfVf1nYHxwv54lrbDhkpjwBP2zi7Ya+b2jmpPdukE5HUK3UidN6SD346ci1r0N3VqGyP7C3PksbTIpSLTSIzyjEYS7toIIa6QTCrFJ1WsfctB4W2AlD1MeWSm09WJqoQhprLVpH6QDhXegq0xzr5+QQaI8IKqLUPVCVtvcmRY1yEW9Fs/xNtcuoJaqb3CNoTl5+ypHhI/fE4RtiYWrZdgh1/Wj1SnpDk1ieg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=D0Zy9/Tg4z8XhCWAE1gPUw8MnOBjkfQd3cdsZE+Y7cw=; b=F8rxw4AGe1WHd384hPw90oI3/HjnpVGW1jHk4qZD3VTvWcf3wvE1GKIymp+ywuycTJk33fqzQ6I/uKhFBqZeisWZWobesmZ44venq6gJw7HRxNk+OaT7BujMyDHjhsE9eP278q+cTB5O66/HpZxcUuk/5mRkGxu6c9hOgtTSHAum2kOJ6fUZWorBp5P2vlhzrd1j4AkpNTTQu0rsjHNEHqDl5omG0bMtCFfb+z1KCD222L6L7Ml57l22alZPHRnMg4i1OKdVRsatBR7byza5DMFcbqKd22GsblrF5ZDqt8fWORRhEHdkSs6f0wAD+JqfX3NgbI+OXQLksH+XLG4wwQ== Received: from BN9PR03CA0557.namprd03.prod.outlook.com (2603:10b6:408:138::22) by DM4PR12MB5748.namprd12.prod.outlook.com (2603:10b6:8:5f::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.19; Mon, 6 Jun 2022 11:22:44 +0000 Received: from BN8NAM11FT047.eop-nam11.prod.protection.outlook.com (2603:10b6:408:138:cafe::f6) by BN9PR03CA0557.outlook.office365.com (2603:10b6:408:138::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.16 via Frontend Transport; Mon, 6 Jun 2022 11:22:44 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by BN8NAM11FT047.mail.protection.outlook.com (10.13.177.220) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:44 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:22:43 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:22:40 -0700 From: Li Zhang To: , , , CC: , , , Subject: [PATCH 12/16] vdpa/mlx5: add virtq creation task for MT management Date: Mon, 6 Jun 2022 14:21:00 +0300 Message-ID: <20220606112109.208873-24-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2cc7e53a-c07d-405b-e2ce-08da47aee0bb X-MS-TrafficTypeDiagnostic: DM4PR12MB5748:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hNp96nbou6JgWPOk5vsqdIoKQ9rtl31rgNjukhPY/cvXiS61HZC+lM7LyiaCiGQzruua4nXMsx97a+l+FbYYMKJ/QKP2ykSReqw8vhEjN6/MX8PlLHVoM27x4Ua0Llhopdl5sF3qHoxQmRI+O567e5NAUODY3Fsq91d4VZc8V9S0m4G93XEIdOsEdzXqvnD2XDc0hhEZCqpCrAUMO6GxtVFNnO78zDOan3svGdDL21wd6lvW9V2V8IX1UQNub25zVVtby/337JFFFgMjY1ewh8DG7HtLcOWZvQzG368vqwaZvIsoEWg12Kv3HqPdDh9XwrDd2JdJ9t13ShmmqdUN7fUjyIiZjvckgqnPGkYNZNvmPo5vjci8acrfNqCcB2LUwsh61wVp/LDd9txAzAZYt9RpQxR4/J+ydWdMnHUEAsob8DFS9zX7cgRH2tV5NP67mIPSRBgPS4oCzX0pFCUQFNqHGUQkoTSFeAgu5fVlyzqNdv4fu2Ym870h5ehl1Xe3gA0FeLcP3HOAvl4Iyqfc3Wz+L6ByjqVJS4NrjAxrH40n75UadmxFqPTdUaurNVuhmUWhZg0121O1GMp6Pyq9ojDkHJIikg0EfWTJBDHGurJ3E/U3VFIA7NQXpbwOI2RKYV7AMXdH6bTxLQc9PqpqkiBD7LQukR3gMSdeoh5pILvkP+DrFScggJOm7sRf0ijF54A2WDZaMXVKi5B+HaWRdw== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(426003)(6286002)(1076003)(36860700001)(8936002)(107886003)(6636002)(16526019)(186003)(2906002)(508600001)(47076005)(83380400001)(54906003)(40460700003)(336012)(2616005)(70586007)(70206006)(55016003)(36756003)(6666004)(81166007)(356005)(4326008)(8676002)(7696005)(30864003)(26005)(86362001)(5660300002)(82310400005)(110136005)(316002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:22:44.4137 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2cc7e53a-c07d-405b-e2ce-08da47aee0bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5748 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The virtq object and all its sub-resources use a lot of FW commands and can be accelerated by the MT management. Split the virtqs creation between the configuration threads. This accelerates the LM process and reduces its time by 20%. Signed-off-by: Li Zhang --- drivers/vdpa/mlx5/mlx5_vdpa.h | 9 +- drivers/vdpa/mlx5/mlx5_vdpa_cthread.c | 14 +++ drivers/vdpa/mlx5/mlx5_vdpa_event.c | 2 +- drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 149 +++++++++++++++++++------- 4 files changed, 134 insertions(+), 40 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index 3316ce42be..35221f5ddc 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -80,6 +80,7 @@ enum { /* Vdpa task types. */ enum mlx5_vdpa_task_type { MLX5_VDPA_TASK_REG_MR = 1, + MLX5_VDPA_TASK_SETUP_VIRTQ, }; /* Generic task information and size must be multiple of 4B. */ @@ -117,12 +118,12 @@ struct mlx5_vdpa_vmem_info { struct mlx5_vdpa_virtq { SLIST_ENTRY(mlx5_vdpa_virtq) next; - uint8_t enable; uint16_t index; uint16_t vq_size; uint8_t notifier_state; - bool stopped; uint32_t configured:1; + uint32_t enable:1; + uint32_t stopped:1; uint32_t version; pthread_mutex_t virtq_lock; struct mlx5_vdpa_priv *priv; @@ -565,11 +566,13 @@ bool mlx5_vdpa_task_add(struct mlx5_vdpa_priv *priv, uint32_t thrd_idx, enum mlx5_vdpa_task_type task_type, - uint32_t *bulk_refcnt, uint32_t *bulk_err_cnt, + uint32_t *remaining_cnt, uint32_t *err_cnt, void **task_data, uint32_t num); int mlx5_vdpa_register_mr(struct mlx5_vdpa_priv *priv, uint32_t idx); bool mlx5_vdpa_c_thread_wait_bulk_tasks_done(uint32_t *remaining_cnt, uint32_t *err_cnt, uint32_t sleep_time); +int +mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index, bool reg_kick); #endif /* RTE_PMD_MLX5_VDPA_H_ */ diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c index 10391931ae..1389d369ae 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c @@ -100,6 +100,7 @@ mlx5_vdpa_c_thread_handle(void *arg) { struct mlx5_vdpa_conf_thread_mng *multhrd = arg; pthread_t thread_id = pthread_self(); + struct mlx5_vdpa_virtq *virtq; struct mlx5_vdpa_priv *priv; struct mlx5_vdpa_task task; struct rte_ring *rng; @@ -139,6 +140,19 @@ mlx5_vdpa_c_thread_handle(void *arg) __ATOMIC_RELAXED); } break; + case MLX5_VDPA_TASK_SETUP_VIRTQ: + virtq = &priv->virtqs[task.idx]; + pthread_mutex_lock(&virtq->virtq_lock); + ret = mlx5_vdpa_virtq_setup(priv, + task.idx, false); + if (ret) { + DRV_LOG(ERR, + "Failed to setup virtq %d.", task.idx); + __atomic_fetch_add( + task.err_cnt, 1, __ATOMIC_RELAXED); + } + pthread_mutex_unlock(&virtq->virtq_lock); + break; default: DRV_LOG(ERR, "Invalid vdpa task type %d.", task.type); diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c index b45fbac146..f782b6b832 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c @@ -371,7 +371,7 @@ mlx5_vdpa_err_interrupt_handler(void *cb_arg __rte_unused) goto unlock; if (rte_rdtsc() / rte_get_tsc_hz() < MLX5_VDPA_ERROR_TIME_SEC) goto unlock; - virtq->stopped = true; + virtq->stopped = 1; /* Query error info. */ if (mlx5_vdpa_virtq_query(priv, vq_index)) goto log; diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c index 0b317655db..db05220e76 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c @@ -111,8 +111,9 @@ mlx5_vdpa_virtqs_cleanup(struct mlx5_vdpa_priv *priv) for (i = 0; i < priv->caps.max_num_virtio_queues; i++) { struct mlx5_vdpa_virtq *virtq = &priv->virtqs[i]; + if (virtq->index != i) + continue; pthread_mutex_lock(&virtq->virtq_lock); - virtq->configured = 0; for (j = 0; j < RTE_DIM(virtq->umems); ++j) { if (virtq->umems[j].obj) { claim_zero(mlx5_glue->devx_umem_dereg @@ -131,7 +132,6 @@ mlx5_vdpa_virtqs_cleanup(struct mlx5_vdpa_priv *priv) } } - static int mlx5_vdpa_virtq_unset(struct mlx5_vdpa_virtq *virtq) { @@ -191,7 +191,7 @@ mlx5_vdpa_virtq_stop(struct mlx5_vdpa_priv *priv, int index) ret = mlx5_vdpa_virtq_modify(virtq, 0); if (ret) return -1; - virtq->stopped = true; + virtq->stopped = 1; DRV_LOG(DEBUG, "vid %u virtq %u was stopped.", priv->vid, index); return mlx5_vdpa_virtq_query(priv, index); } @@ -411,7 +411,38 @@ mlx5_vdpa_is_modify_virtq_supported(struct mlx5_vdpa_priv *priv) } static int -mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index) +mlx5_vdpa_virtq_doorbell_setup(struct mlx5_vdpa_virtq *virtq, + struct rte_vhost_vring *vq, int index) +{ + virtq->intr_handle = + rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); + if (virtq->intr_handle == NULL) { + DRV_LOG(ERR, "Fail to allocate intr_handle"); + return -1; + } + if (rte_intr_fd_set(virtq->intr_handle, vq->kickfd)) + return -1; + if (rte_intr_fd_get(virtq->intr_handle) == -1) { + DRV_LOG(WARNING, "Virtq %d kickfd is invalid.", index); + } else { + if (rte_intr_type_set(virtq->intr_handle, + RTE_INTR_HANDLE_EXT)) + return -1; + if (rte_intr_callback_register(virtq->intr_handle, + mlx5_vdpa_virtq_kick_handler, virtq)) { + (void)rte_intr_fd_set(virtq->intr_handle, -1); + DRV_LOG(ERR, "Failed to register virtq %d interrupt.", + index); + return -1; + } + DRV_LOG(DEBUG, "Register fd %d interrupt for virtq %d.", + rte_intr_fd_get(virtq->intr_handle), index); + } + return 0; +} + +int +mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index, bool reg_kick) { struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index]; struct rte_vhost_vring vq; @@ -455,33 +486,11 @@ mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index) rte_write32(virtq->index, priv->virtq_db_addr); rte_spinlock_unlock(&priv->db_lock); /* Setup doorbell mapping. */ - virtq->intr_handle = - rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); - if (virtq->intr_handle == NULL) { - DRV_LOG(ERR, "Fail to allocate intr_handle"); - goto error; - } - - if (rte_intr_fd_set(virtq->intr_handle, vq.kickfd)) - goto error; - - if (rte_intr_fd_get(virtq->intr_handle) == -1) { - DRV_LOG(WARNING, "Virtq %d kickfd is invalid.", index); - } else { - if (rte_intr_type_set(virtq->intr_handle, RTE_INTR_HANDLE_EXT)) - goto error; - - if (rte_intr_callback_register(virtq->intr_handle, - mlx5_vdpa_virtq_kick_handler, - virtq)) { - (void)rte_intr_fd_set(virtq->intr_handle, -1); + if (reg_kick) { + if (mlx5_vdpa_virtq_doorbell_setup(virtq, &vq, index)) { DRV_LOG(ERR, "Failed to register virtq %d interrupt.", index); goto error; - } else { - DRV_LOG(DEBUG, "Register fd %d interrupt for virtq %d.", - rte_intr_fd_get(virtq->intr_handle), - index); } } /* Subscribe virtq error event. */ @@ -497,7 +506,6 @@ mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index) rte_errno = errno; goto error; } - virtq->stopped = false; /* Initial notification to ask Qemu handling completed buffers. */ if (virtq->eqp.cq.callfd != -1) eventfd_write(virtq->eqp.cq.callfd, (eventfd_t)1); @@ -567,10 +575,12 @@ mlx5_vdpa_features_validate(struct mlx5_vdpa_priv *priv) int mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv) { - uint32_t i; - uint16_t nr_vring = rte_vhost_get_vring_num(priv->vid); int ret = rte_vhost_get_negotiated_features(priv->vid, &priv->features); + uint16_t nr_vring = rte_vhost_get_vring_num(priv->vid); + uint32_t remaining_cnt = 0, err_cnt = 0, task_num = 0; + uint32_t i, thrd_idx, data[1]; struct mlx5_vdpa_virtq *virtq; + struct rte_vhost_vring vq; if (ret || mlx5_vdpa_features_validate(priv)) { DRV_LOG(ERR, "Failed to configure negotiated features."); @@ -590,16 +600,83 @@ mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv) return -1; } priv->nr_virtqs = nr_vring; - for (i = 0; i < nr_vring; i++) { - virtq = &priv->virtqs[i]; - if (virtq->enable) { + if (priv->use_c_thread) { + uint32_t main_task_idx[nr_vring]; + + for (i = 0; i < nr_vring; i++) { + virtq = &priv->virtqs[i]; + if (!virtq->enable) + continue; + thrd_idx = i % (conf_thread_mng.max_thrds + 1); + if (!thrd_idx) { + main_task_idx[task_num] = i; + task_num++; + continue; + } + thrd_idx = priv->last_c_thrd_idx + 1; + if (thrd_idx >= conf_thread_mng.max_thrds) + thrd_idx = 0; + priv->last_c_thrd_idx = thrd_idx; + data[0] = i; + if (mlx5_vdpa_task_add(priv, thrd_idx, + MLX5_VDPA_TASK_SETUP_VIRTQ, + &remaining_cnt, &err_cnt, + (void **)&data, 1)) { + DRV_LOG(ERR, "Fail to add " + "task setup virtq (%d).", i); + main_task_idx[task_num] = i; + task_num++; + } + } + for (i = 0; i < task_num; i++) { + virtq = &priv->virtqs[main_task_idx[i]]; pthread_mutex_lock(&virtq->virtq_lock); - if (mlx5_vdpa_virtq_setup(priv, i)) { + if (mlx5_vdpa_virtq_setup(priv, + main_task_idx[i], false)) { pthread_mutex_unlock(&virtq->virtq_lock); goto error; } pthread_mutex_unlock(&virtq->virtq_lock); } + if (mlx5_vdpa_c_thread_wait_bulk_tasks_done(&remaining_cnt, + &err_cnt, 2000)) { + DRV_LOG(ERR, + "Failed to wait virt-queue setup tasks ready."); + goto error; + } + for (i = 0; i < nr_vring; i++) { + /* Setup doorbell mapping in order for Qume. */ + virtq = &priv->virtqs[i]; + pthread_mutex_lock(&virtq->virtq_lock); + if (!virtq->enable || !virtq->configured) { + pthread_mutex_unlock(&virtq->virtq_lock); + continue; + } + if (rte_vhost_get_vhost_vring(priv->vid, i, &vq)) { + pthread_mutex_unlock(&virtq->virtq_lock); + goto error; + } + if (mlx5_vdpa_virtq_doorbell_setup(virtq, &vq, i)) { + pthread_mutex_unlock(&virtq->virtq_lock); + DRV_LOG(ERR, + "Failed to register virtq %d interrupt.", i); + goto error; + } + pthread_mutex_unlock(&virtq->virtq_lock); + } + } else { + for (i = 0; i < nr_vring; i++) { + virtq = &priv->virtqs[i]; + pthread_mutex_lock(&virtq->virtq_lock); + if (virtq->enable) { + if (mlx5_vdpa_virtq_setup(priv, i, true)) { + pthread_mutex_unlock( + &virtq->virtq_lock); + goto error; + } + } + pthread_mutex_unlock(&virtq->virtq_lock); + } } return 0; error: @@ -663,7 +740,7 @@ mlx5_vdpa_virtq_enable(struct mlx5_vdpa_priv *priv, int index, int enable) mlx5_vdpa_virtq_unset(virtq); } if (enable) { - ret = mlx5_vdpa_virtq_setup(priv, index); + ret = mlx5_vdpa_virtq_setup(priv, index, true); if (ret) { DRV_LOG(ERR, "Failed to setup virtq %d.", index); return ret; From patchwork Mon Jun 6 11:21:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112365 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C1B9EA0543; Mon, 6 Jun 2022 13:24:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9DDC842BD1; Mon, 6 Jun 2022 13:22:50 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2073.outbound.protection.outlook.com [40.107.244.73]) by mails.dpdk.org (Postfix) with ESMTP id EED6642B84 for ; Mon, 6 Jun 2022 13:22:48 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iP9jdXKEtBAnCekt2W64nfkvKtjdloKV+aZ9LVn+owVLXXPHvgh6oZJW5LGpXhuk9mJDXsa2ddHa7AOSJKQrYrb47fGMof/0DGjWqqcE3dBxQosmvKhYjz0yK16HaOAMPLyeVWyb4V6Akg0Ktf+HKHEmrsTYLnG+0Hq53HOZDyW1R5nxx/n0zQIE56apdcZikYYMJt84R2X2XuN+5Qnv8km8WM5TqjvaXrjI2dr8XYsXSHZlsgh4YtJ05OdbuWoA6wxjZGrsNVdR1wtTE4T4+HMKoKV5x/7ih4vEAE1zlZpS75iXhO2NqdvXp0aKZb/LMXn7exYM3owrW+gyl+EbjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TFlSU0NM+Vl7ACH+AnzFBZIOnfKwLgjvtRy8gMC45iw=; b=WSyhnJzg1vsGyorUzQjx5dAfyLhqi5Kv5jUY8ZivY33Z+aolB2H2tIG5j96pM22bluqosPzyTuBmiWlDH0Rn0Yc1eNGXYpbjJTNx27d4uJiK/UgbiTuseu58KSMAeBG2+5hdcSr7s5maVew6iYVLC/RvA7xsLrWhtIpqz/+mHsSafkbGU45Ja7dp8SvzM5HujSXFWBNo8dzOU3XvCq+gzxjm9pv4VbV/YhxVhPoU/Lle0XBEPNpt0TDKPTDnZT5VeRiSS9DTWRRgVHZem2pHO9dB/O9+zfoQ1+K1X0zguFUw5HO5Xk4AkVqTvgYe8Qe1qX0YGfCel+4JtkScnFWZTg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.238) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TFlSU0NM+Vl7ACH+AnzFBZIOnfKwLgjvtRy8gMC45iw=; b=JTV8pimO9IBmsnSG7/rKE29hth8F8ycvYr5F0j3OcTi2gPFR8uW54ampUv/XkJnqMkW1qZBP+HzWH4do3ETJ5QbI2xQvZkQWMdyRotL2niJsP5eGhW8xyE3FShxVdeULqQVzd6hm0kIPM4FhkMtC/bqpCZg3qy3kxNslm2wDwwuOKmrqI6EK3F7X7+2KEg/f32U1EjtfR2ZrwTMgpzIN/vqZZiFui5MimsDnc22D/94hdFp7ss2cHDgBBAvUNDsbW65YqEK0mOAbeHZEXVrLXzxgyiYsG3s4w9+giNmH+sWe6zDyPUOqOt9FiICmzVCQ4BebWFYrLlZJeZ0s3j6IWA== Received: from DM3PR03CA0017.namprd03.prod.outlook.com (2603:10b6:0:50::27) by CH2PR12MB5564.namprd12.prod.outlook.com (2603:10b6:610:65::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13; Mon, 6 Jun 2022 11:22:47 +0000 Received: from DM6NAM11FT060.eop-nam11.prod.protection.outlook.com (2603:10b6:0:50:cafe::6e) by DM3PR03CA0017.outlook.office365.com (2603:10b6:0:50::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.238) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.238) by DM6NAM11FT060.mail.protection.outlook.com (10.13.173.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:47 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:22:46 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:22:43 -0700 From: Li Zhang To: , , , CC: , , , Subject: [PATCH 13/16] vdpa/mlx5: add virtq LM log task Date: Mon, 6 Jun 2022 14:21:01 +0300 Message-ID: <20220606112109.208873-25-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bd5507fa-eba6-4da0-2707-08da47aee25f X-MS-TrafficTypeDiagnostic: CH2PR12MB5564:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: X3C04lkMQ3Vq2KnSX/hL7x5nfepTLM+sdYHMRtKZwQvFOKprU4dGZ9svQWa/2SpQZkW7jT4PoitWAFC0jlkSApd+5PQe029IRNO4vOfuszm+jL7fXVHrAKd177ftxvj/kPQxrW4Zb/Ko1raq/DzWroLg73irU/mBxy3VSWf/OsWZU+CsC5Gfag42nJY2PTRcGNgVHTR4uxUC4qghPaN4HTVUU/nuf0pAFKCDdpble+ItrtJZP3KTxOE5Vg42LnnhIOxvk0b2Iv+WOjyojXgbq1XFm9FRArTIPaXwze1YVhUfQ4wS6m/auOjmeP57tcNdOvobz3DMMTxEYZv4RCoT5VHJnHHtG1LHPZdrlMvT0P/t1w91x2AOitt8/5ffGCngJsx6uStOKXA2+JF4iYNj35H0rSi6ffLZcT/KEl1+pX49TN89uI3Ms8VZeY8oi44KjnBu4m4fS8H2AzZONDnyIljRCK51R3gOJKGQ6VxK1nHKsUZheau4SYNQBG4ZgdKofbVBRH+lb1+SZMeoZw1Ze5M7OmX9swet+cE38obSWi4QVrlmMKz0R1kZxi0hUTS70cz7aWFOA6n/7gUUj6wP1XoF65c3GqmhanTVKXWetqVdobe/XErH634t/r8Io4c3AzUVoHohvzRVdjiFYKMMU1XknXeIpahAHPSgLeaG+u35kMyeyIRhbLtiNCHfG/8qc8ReKWmn19SU1zKn0TV7rw== X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(40460700003)(336012)(82310400005)(70586007)(70206006)(16526019)(8936002)(186003)(5660300002)(508600001)(110136005)(4326008)(2616005)(8676002)(1076003)(107886003)(7696005)(54906003)(47076005)(426003)(81166007)(26005)(55016003)(356005)(2906002)(6636002)(6666004)(316002)(36756003)(36860700001)(83380400001)(86362001)(6286002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:22:47.2708 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd5507fa-eba6-4da0-2707-08da47aee25f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB5564 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Split the virtqs LM log between the configuration threads. This accelerates the LM process and reduces its time by 20%. Signed-off-by: Li Zhang --- drivers/vdpa/mlx5/mlx5_vdpa.h | 3 + drivers/vdpa/mlx5/mlx5_vdpa_cthread.c | 34 +++++++++++ drivers/vdpa/mlx5/mlx5_vdpa_lm.c | 85 +++++++++++++++++++++------ 3 files changed, 105 insertions(+), 17 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index 35221f5ddc..e08931719f 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -72,6 +72,8 @@ enum { MLX5_VDPA_NOTIFIER_STATE_ERR }; +#define MLX5_VDPA_USED_RING_LEN(size) \ + ((size) * sizeof(struct vring_used_elem) + sizeof(uint16_t) * 3) #define MLX5_VDPA_MAX_C_THRD 256 #define MLX5_VDPA_MAX_TASKS_PER_THRD 4096 #define MLX5_VDPA_TASKS_PER_DEV 64 @@ -81,6 +83,7 @@ enum { enum mlx5_vdpa_task_type { MLX5_VDPA_TASK_REG_MR = 1, MLX5_VDPA_TASK_SETUP_VIRTQ, + MLX5_VDPA_TASK_STOP_VIRTQ, }; /* Generic task information and size must be multiple of 4B. */ diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c index 1389d369ae..98369f0887 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c @@ -104,6 +104,7 @@ mlx5_vdpa_c_thread_handle(void *arg) struct mlx5_vdpa_priv *priv; struct mlx5_vdpa_task task; struct rte_ring *rng; + uint64_t features; uint32_t thrd_idx; uint32_t task_num; int ret; @@ -153,6 +154,39 @@ mlx5_vdpa_c_thread_handle(void *arg) } pthread_mutex_unlock(&virtq->virtq_lock); break; + case MLX5_VDPA_TASK_STOP_VIRTQ: + virtq = &priv->virtqs[task.idx]; + pthread_mutex_lock(&virtq->virtq_lock); + ret = mlx5_vdpa_virtq_stop(priv, + task.idx); + if (ret) { + DRV_LOG(ERR, + "Failed to stop virtq %d.", + task.idx); + __atomic_fetch_add( + task.err_cnt, 1, + __ATOMIC_RELAXED); + pthread_mutex_unlock(&virtq->virtq_lock); + break; + } + ret = rte_vhost_get_negotiated_features( + priv->vid, &features); + if (ret) { + DRV_LOG(ERR, + "Failed to get negotiated features virtq %d.", + task.idx); + __atomic_fetch_add( + task.err_cnt, 1, + __ATOMIC_RELAXED); + pthread_mutex_unlock(&virtq->virtq_lock); + break; + } + if (RTE_VHOST_NEED_LOG(features)) + rte_vhost_log_used_vring( + priv->vid, task.idx, 0, + MLX5_VDPA_USED_RING_LEN(virtq->vq_size)); + pthread_mutex_unlock(&virtq->virtq_lock); + break; default: DRV_LOG(ERR, "Invalid vdpa task type %d.", task.type); diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_lm.c b/drivers/vdpa/mlx5/mlx5_vdpa_lm.c index efebf364d0..c2e78218ca 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_lm.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_lm.c @@ -89,39 +89,90 @@ mlx5_vdpa_dirty_bitmap_set(struct mlx5_vdpa_priv *priv, uint64_t log_base, return -1; } -#define MLX5_VDPA_USED_RING_LEN(size) \ - ((size) * sizeof(struct vring_used_elem) + sizeof(uint16_t) * 3) - int mlx5_vdpa_lm_log(struct mlx5_vdpa_priv *priv) { + uint32_t remaining_cnt = 0, err_cnt = 0, task_num = 0; + uint32_t i, thrd_idx, data[1]; struct mlx5_vdpa_virtq *virtq; uint64_t features; - int ret = rte_vhost_get_negotiated_features(priv->vid, &features); - int i; + int ret; + ret = rte_vhost_get_negotiated_features(priv->vid, &features); if (ret) { DRV_LOG(ERR, "Failed to get negotiated features."); return -1; } - if (!RTE_VHOST_NEED_LOG(features)) - return 0; - for (i = 0; i < priv->nr_virtqs; ++i) { - virtq = &priv->virtqs[i]; - if (!priv->virtqs[i].virtq) { - DRV_LOG(DEBUG, "virtq %d is invalid for LM log.", i); - } else { + if (priv->use_c_thread && priv->nr_virtqs) { + uint32_t main_task_idx[priv->nr_virtqs]; + + for (i = 0; i < priv->nr_virtqs; i++) { + virtq = &priv->virtqs[i]; + if (!virtq->configured) + continue; + thrd_idx = i % (conf_thread_mng.max_thrds + 1); + if (!thrd_idx) { + main_task_idx[task_num] = i; + task_num++; + continue; + } + thrd_idx = priv->last_c_thrd_idx + 1; + if (thrd_idx >= conf_thread_mng.max_thrds) + thrd_idx = 0; + priv->last_c_thrd_idx = thrd_idx; + data[0] = i; + if (mlx5_vdpa_task_add(priv, thrd_idx, + MLX5_VDPA_TASK_STOP_VIRTQ, + &remaining_cnt, &err_cnt, + (void **)&data, 1)) { + DRV_LOG(ERR, "Fail to add " + "task stop virtq (%d).", i); + main_task_idx[task_num] = i; + task_num++; + } + } + for (i = 0; i < task_num; i++) { + virtq = &priv->virtqs[main_task_idx[i]]; pthread_mutex_lock(&virtq->virtq_lock); - ret = mlx5_vdpa_virtq_stop(priv, i); + ret = mlx5_vdpa_virtq_stop(priv, + main_task_idx[i]); + if (ret) { + pthread_mutex_unlock(&virtq->virtq_lock); + DRV_LOG(ERR, + "Failed to stop virtq %d.", i); + return -1; + } + if (RTE_VHOST_NEED_LOG(features)) + rte_vhost_log_used_vring(priv->vid, i, 0, + MLX5_VDPA_USED_RING_LEN(virtq->vq_size)); pthread_mutex_unlock(&virtq->virtq_lock); + } + if (mlx5_vdpa_c_thread_wait_bulk_tasks_done(&remaining_cnt, + &err_cnt, 2000)) { + DRV_LOG(ERR, + "Failed to wait virt-queue setup tasks ready."); + return -1; + } + } else { + for (i = 0; i < priv->nr_virtqs; i++) { + virtq = &priv->virtqs[i]; + pthread_mutex_lock(&virtq->virtq_lock); + if (!virtq->configured) { + pthread_mutex_unlock(&virtq->virtq_lock); + continue; + } + ret = mlx5_vdpa_virtq_stop(priv, i); if (ret) { - DRV_LOG(ERR, "Failed to stop virtq %d for LM " - "log.", i); + pthread_mutex_unlock(&virtq->virtq_lock); + DRV_LOG(ERR, + "Failed to stop virtq %d for LM log.", i); return -1; } + if (RTE_VHOST_NEED_LOG(features)) + rte_vhost_log_used_vring(priv->vid, i, 0, + MLX5_VDPA_USED_RING_LEN(virtq->vq_size)); + pthread_mutex_unlock(&virtq->virtq_lock); } - rte_vhost_log_used_vring(priv->vid, i, 0, - MLX5_VDPA_USED_RING_LEN(priv->virtqs[i].vq_size)); } return 0; } From patchwork Mon Jun 6 11:21:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112367 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0C3AEA0543; Mon, 6 Jun 2022 13:24:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B4E4442BDA; Mon, 6 Jun 2022 13:22:56 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2075.outbound.protection.outlook.com [40.107.244.75]) by mails.dpdk.org (Postfix) with ESMTP id 3B9A142BD6 for ; Mon, 6 Jun 2022 13:22:55 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=No5KBLE9rDNN4SQYy3PKxqRkMy6IQDSOILmVgLVwgfsRNrgBbkgWdoSC2Z3KUZJIcf5k0Z7o1Qqbyv5rFrxKRwc9EzLxu+R6O0GNvZ7FSFnsoLLmczOn48QwQE8RxYLodmkMc1cboSDalrz/8ppS53LslacKx+rax4oVHREMlGHlVcqIFxNxGjvL/6Qaztn9yydTMuGIjpsbk5MovFpx2jhlqSuFU/V6jxStBE7r/1wP2XrE97Wjv5ehx5r7P6I/Hn4bn2XZw3LrczQCYy4JChljdMvyihRKt+RyyM5dC+9zZsUGTcfAZBdiSIxeSwvHNRojijRl3Jo0yME0mHC1Vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=CFwda5vOA5XlHexKDRkII1aR3V+Nqm/BytjADmQ2iyE=; b=bpTK0mkt56/TdZi1M8rkFp6hOIdoV4ti3+bqndB5qcyotB8D28XzAdUWiOC9g3KAkenhVPsiACd7FKlUGxIGW4scjtUe53C4OJs+3f8DpPKtXb8/V9qNtxVcqaxBCCAM26JDNftArVwjl3Yu5tFpOqZ0C2WDxjKSI2qKrGmX6XnVa0Ldq1p5mqSAgNXPZxVHU7i0uKCBby0V0TLUZjNCvQCdYO5DCbiu0LIxjr8/zOnDSGFZKyX6A9eRVqxJt2YlXlvYs4+2rJjrZvMlA6IKEkaTqnqmu+sXr1FHV4mhtI0y2mfqFG4cXV3YOn820qiYVqTXULNh2QxK8HUiJ/X07Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CFwda5vOA5XlHexKDRkII1aR3V+Nqm/BytjADmQ2iyE=; b=Y8LbITcWb7d4ZLvqKg93ZNwFgF7ESHT4KmfHR+nCjE1PGihxL9TgRdgvmxhXYuTHdjPkQirD88a35rXmz+4Gp2L54VZlb6hwegHKPxPjA4Onni5cR1PXZOKugEk6A5xQa3OGk1bZCcxFonSuMghUQYBRsCYzdWBB5nH1xG1WaVRmCcBxhbbsl4IPRbiQSjlSNuC5GCt2T9ACo9QKMTM4eT1cHv4Bkc377Rydk/Ye+cX/tzr8RqtP60MEk1FYkMHE/bFRHlpNEXB9tsUPBF3izcnhSj1eQVFC8LiluGjSM4dZjQTj2w/cb0T6DFjSt54A2ST4/HB4zJ1rBcB7BRhRmg== Received: from BN6PR21CA0006.namprd21.prod.outlook.com (2603:10b6:404:8e::16) by CH2PR12MB4262.namprd12.prod.outlook.com (2603:10b6:610:af::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13; Mon, 6 Jun 2022 11:22:53 +0000 Received: from BN8NAM11FT038.eop-nam11.prod.protection.outlook.com (2603:10b6:404:8e:cafe::15) by BN6PR21CA0006.outlook.office365.com (2603:10b6:404:8e::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5353.1 via Frontend Transport; Mon, 6 Jun 2022 11:22:53 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.236) by BN8NAM11FT038.mail.protection.outlook.com (10.13.176.246) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:52 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:22:51 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:22:48 -0700 From: Li Zhang To: , , , CC: , , , Subject: [PATCH 14/16] vdpa/mlx5: add device close task Date: Mon, 6 Jun 2022 14:21:03 +0300 Message-ID: <20220606112109.208873-27-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ec2c72ff-be5b-4384-6873-08da47aee594 X-MS-TrafficTypeDiagnostic: CH2PR12MB4262:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jPUDkBCCZ6W3tsmnyTXFA0vqb4X6x/v4aKnz2X2JDrGShsranPL2o079q9IcR1+zcpOmu1YopCXQnWFzY3W8GqwAPZTWR+YFp62xmqVnE+TgsSer4Pc2csbNODOPEWuylTxleX+RGlw5FEinrKEV8H4zeVTfHiajH00SSRGCzGdt8Ic12wCpzXn/Z5Vhafb2L0h6TD6GiZRc0dhb/Z2GZzozq/7MSjfTLaHR2VMMQxVMO64pplBiFGx5HyfaRpEDfoDendEKdYwiMe5Ts/nt6oq7WPZj2t1NCTwkUhr0uXjNY/f2WwLVMJuVPLgebbiFsh/AEuxCMeEYTKn3alMTMbgeDJp1pz7AzSs+DgoDRKEf+2sGmv2BX0FyxILCJ5+BhOID7K2XLh7cv9RMSCrqxUK56+IY23FgXQ6IptZzKdrtbMk/cF9+5xUYuBQc0OnIyXQ6T7RlC0kLpJxdm+q+kcfhG+FdKNFNJos99Icf6a4Gpjm8RvAHD3qKf0loimvNDDaYX8BSheZUZtiidWCBI7ooRbrdTMhN8kJr0fhrzsih2NPRK1UDILKM9vxyHRMt3AtW58cd+ZD1Jv013xx2/qAUPOARGO/LJ/eXVb04TdEWs0QstTL5EU6iHlWTuKxju9UYTNKrEoEJJlH5KFUx3o26k0hPyvmPKMkMrOod7uZKidux9G/Et8h6F36hpm8H2BGL+7HZevTdq01mkoDKNg== X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(55016003)(186003)(16526019)(86362001)(316002)(426003)(40460700003)(8936002)(1076003)(54906003)(36860700001)(110136005)(508600001)(70206006)(70586007)(8676002)(82310400005)(107886003)(4326008)(6636002)(2616005)(81166007)(336012)(356005)(7696005)(2906002)(47076005)(6666004)(5660300002)(26005)(36756003)(6286002)(83380400001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:22:52.6218 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ec2c72ff-be5b-4384-6873-08da47aee594 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4262 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Split the virtqs device close tasks after stopping virt-queue between the configuration threads. This accelerates the LM process and reduces its time by 50%. Signed-off-by: Li Zhang --- drivers/vdpa/mlx5/mlx5_vdpa.c | 56 +++++++++++++++++++++++++-- drivers/vdpa/mlx5/mlx5_vdpa.h | 8 ++++ drivers/vdpa/mlx5/mlx5_vdpa_cthread.c | 20 +++++++++- drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 14 +++++++ 4 files changed, 94 insertions(+), 4 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c index e3b32fa087..d000854c08 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa.c @@ -245,7 +245,7 @@ mlx5_vdpa_mtu_set(struct mlx5_vdpa_priv *priv) return kern_mtu == vhost_mtu ? 0 : -1; } -static void +void mlx5_vdpa_dev_cache_clean(struct mlx5_vdpa_priv *priv) { /* Clean pre-created resource in dev removal only. */ @@ -254,6 +254,26 @@ mlx5_vdpa_dev_cache_clean(struct mlx5_vdpa_priv *priv) mlx5_vdpa_mem_dereg(priv); } +static bool +mlx5_vdpa_wait_dev_close_tasks_done(struct mlx5_vdpa_priv *priv) +{ + uint32_t timeout = 0; + + /* Check and wait all close tasks done. */ + while (__atomic_load_n(&priv->dev_close_progress, + __ATOMIC_RELAXED) != 0 && timeout < 1000) { + rte_delay_us_sleep(10000); + timeout++; + } + if (priv->dev_close_progress) { + DRV_LOG(ERR, + "Failed to wait close device tasks done vid %d.", + priv->vid); + return true; + } + return false; +} + static int mlx5_vdpa_dev_close(int vid) { @@ -271,6 +291,27 @@ mlx5_vdpa_dev_close(int vid) ret |= mlx5_vdpa_lm_log(priv); priv->state = MLX5_VDPA_STATE_IN_PROGRESS; } + if (priv->use_c_thread) { + if (priv->last_c_thrd_idx >= + (conf_thread_mng.max_thrds - 1)) + priv->last_c_thrd_idx = 0; + else + priv->last_c_thrd_idx++; + __atomic_store_n(&priv->dev_close_progress, + 1, __ATOMIC_RELAXED); + if (mlx5_vdpa_task_add(priv, + priv->last_c_thrd_idx, + MLX5_VDPA_TASK_DEV_CLOSE_NOWAIT, + NULL, NULL, NULL, 1)) { + DRV_LOG(ERR, + "Fail to add dev close task. "); + goto single_thrd; + } + priv->state = MLX5_VDPA_STATE_PROBED; + DRV_LOG(INFO, "vDPA device %d was closed.", vid); + return ret; + } +single_thrd: pthread_mutex_lock(&priv->steer_update_lock); mlx5_vdpa_steer_unset(priv); pthread_mutex_unlock(&priv->steer_update_lock); @@ -278,10 +319,12 @@ mlx5_vdpa_dev_close(int vid) mlx5_vdpa_drain_cq(priv); if (priv->lm_mr.addr) mlx5_os_wrapped_mkey_destroy(&priv->lm_mr); - priv->state = MLX5_VDPA_STATE_PROBED; if (!priv->connected) mlx5_vdpa_dev_cache_clean(priv); priv->vid = 0; + __atomic_store_n(&priv->dev_close_progress, 0, + __ATOMIC_RELAXED); + priv->state = MLX5_VDPA_STATE_PROBED; DRV_LOG(INFO, "vDPA device %d was closed.", vid); return ret; } @@ -302,6 +345,8 @@ mlx5_vdpa_dev_config(int vid) DRV_LOG(ERR, "Failed to reconfigure vid %d.", vid); return -1; } + if (mlx5_vdpa_wait_dev_close_tasks_done(priv)) + return -1; priv->vid = vid; priv->connected = true; if (mlx5_vdpa_mtu_set(priv)) @@ -444,8 +489,11 @@ mlx5_vdpa_dev_cleanup(int vid) DRV_LOG(ERR, "Invalid vDPA device: %s.", vdev->device->name); return -1; } - if (priv->state == MLX5_VDPA_STATE_PROBED) + if (priv->state == MLX5_VDPA_STATE_PROBED) { + if (priv->use_c_thread) + mlx5_vdpa_wait_dev_close_tasks_done(priv); mlx5_vdpa_dev_cache_clean(priv); + } priv->connected = false; return 0; } @@ -839,6 +887,8 @@ mlx5_vdpa_dev_release(struct mlx5_vdpa_priv *priv) { if (priv->state == MLX5_VDPA_STATE_CONFIGURED) mlx5_vdpa_dev_close(priv->vid); + if (priv->use_c_thread) + mlx5_vdpa_wait_dev_close_tasks_done(priv); mlx5_vdpa_release_dev_resources(priv); if (priv->vdev) rte_vdpa_unregister_device(priv->vdev); diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index e08931719f..b6392b9d66 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -84,6 +84,7 @@ enum mlx5_vdpa_task_type { MLX5_VDPA_TASK_REG_MR = 1, MLX5_VDPA_TASK_SETUP_VIRTQ, MLX5_VDPA_TASK_STOP_VIRTQ, + MLX5_VDPA_TASK_DEV_CLOSE_NOWAIT, }; /* Generic task information and size must be multiple of 4B. */ @@ -206,6 +207,7 @@ struct mlx5_vdpa_priv { uint64_t features; /* Negotiated features. */ uint16_t log_max_rqt_size; uint16_t last_c_thrd_idx; + uint16_t dev_close_progress; uint16_t num_mrs; /* Number of memory regions. */ struct mlx5_vdpa_steer steer; struct mlx5dv_var *var; @@ -578,4 +580,10 @@ mlx5_vdpa_c_thread_wait_bulk_tasks_done(uint32_t *remaining_cnt, uint32_t *err_cnt, uint32_t sleep_time); int mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index, bool reg_kick); +void +mlx5_vdpa_vq_destroy(struct mlx5_vdpa_virtq *virtq); +void +mlx5_vdpa_dev_cache_clean(struct mlx5_vdpa_priv *priv); +void +mlx5_vdpa_virtq_unreg_intr_handle_all(struct mlx5_vdpa_priv *priv); #endif /* RTE_PMD_MLX5_VDPA_H_ */ diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c index 98369f0887..bb2279440b 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c @@ -63,7 +63,8 @@ mlx5_vdpa_task_add(struct mlx5_vdpa_priv *priv, task[i].type = task_type; task[i].remaining_cnt = remaining_cnt; task[i].err_cnt = err_cnt; - task[i].idx = data[i]; + if (data) + task[i].idx = data[i]; } if (!mlx5_vdpa_c_thrd_ring_enqueue_bulk(rng, (void **)&task, num, NULL)) return -1; @@ -187,6 +188,23 @@ mlx5_vdpa_c_thread_handle(void *arg) MLX5_VDPA_USED_RING_LEN(virtq->vq_size)); pthread_mutex_unlock(&virtq->virtq_lock); break; + case MLX5_VDPA_TASK_DEV_CLOSE_NOWAIT: + mlx5_vdpa_virtq_unreg_intr_handle_all(priv); + pthread_mutex_lock(&priv->steer_update_lock); + mlx5_vdpa_steer_unset(priv); + pthread_mutex_unlock(&priv->steer_update_lock); + mlx5_vdpa_virtqs_release(priv); + mlx5_vdpa_drain_cq(priv); + if (priv->lm_mr.addr) + mlx5_os_wrapped_mkey_destroy( + &priv->lm_mr); + if (!priv->connected) + mlx5_vdpa_dev_cache_clean(priv); + priv->vid = 0; + __atomic_store_n( + &priv->dev_close_progress, 0, + __ATOMIC_RELAXED); + break; default: DRV_LOG(ERR, "Invalid vdpa task type %d.", task.type); diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c index db05220e76..a08c854b14 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c @@ -102,6 +102,20 @@ mlx5_vdpa_virtq_unregister_intr_handle(struct mlx5_vdpa_virtq *virtq) virtq->intr_handle = NULL; } +void +mlx5_vdpa_virtq_unreg_intr_handle_all(struct mlx5_vdpa_priv *priv) +{ + uint32_t i; + struct mlx5_vdpa_virtq *virtq; + + for (i = 0; i < priv->nr_virtqs; i++) { + virtq = &priv->virtqs[i]; + pthread_mutex_lock(&virtq->virtq_lock); + mlx5_vdpa_virtq_unregister_intr_handle(virtq); + pthread_mutex_unlock(&virtq->virtq_lock); + } +} + /* Release cached VQ resources. */ void mlx5_vdpa_virtqs_cleanup(struct mlx5_vdpa_priv *priv) From patchwork Mon Jun 6 11:21:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112370 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8C539A0543; Mon, 6 Jun 2022 13:25:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 10A6842BF5; Mon, 6 Jun 2022 13:23:02 +0200 (CEST) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2054.outbound.protection.outlook.com [40.107.92.54]) by mails.dpdk.org (Postfix) with ESMTP id 2E570427F3 for ; Mon, 6 Jun 2022 13:23:00 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=b2YQL+xAQu4+a6jouM360sCwf+Hgzup43FwURwHm3f3fAVukSZRZNetfWnmZhwPWEGoEIEcT2SR43DbNZ777iuLCNG7JiZso6m8FRfGZQioFt/BTuyLIlGtDBounJyJXlsRsH+E5yqcYp2s/1OIDOa9UME8sHrp7Ubp5g0fu5HtCpjuT1NJ75wNnkUg8FwZk0fbZoSjfzqOjpAyJaA6cjeSwnSBka3XU8zbbUgaeiMgdrYnamwkAxhR0avezjwq652NdjNnTlmd1aolAE1pQ3xSShGsAHU7qi71JiTW8+TocPjfL0Ym7inwVpjI1d1k83v7s3gkLNGvRaWQQETsPHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=CFwda5vOA5XlHexKDRkII1aR3V+Nqm/BytjADmQ2iyE=; b=L2rV9tVwZjynqd3j85z2FHA2NivNplhAZm/EOG0lNfy2sANc/FKlVloQGZU7h7lbuHlptF/wRlPYio/fYe6HPAp1UD+DEgrV5CJZvD58gdMkPR2KMlXky3GYq1VNcLmJUkBFexPS6RnEfqXw9ocLpTkZ6glBeI1l/w89euu1wVfbBSKHF+oXqySfxYIHJoloPH2LLxozGuVIb8jIgkt20Am/0V6oMobD8LQjYtYbvqZ+PiocOUxOgNDfZ7aNDMbeRS40XpbXo2ZQ77VZsje04LvenKkY8eHDzKEyatiGvtCVQgESG5l6r526IpvbQJsJiAs8PRZG5VWj3j3W7hMJMw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.238) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CFwda5vOA5XlHexKDRkII1aR3V+Nqm/BytjADmQ2iyE=; b=e3jBLfQLUhHdqAmAn511TdvxW+RL8JQURsA8a0iwYwAWYCbZkRelTPGxgNK++xHVGbt08ABMDKrRYD9odHIGd+jmF3DdnbeByxGetNjhDxtArpfr3r09ZSAxeq+lOgIlsgjkIrwKX2jTxIK54+U4/6xJ4OmrEuqyc3Nyd+wyGlyD5ANrecUv6rHo5JS58tFYuLtRktaA4O7QGd7rUeCxqPSRu26kgZ7928bv+7qUu2ps8mL8c1xOYvJWZIgriH7Dd3hXHjtcxWT/crUlsRYgzhq7iJQSgrZhcA4DPK635NUZVDx53Jnzc0r0XKx8GFA3KSkUybaQ3GT6VugGME4fQw== Received: from DM6PR07CA0103.namprd07.prod.outlook.com (2603:10b6:5:330::35) by MWHPR12MB1696.namprd12.prod.outlook.com (2603:10b6:301:8::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.15; Mon, 6 Jun 2022 11:22:58 +0000 Received: from DM6NAM11FT029.eop-nam11.prod.protection.outlook.com (2603:10b6:5:330:cafe::ba) by DM6PR07CA0103.outlook.office365.com (2603:10b6:5:330::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:58 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.238) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.238) by DM6NAM11FT029.mail.protection.outlook.com (10.13.173.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:22:58 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:22:57 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:22:54 -0700 From: Li Zhang To: , , , CC: , , , Subject: [PATCH v1 15/17] vdpa/mlx5: add device close task Date: Mon, 6 Jun 2022 14:21:05 +0300 Message-ID: <20220606112109.208873-29-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 38cbcee8-293d-4ddc-cd81-08da47aee8c6 X-MS-TrafficTypeDiagnostic: MWHPR12MB1696:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cRW/diiTwHdIdPplGBU59tCD2BbpghC4WSzJCD72J3fTlskqJMkQJkdkyaJHcM76GG3YHOqwQeXDVORLvD0x8qJi8ZHk60JwIUD+FmZCHDnGPXju1ED/WgbXFo5ywguQrETUwQ+YpRfWCsyFDj2EqufZ7tNnP/iDev+FJx8gXLUsAtq2EFi5uurUyl+97NUP0YcbDywUvkhLLOS2dOjRuCQsvbgMFbgS+NRjwe7Z0XS0IXe6xP8S3npJP6/fatoQ7ezZY59S/eIOiJELiTPaYblkTiqTV2qZ5Dm4/nNnf6yPgKX90b7XJDNKLPsZ6Yx27Sf3v4XZV2szvpvXUlW2WqxZ3nxmaFy4ps/WiKHNBah7jsi3JukEDUazMcxqD0Td2OgfQ8qSz4LFqbuQL4tOCLBPxTT3W4TqH9nnfVx97+pAKGibYEBH7Iz4NZVf3/KuaKWfKjhh4IMdhjX06pS4KrMrql6YToKnF1nq1KQaCibmcXi93WdxyxBjlPvL0lfvB6wlnOV8EOJc8Jp0kA/ZXSvetLoczFcMtlG7jxh9MFxkPeYSkxBnZ9skdjxXhmZDbBA3w5cTyHFhZ65zJfbnK8lqdMmn5xGcLc9CDTYsVGrqjHO8hKSrca7P6VEnaReGE9D5xWY88mSBhJjS2g0gQuwibPQJhBoUcUTAgu4Dvz+3MzEKwcwU91+psQeSNuroxNYYepMpIijMUqs1SDHgQw== X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(83380400001)(336012)(186003)(6636002)(47076005)(426003)(2616005)(70206006)(1076003)(54906003)(8676002)(107886003)(70586007)(110136005)(16526019)(316002)(7696005)(6286002)(6666004)(2906002)(26005)(40460700003)(36756003)(508600001)(55016003)(8936002)(4326008)(5660300002)(36860700001)(86362001)(81166007)(356005)(82310400005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:22:58.0477 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 38cbcee8-293d-4ddc-cd81-08da47aee8c6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1696 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Split the virtqs device close tasks after stopping virt-queue between the configuration threads. This accelerates the LM process and reduces its time by 50%. Signed-off-by: Li Zhang --- drivers/vdpa/mlx5/mlx5_vdpa.c | 56 +++++++++++++++++++++++++-- drivers/vdpa/mlx5/mlx5_vdpa.h | 8 ++++ drivers/vdpa/mlx5/mlx5_vdpa_cthread.c | 20 +++++++++- drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 14 +++++++ 4 files changed, 94 insertions(+), 4 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c index e3b32fa087..d000854c08 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa.c @@ -245,7 +245,7 @@ mlx5_vdpa_mtu_set(struct mlx5_vdpa_priv *priv) return kern_mtu == vhost_mtu ? 0 : -1; } -static void +void mlx5_vdpa_dev_cache_clean(struct mlx5_vdpa_priv *priv) { /* Clean pre-created resource in dev removal only. */ @@ -254,6 +254,26 @@ mlx5_vdpa_dev_cache_clean(struct mlx5_vdpa_priv *priv) mlx5_vdpa_mem_dereg(priv); } +static bool +mlx5_vdpa_wait_dev_close_tasks_done(struct mlx5_vdpa_priv *priv) +{ + uint32_t timeout = 0; + + /* Check and wait all close tasks done. */ + while (__atomic_load_n(&priv->dev_close_progress, + __ATOMIC_RELAXED) != 0 && timeout < 1000) { + rte_delay_us_sleep(10000); + timeout++; + } + if (priv->dev_close_progress) { + DRV_LOG(ERR, + "Failed to wait close device tasks done vid %d.", + priv->vid); + return true; + } + return false; +} + static int mlx5_vdpa_dev_close(int vid) { @@ -271,6 +291,27 @@ mlx5_vdpa_dev_close(int vid) ret |= mlx5_vdpa_lm_log(priv); priv->state = MLX5_VDPA_STATE_IN_PROGRESS; } + if (priv->use_c_thread) { + if (priv->last_c_thrd_idx >= + (conf_thread_mng.max_thrds - 1)) + priv->last_c_thrd_idx = 0; + else + priv->last_c_thrd_idx++; + __atomic_store_n(&priv->dev_close_progress, + 1, __ATOMIC_RELAXED); + if (mlx5_vdpa_task_add(priv, + priv->last_c_thrd_idx, + MLX5_VDPA_TASK_DEV_CLOSE_NOWAIT, + NULL, NULL, NULL, 1)) { + DRV_LOG(ERR, + "Fail to add dev close task. "); + goto single_thrd; + } + priv->state = MLX5_VDPA_STATE_PROBED; + DRV_LOG(INFO, "vDPA device %d was closed.", vid); + return ret; + } +single_thrd: pthread_mutex_lock(&priv->steer_update_lock); mlx5_vdpa_steer_unset(priv); pthread_mutex_unlock(&priv->steer_update_lock); @@ -278,10 +319,12 @@ mlx5_vdpa_dev_close(int vid) mlx5_vdpa_drain_cq(priv); if (priv->lm_mr.addr) mlx5_os_wrapped_mkey_destroy(&priv->lm_mr); - priv->state = MLX5_VDPA_STATE_PROBED; if (!priv->connected) mlx5_vdpa_dev_cache_clean(priv); priv->vid = 0; + __atomic_store_n(&priv->dev_close_progress, 0, + __ATOMIC_RELAXED); + priv->state = MLX5_VDPA_STATE_PROBED; DRV_LOG(INFO, "vDPA device %d was closed.", vid); return ret; } @@ -302,6 +345,8 @@ mlx5_vdpa_dev_config(int vid) DRV_LOG(ERR, "Failed to reconfigure vid %d.", vid); return -1; } + if (mlx5_vdpa_wait_dev_close_tasks_done(priv)) + return -1; priv->vid = vid; priv->connected = true; if (mlx5_vdpa_mtu_set(priv)) @@ -444,8 +489,11 @@ mlx5_vdpa_dev_cleanup(int vid) DRV_LOG(ERR, "Invalid vDPA device: %s.", vdev->device->name); return -1; } - if (priv->state == MLX5_VDPA_STATE_PROBED) + if (priv->state == MLX5_VDPA_STATE_PROBED) { + if (priv->use_c_thread) + mlx5_vdpa_wait_dev_close_tasks_done(priv); mlx5_vdpa_dev_cache_clean(priv); + } priv->connected = false; return 0; } @@ -839,6 +887,8 @@ mlx5_vdpa_dev_release(struct mlx5_vdpa_priv *priv) { if (priv->state == MLX5_VDPA_STATE_CONFIGURED) mlx5_vdpa_dev_close(priv->vid); + if (priv->use_c_thread) + mlx5_vdpa_wait_dev_close_tasks_done(priv); mlx5_vdpa_release_dev_resources(priv); if (priv->vdev) rte_vdpa_unregister_device(priv->vdev); diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index e08931719f..b6392b9d66 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -84,6 +84,7 @@ enum mlx5_vdpa_task_type { MLX5_VDPA_TASK_REG_MR = 1, MLX5_VDPA_TASK_SETUP_VIRTQ, MLX5_VDPA_TASK_STOP_VIRTQ, + MLX5_VDPA_TASK_DEV_CLOSE_NOWAIT, }; /* Generic task information and size must be multiple of 4B. */ @@ -206,6 +207,7 @@ struct mlx5_vdpa_priv { uint64_t features; /* Negotiated features. */ uint16_t log_max_rqt_size; uint16_t last_c_thrd_idx; + uint16_t dev_close_progress; uint16_t num_mrs; /* Number of memory regions. */ struct mlx5_vdpa_steer steer; struct mlx5dv_var *var; @@ -578,4 +580,10 @@ mlx5_vdpa_c_thread_wait_bulk_tasks_done(uint32_t *remaining_cnt, uint32_t *err_cnt, uint32_t sleep_time); int mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index, bool reg_kick); +void +mlx5_vdpa_vq_destroy(struct mlx5_vdpa_virtq *virtq); +void +mlx5_vdpa_dev_cache_clean(struct mlx5_vdpa_priv *priv); +void +mlx5_vdpa_virtq_unreg_intr_handle_all(struct mlx5_vdpa_priv *priv); #endif /* RTE_PMD_MLX5_VDPA_H_ */ diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c index 98369f0887..bb2279440b 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c @@ -63,7 +63,8 @@ mlx5_vdpa_task_add(struct mlx5_vdpa_priv *priv, task[i].type = task_type; task[i].remaining_cnt = remaining_cnt; task[i].err_cnt = err_cnt; - task[i].idx = data[i]; + if (data) + task[i].idx = data[i]; } if (!mlx5_vdpa_c_thrd_ring_enqueue_bulk(rng, (void **)&task, num, NULL)) return -1; @@ -187,6 +188,23 @@ mlx5_vdpa_c_thread_handle(void *arg) MLX5_VDPA_USED_RING_LEN(virtq->vq_size)); pthread_mutex_unlock(&virtq->virtq_lock); break; + case MLX5_VDPA_TASK_DEV_CLOSE_NOWAIT: + mlx5_vdpa_virtq_unreg_intr_handle_all(priv); + pthread_mutex_lock(&priv->steer_update_lock); + mlx5_vdpa_steer_unset(priv); + pthread_mutex_unlock(&priv->steer_update_lock); + mlx5_vdpa_virtqs_release(priv); + mlx5_vdpa_drain_cq(priv); + if (priv->lm_mr.addr) + mlx5_os_wrapped_mkey_destroy( + &priv->lm_mr); + if (!priv->connected) + mlx5_vdpa_dev_cache_clean(priv); + priv->vid = 0; + __atomic_store_n( + &priv->dev_close_progress, 0, + __ATOMIC_RELAXED); + break; default: DRV_LOG(ERR, "Invalid vdpa task type %d.", task.type); diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c index db05220e76..a08c854b14 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c @@ -102,6 +102,20 @@ mlx5_vdpa_virtq_unregister_intr_handle(struct mlx5_vdpa_virtq *virtq) virtq->intr_handle = NULL; } +void +mlx5_vdpa_virtq_unreg_intr_handle_all(struct mlx5_vdpa_priv *priv) +{ + uint32_t i; + struct mlx5_vdpa_virtq *virtq; + + for (i = 0; i < priv->nr_virtqs; i++) { + virtq = &priv->virtqs[i]; + pthread_mutex_lock(&virtq->virtq_lock); + mlx5_vdpa_virtq_unregister_intr_handle(virtq); + pthread_mutex_unlock(&virtq->virtq_lock); + } +} + /* Release cached VQ resources. */ void mlx5_vdpa_virtqs_cleanup(struct mlx5_vdpa_priv *priv) From patchwork Mon Jun 6 11:21:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112372 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D42E7A0543; Mon, 6 Jun 2022 13:25:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4BCB042B7B; Mon, 6 Jun 2022 13:23:11 +0200 (CEST) Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2075.outbound.protection.outlook.com [40.107.102.75]) by mails.dpdk.org (Postfix) with ESMTP id 3581D42B94 for ; Mon, 6 Jun 2022 13:23:09 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=G0xwYYsr58nNJYi29cfHA2LZNf4Sg9Hpt3t8KIvInzkqW9AB5ecJgu11VN6kdvkN2BWZaKujgM0ZP8xT9vIyjsWGQvL7wz8Ky+Ft7j6AYyDrMcIMKnC/lF16BGPFlGJG7lGLEew8dI2eQqZQ2zz9pMAe3bRCjt/H74XkIUufFGc+UH18pru+eMILmRD1RLvy5avxTkgt/TQHJpMwEyQTjfk2oXVf3FmCzMG1GQI1A4BIl5IFxrx76hTaNwdcMos4wDfN7PvnoMPB0Z6yCEgyOY59f2hoGRmm7GBVfujizTlwCONZCA7NWfr0tMZg0XrnKIH93ddyrh8dOGwFap8wxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=XsUnvxy0pfveSZZ6jgiaSH5PTTAq7dr+MbccXrR8wgI=; b=Fugu/mOH9kZ3SLTndq2eEHjnbIPkI09bkw5odtEiBpsTE8N7JQKFCQ8OY1F9lUYJKW2i1BrW+fhwDU3uaTaEkMKxMNIkR2rPELP72iP71ytxi7AywqpWLjmpGJarU2MPpr6Z7ITvadebacpQ3WBRtJKeoLEXiqzzgAdauhvkVw+owH6tdU5cgPoHF0dDqYkLzAku8enimEezyN0pKWKR46UR2Or+dIyCy+LpCGdcwDdZGfCoiiLG1A1UVPSmJ4bive9ZDUnfarHT+bKCtUlvRzVOHrtWAxZs6qt7Ki42Z/WvMiTsxZDjbMEZ9mtvw4VgzRfDQ06uLfZVb32qfvJYug== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.238) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XsUnvxy0pfveSZZ6jgiaSH5PTTAq7dr+MbccXrR8wgI=; b=IaDAUuZ/pqg1l5gXgNnklc069IvsT1XWwU+gDDQsYo5hF5kzNgLwHklgEyjgXyPlG6I8EXcKy78TKVheEqxvOYPjWzIUIOkbGn1rcqDYBpMkEz2LwoczLFoTdEzs5RqHu5+RcugGBjf3KD8ikJEE4nENppJwyasFBVF1sunhda/tl5PiA26N5vmXe4Us/0e6U9XgW6nqXgqFnMiH9p56nXBlE34bL23FlH2xNjmkPjSEnXhABmrrMnpHOtsy7VELgtuEkXAHVb1Uu7E1OgVfqUwWrTL/Nzi4DdoVBGXi8jwhhD1BoZ+dFb4K8BofdPPqwoQG2mA2ttp2KVCaA1+gYg== Received: from DM3PR03CA0017.namprd03.prod.outlook.com (2603:10b6:0:50::27) by CY4PR12MB1367.namprd12.prod.outlook.com (2603:10b6:903:3c::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13; Mon, 6 Jun 2022 11:23:07 +0000 Received: from DM6NAM11FT035.eop-nam11.prod.protection.outlook.com (2603:10b6:0:50:cafe::9f) by DM3PR03CA0017.outlook.office365.com (2603:10b6:0:50::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:23:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.238) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.238) by DM6NAM11FT035.mail.protection.outlook.com (10.13.172.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:23:07 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:23:06 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:23:03 -0700 From: Li Zhang To: , , , CC: , , , Subject: [PATCH 16/16] vdpa/mlx5: prepare virtqueue resource creation Date: Mon, 6 Jun 2022 14:21:08 +0300 Message-ID: <20220606112109.208873-32-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b464f7bb-1da3-435d-7885-08da47aeee33 X-MS-TrafficTypeDiagnostic: CY4PR12MB1367:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ty1i3bMz1pDxT9MDTViWj2gIzZJV4YXmwqizbr+mAS+JGEovK0jc4zOwfpJIC2eZJvwrPyGRxufSO6hedDaNFKjRNfHG6rSuJPd1Sm8Pane+XdyKSy5UzQH8VCslZqeFlKLrDrbfj16LCrfGJbOuNFAATSgxXh22aO7KjlTcMuvZUgaD95WOSZu7TCm9bFB6T2SOy13IS7k7a6G62jfie2oKTL31VM4+5b31kg7qhQRpp8TwOB5bjonQGOuTVTaBHiWSMXeAyOAsEa1es9Sqp4ENBsoGASl/m9XazzegG4XvnsI/dFJqS/ZtdUhg5Jr+lvwfYCLkcu0Ke+Lc2d7jdcZefOoCNr5VZqpaSPlK9N/2N++96mp7xPgUjcwz1B2jvd9KN5LjuC8V54gDoQ9UmwItTQJe/vNba8Th2+r6vx5Rr0J5uEE/jHx3IXEBkoJONfXSEbxsTH9bA8P2WFTAcmU7yYSPVSS9HjNTTxjcXFsDyrpzIsMmpDGF1/7annB9DcqgmRx6jO892urfKJ8kVW3VyN8kgeqF+voHZSg8KVefsrVYprAhjW5Tje4PINmaatTcbYrN41csVJMmITRMyO+QIvGsjuw3ZMjQ9N55XYmSMNY4rnZV2GfnDWrylp8CInl5/84U3KtZDCuDehv5ZS9FjQlZ04g52xpfxM9myezgi7SjHn5XqtkUCC0/Fc8EINAHqwR7q3wCTXfU7sFvwg== X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(8676002)(8936002)(83380400001)(47076005)(426003)(54906003)(336012)(4326008)(110136005)(2906002)(7696005)(6636002)(356005)(70586007)(70206006)(36756003)(30864003)(1076003)(86362001)(316002)(508600001)(2616005)(81166007)(5660300002)(82310400005)(6286002)(36860700001)(107886003)(16526019)(40460700003)(186003)(26005)(55016003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:23:07.1016 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b464f7bb-1da3-435d-7885-08da47aeee33 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1367 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Split the virtqs virt-queue resource between the configuration threads. Also need pre-created virt-queue resource after virtq destruction. This accelerates the LM process and reduces its time by 30%. Signed-off-by: Li Zhang --- drivers/vdpa/mlx5/mlx5_vdpa.c | 115 ++++++++++++++++++++------ drivers/vdpa/mlx5/mlx5_vdpa.h | 12 ++- drivers/vdpa/mlx5/mlx5_vdpa_cthread.c | 15 +++- drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 111 +++++++++++++++++++++---- 4 files changed, 208 insertions(+), 45 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c index f006a9cd3f..c5d82872c7 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa.c @@ -275,23 +275,18 @@ mlx5_vdpa_wait_dev_close_tasks_done(struct mlx5_vdpa_priv *priv) } static int -mlx5_vdpa_dev_close(int vid) +_internal_mlx5_vdpa_dev_close(struct mlx5_vdpa_priv *priv, + bool release_resource) { - struct rte_vdpa_device *vdev = rte_vhost_get_vdpa_device(vid); - struct mlx5_vdpa_priv *priv = - mlx5_vdpa_find_priv_resource_by_vdev(vdev); int ret = 0; + int vid = priv->vid; - if (priv == NULL) { - DRV_LOG(ERR, "Invalid vDPA device: %s.", vdev->device->name); - return -1; - } mlx5_vdpa_cqe_event_unset(priv); if (priv->state == MLX5_VDPA_STATE_CONFIGURED) { ret |= mlx5_vdpa_lm_log(priv); priv->state = MLX5_VDPA_STATE_IN_PROGRESS; } - if (priv->use_c_thread) { + if (priv->use_c_thread && !release_resource) { if (priv->last_c_thrd_idx >= (conf_thread_mng.max_thrds - 1)) priv->last_c_thrd_idx = 0; @@ -315,7 +310,7 @@ mlx5_vdpa_dev_close(int vid) pthread_mutex_lock(&priv->steer_update_lock); mlx5_vdpa_steer_unset(priv); pthread_mutex_unlock(&priv->steer_update_lock); - mlx5_vdpa_virtqs_release(priv); + mlx5_vdpa_virtqs_release(priv, release_resource); mlx5_vdpa_drain_cq(priv); if (priv->lm_mr.addr) mlx5_os_wrapped_mkey_destroy(&priv->lm_mr); @@ -329,6 +324,24 @@ mlx5_vdpa_dev_close(int vid) return ret; } +static int +mlx5_vdpa_dev_close(int vid) +{ + struct rte_vdpa_device *vdev = rte_vhost_get_vdpa_device(vid); + struct mlx5_vdpa_priv *priv; + + if (!vdev) { + DRV_LOG(ERR, "Invalid vDPA device."); + return -1; + } + priv = mlx5_vdpa_find_priv_resource_by_vdev(vdev); + if (priv == NULL) { + DRV_LOG(ERR, "Invalid vDPA device: %s.", vdev->device->name); + return -1; + } + return _internal_mlx5_vdpa_dev_close(priv, false); +} + static int mlx5_vdpa_dev_config(int vid) { @@ -624,11 +637,33 @@ mlx5_vdpa_config_get(struct mlx5_kvargs_ctrl *mkvlist, priv->queue_size); } +void +mlx5_vdpa_prepare_virtq_destroy(struct mlx5_vdpa_priv *priv) +{ + uint32_t max_queues, index; + struct mlx5_vdpa_virtq *virtq; + + if (!priv->queues || !priv->queue_size) + return; + max_queues = ((priv->queues * 2) < priv->caps.max_num_virtio_queues) ? + (priv->queues * 2) : (priv->caps.max_num_virtio_queues); + if (mlx5_vdpa_is_modify_virtq_supported(priv)) + mlx5_vdpa_steer_unset(priv); + for (index = 0; index < max_queues; ++index) { + virtq = &priv->virtqs[index]; + if (virtq->virtq) { + pthread_mutex_lock(&virtq->virtq_lock); + mlx5_vdpa_virtq_unset(virtq); + pthread_mutex_unlock(&virtq->virtq_lock); + } + } +} + static int mlx5_vdpa_virtq_resource_prepare(struct mlx5_vdpa_priv *priv) { - uint32_t max_queues; - uint32_t index; + uint32_t remaining_cnt = 0, err_cnt = 0, task_num = 0; + uint32_t max_queues, index, thrd_idx, data[1]; struct mlx5_vdpa_virtq *virtq; for (index = 0; index < priv->caps.max_num_virtio_queues; @@ -640,25 +675,53 @@ mlx5_vdpa_virtq_resource_prepare(struct mlx5_vdpa_priv *priv) return 0; max_queues = (priv->queues < priv->caps.max_num_virtio_queues) ? (priv->queues * 2) : (priv->caps.max_num_virtio_queues); - for (index = 0; index < max_queues; ++index) - if (mlx5_vdpa_virtq_single_resource_prepare(priv, - index)) + if (priv->use_c_thread) { + uint32_t main_task_idx[max_queues]; + + for (index = 0; index < max_queues; ++index) { + thrd_idx = index % (conf_thread_mng.max_thrds + 1); + if (!thrd_idx) { + main_task_idx[task_num] = index; + task_num++; + continue; + } + thrd_idx = priv->last_c_thrd_idx + 1; + if (thrd_idx >= conf_thread_mng.max_thrds) + thrd_idx = 0; + priv->last_c_thrd_idx = thrd_idx; + data[0] = index; + if (mlx5_vdpa_task_add(priv, thrd_idx, + MLX5_VDPA_TASK_PREPARE_VIRTQ, + &remaining_cnt, &err_cnt, + (void **)&data, 1)) { + DRV_LOG(ERR, "Fail to add " + "task prepare virtq (%d).", index); + main_task_idx[task_num] = index; + task_num++; + } + } + for (index = 0; index < task_num; ++index) + if (mlx5_vdpa_virtq_single_resource_prepare(priv, + main_task_idx[index])) + goto error; + if (mlx5_vdpa_c_thread_wait_bulk_tasks_done(&remaining_cnt, + &err_cnt, 2000)) { + DRV_LOG(ERR, + "Failed to wait virt-queue prepare tasks ready."); goto error; + } + } else { + for (index = 0; index < max_queues; ++index) + if (mlx5_vdpa_virtq_single_resource_prepare(priv, + index)) + goto error; + } if (mlx5_vdpa_is_modify_virtq_supported(priv)) if (mlx5_vdpa_steer_update(priv, true)) goto error; return 0; error: - for (index = 0; index < max_queues; ++index) { - virtq = &priv->virtqs[index]; - if (virtq->virtq) { - pthread_mutex_lock(&virtq->virtq_lock); - mlx5_vdpa_virtq_unset(virtq); - pthread_mutex_unlock(&virtq->virtq_lock); - } - } - if (mlx5_vdpa_is_modify_virtq_supported(priv)) - mlx5_vdpa_steer_unset(priv); + mlx5_vdpa_prepare_virtq_destroy(priv); return -1; } @@ -860,7 +923,7 @@ static void mlx5_vdpa_dev_release(struct mlx5_vdpa_priv *priv) { if (priv->state == MLX5_VDPA_STATE_CONFIGURED) - mlx5_vdpa_dev_close(priv->vid); + _internal_mlx5_vdpa_dev_close(priv, true); if (priv->use_c_thread) mlx5_vdpa_wait_dev_close_tasks_done(priv); mlx5_vdpa_release_dev_resources(priv); diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index f353db62ac..dc4dfba5ed 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -85,6 +85,7 @@ enum mlx5_vdpa_task_type { MLX5_VDPA_TASK_SETUP_VIRTQ, MLX5_VDPA_TASK_STOP_VIRTQ, MLX5_VDPA_TASK_DEV_CLOSE_NOWAIT, + MLX5_VDPA_TASK_PREPARE_VIRTQ, }; /* Generic task information and size must be multiple of 4B. */ @@ -128,6 +129,9 @@ struct mlx5_vdpa_virtq { uint32_t configured:1; uint32_t enable:1; uint32_t stopped:1; + uint32_t rx_csum:1; + uint32_t virtio_version_1_0:1; + uint32_t event_mode:3; uint32_t version; pthread_mutex_t virtq_lock; struct mlx5_vdpa_priv *priv; @@ -355,8 +359,12 @@ void mlx5_vdpa_err_event_unset(struct mlx5_vdpa_priv *priv); * * @param[in] priv * The vdpa driver private structure. + * @param[in] release_resource + * The vdpa driver release resource without prepare resource. */ -void mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv); +void +mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv, + bool release_resource); /** * Cleanup cached resources of all virtqs. @@ -595,4 +603,6 @@ int mlx5_vdpa_qps2rst2rts(struct mlx5_vdpa_event_qp *eqp); void mlx5_vdpa_virtq_unset(struct mlx5_vdpa_virtq *virtq); +void +mlx5_vdpa_prepare_virtq_destroy(struct mlx5_vdpa_priv *priv); #endif /* RTE_PMD_MLX5_VDPA_H_ */ diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c index bb2279440b..6e6624e5a3 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c @@ -153,6 +153,7 @@ mlx5_vdpa_c_thread_handle(void *arg) __atomic_fetch_add( task.err_cnt, 1, __ATOMIC_RELAXED); } + virtq->enable = 1; pthread_mutex_unlock(&virtq->virtq_lock); break; case MLX5_VDPA_TASK_STOP_VIRTQ: @@ -193,7 +194,7 @@ mlx5_vdpa_c_thread_handle(void *arg) pthread_mutex_lock(&priv->steer_update_lock); mlx5_vdpa_steer_unset(priv); pthread_mutex_unlock(&priv->steer_update_lock); - mlx5_vdpa_virtqs_release(priv); + mlx5_vdpa_virtqs_release(priv, false); mlx5_vdpa_drain_cq(priv); if (priv->lm_mr.addr) mlx5_os_wrapped_mkey_destroy( @@ -205,6 +206,18 @@ mlx5_vdpa_c_thread_handle(void *arg) &priv->dev_close_progress, 0, __ATOMIC_RELAXED); break; + case MLX5_VDPA_TASK_PREPARE_VIRTQ: + ret = mlx5_vdpa_virtq_single_resource_prepare( + priv, task.idx); + if (ret) { + DRV_LOG(ERR, + "Failed to prepare virtq %d.", + task.idx); + __atomic_fetch_add( + task.err_cnt, 1, + __ATOMIC_RELAXED); + } + break; default: DRV_LOG(ERR, "Invalid vdpa task type %d.", task.type); diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c index 20ce382487..d4dd73f861 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c @@ -116,18 +116,29 @@ mlx5_vdpa_virtq_unreg_intr_handle_all(struct mlx5_vdpa_priv *priv) } } +static void +mlx5_vdpa_vq_destroy(struct mlx5_vdpa_virtq *virtq) +{ + /* Clean pre-created resource in dev removal only */ + claim_zero(mlx5_devx_cmd_destroy(virtq->virtq)); + virtq->index = 0; + virtq->virtq = NULL; + virtq->configured = 0; +} + /* Release cached VQ resources. */ void mlx5_vdpa_virtqs_cleanup(struct mlx5_vdpa_priv *priv) { unsigned int i, j; + mlx5_vdpa_steer_unset(priv); for (i = 0; i < priv->caps.max_num_virtio_queues; i++) { struct mlx5_vdpa_virtq *virtq = &priv->virtqs[i]; - if (virtq->index != i) - continue; pthread_mutex_lock(&virtq->virtq_lock); + if (virtq->virtq) + mlx5_vdpa_vq_destroy(virtq); for (j = 0; j < RTE_DIM(virtq->umems); ++j) { if (virtq->umems[j].obj) { claim_zero(mlx5_glue->devx_umem_dereg @@ -157,29 +168,37 @@ mlx5_vdpa_virtq_unset(struct mlx5_vdpa_virtq *virtq) if (ret) DRV_LOG(WARNING, "Failed to stop virtq %d.", virtq->index); - claim_zero(mlx5_devx_cmd_destroy(virtq->virtq)); - virtq->index = 0; - virtq->virtq = NULL; - virtq->configured = 0; } + mlx5_vdpa_vq_destroy(virtq); virtq->notifier_state = MLX5_VDPA_NOTIFIER_STATE_DISABLED; } void -mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv) +mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv, + bool release_resource) { struct mlx5_vdpa_virtq *virtq; - int i; - - for (i = 0; i < priv->nr_virtqs; i++) { + uint32_t i, max_virtq, valid_vq_num; + + valid_vq_num = ((priv->queues * 2) < priv->caps.max_num_virtio_queues) ? + (priv->queues * 2) : priv->caps.max_num_virtio_queues; + max_virtq = (release_resource && + (valid_vq_num) > priv->nr_virtqs) ? + (valid_vq_num) : priv->nr_virtqs; + for (i = 0; i < max_virtq; i++) { virtq = &priv->virtqs[i]; pthread_mutex_lock(&virtq->virtq_lock); mlx5_vdpa_virtq_unset(virtq); - if (i < (priv->queues * 2)) + virtq->enable = 0; + if (!release_resource && i < valid_vq_num) mlx5_vdpa_virtq_single_resource_prepare( priv, i); pthread_mutex_unlock(&virtq->virtq_lock); } + if (!release_resource && priv->queues && + mlx5_vdpa_is_modify_virtq_supported(priv)) + if (mlx5_vdpa_steer_update(priv, true)) + mlx5_vdpa_steer_unset(priv); priv->features = 0; priv->nr_virtqs = 0; } @@ -455,6 +474,9 @@ mlx5_vdpa_virtq_single_resource_prepare(struct mlx5_vdpa_priv *priv, virtq->priv = priv; if (!virtq->virtq) return true; + virtq->rx_csum = attr.rx_csum; + virtq->virtio_version_1_0 = attr.virtio_version_1_0; + virtq->event_mode = attr.event_mode; } return false; } @@ -538,6 +560,9 @@ mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index, bool reg_kick) goto error; } claim_zero(rte_vhost_enable_guest_notification(priv->vid, index, 1)); + virtq->rx_csum = attr.rx_csum; + virtq->virtio_version_1_0 = attr.virtio_version_1_0; + virtq->event_mode = attr.event_mode; virtq->configured = 1; rte_spinlock_lock(&priv->db_lock); rte_write32(virtq->index, priv->virtq_db_addr); @@ -629,6 +654,31 @@ mlx5_vdpa_features_validate(struct mlx5_vdpa_priv *priv) return 0; } +static bool +mlx5_vdpa_is_pre_created_vq_mismatch(struct mlx5_vdpa_priv *priv, + struct mlx5_vdpa_virtq *virtq) +{ + struct rte_vhost_vring vq; + uint32_t event_mode; + + if (virtq->rx_csum != + !!(priv->features & (1ULL << VIRTIO_NET_F_GUEST_CSUM))) + return true; + if (virtq->virtio_version_1_0 != + !!(priv->features & (1ULL << VIRTIO_F_VERSION_1))) + return true; + if (rte_vhost_get_vhost_vring(priv->vid, virtq->index, &vq)) + return true; + if (vq.size != virtq->vq_size) + return true; + event_mode = vq.callfd != -1 || !(priv->caps.event_mode & + (1 << MLX5_VIRTQ_EVENT_MODE_NO_MSIX)) ? + MLX5_VIRTQ_EVENT_MODE_QP : MLX5_VIRTQ_EVENT_MODE_NO_MSIX; + if (virtq->event_mode != event_mode) + return true; + return false; +} + int mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv) { @@ -664,6 +714,15 @@ mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv) virtq = &priv->virtqs[i]; if (!virtq->enable) continue; + if (priv->queues && virtq->virtq) { + if (mlx5_vdpa_is_pre_created_vq_mismatch(priv, virtq)) { + mlx5_vdpa_prepare_virtq_destroy(priv); + i = 0; + virtq = &priv->virtqs[i]; + if (!virtq->enable) + continue; + } + } thrd_idx = i % (conf_thread_mng.max_thrds + 1); if (!thrd_idx) { main_task_idx[task_num] = i; @@ -693,6 +752,7 @@ mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv) pthread_mutex_unlock(&virtq->virtq_lock); goto error; } + virtq->enable = 1; pthread_mutex_unlock(&virtq->virtq_lock); } if (mlx5_vdpa_c_thread_wait_bulk_tasks_done(&remaining_cnt, @@ -724,20 +784,32 @@ mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv) } else { for (i = 0; i < nr_vring; i++) { virtq = &priv->virtqs[i]; + if (!virtq->enable) + continue; + if (priv->queues && virtq->virtq) { + if (mlx5_vdpa_is_pre_created_vq_mismatch(priv, + virtq)) { + mlx5_vdpa_prepare_virtq_destroy( + priv); + i = 0; + virtq = &priv->virtqs[i]; + if (!virtq->enable) + continue; + } + } pthread_mutex_lock(&virtq->virtq_lock); - if (virtq->enable) { - if (mlx5_vdpa_virtq_setup(priv, i, true)) { - pthread_mutex_unlock( + if (mlx5_vdpa_virtq_setup(priv, i, true)) { + pthread_mutex_unlock( &virtq->virtq_lock); - goto error; - } + goto error; } + virtq->enable = 1; pthread_mutex_unlock(&virtq->virtq_lock); } } return 0; error: - mlx5_vdpa_virtqs_release(priv); + mlx5_vdpa_virtqs_release(priv, true); return -1; } @@ -795,6 +867,11 @@ mlx5_vdpa_virtq_enable(struct mlx5_vdpa_priv *priv, int index, int enable) "for virtq %d.", index); } mlx5_vdpa_virtq_unset(virtq); + } else { + if (virtq->virtq && + mlx5_vdpa_is_pre_created_vq_mismatch(priv, virtq)) + DRV_LOG(WARNING, + "Configuration mismatch dummy virtq %d.", index); } if (enable) { ret = mlx5_vdpa_virtq_setup(priv, index, true); From patchwork Mon Jun 6 11:21:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zhang X-Patchwork-Id: 112374 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EF89EA0543; Mon, 6 Jun 2022 13:25:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8075542BC3; Mon, 6 Jun 2022 13:23:17 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2079.outbound.protection.outlook.com [40.107.244.79]) by mails.dpdk.org (Postfix) with ESMTP id 1254C42BBB for ; Mon, 6 Jun 2022 13:23:16 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=O8xpzz+pRV0g5+cgeQaglTUhYNS2taOydEJ/5GKUG36snonwZJYepKbNCyN+I9rqxLTTHE+/FE/nw1OGzgeWpWSOg73ZwLZXpn7riZnfpufcGDC2K7+wPjPwcNUDtFrz4sZwoEhJ9Kyjr6cunNKw2XT4PVOCZ56VH0ouh+5bcs1cgtlC0DiFNAHx5HdYgJbRFOfBf1QV7r/utQZof/+4fVvK7pfcli30kAIa1ftxBISRP1oQc8L/e6NbRY0PeAP6W5bSERKX75IrwRj9nwL3jvmBPSsaOLsI6cAKnU9OtI2zKIG5eZhBaD9x4R3vP1l4xUBCDFHI90+iXMF/hjyXWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=XsUnvxy0pfveSZZ6jgiaSH5PTTAq7dr+MbccXrR8wgI=; b=fE6G7lLx1Xd/ATO8lA1rgw2rVAygV7yt01/QUytTq+daRi7owg1+mNVheIAwY5xKv594KgI8CMSpm/kAhJvzy+TfRjxsv+bMxk1mEA+3Sb7womXIKHZdfViJk1DAQrFW0VZ4K2R/49uisJrjJEB0zTsFRIwsnPOb6qelgC/r3KynfDDHWHOr3HDJqXMbDFxaLuNCX8VSY8LVuVBZJB1qXYpCB0+Q3GoldRhXZK+07sNZx/LlKh1VY8Lhuqr3XSKtbZz1SLu4rHG5OhnPLc577LU8nYVeNl9FS3ARZbG8k/HmBVOvtDFjPJRQkwl47nOTk/U1vZL7PLsmpq8I5Kg4Mw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XsUnvxy0pfveSZZ6jgiaSH5PTTAq7dr+MbccXrR8wgI=; b=LkppW1JQ0YNvAAs7YhnwZ+L6aPot0gtb6qr7VIH4glEooJfxqqqBKuKhsEI8Z3o+8Ie0vkilt4oMA4orVVT5SG1rAEE7rOMuIPpgDd7m3rNarpevg8pyEn1CCqtxFVR8CVSKzD1cvKndoIU0QrRmLHkZQw4R+FHy5q0D/HsKMrXKarfvN9yhghmWQZxg1TNjY2+02uzHLVjh0VtTfvwKauP0V3TavLuDOTUnHuXg68ny8isw6smcPdO4O0lzmDz6ljxWvOpw2/jqQ2gRFcj2vpIUJEMsHujZJsyeFC5LPQQEU1oBELfaFurvgZp/VN9G5R7HZr96FX1grT/jB1BF5A== Received: from BN0PR03CA0056.namprd03.prod.outlook.com (2603:10b6:408:e7::31) by DS0PR12MB6632.namprd12.prod.outlook.com (2603:10b6:8:d0::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.19; Mon, 6 Jun 2022 11:23:10 +0000 Received: from BN8NAM11FT046.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e7:cafe::8c) by BN0PR03CA0056.outlook.office365.com (2603:10b6:408:e7::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13 via Frontend Transport; Mon, 6 Jun 2022 11:23:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.236) by BN8NAM11FT046.mail.protection.outlook.com (10.13.177.127) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:23:10 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:23:09 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:23:06 -0700 From: Li Zhang To: , , , CC: , , , Subject: [PATCH v1 17/17] vdpa/mlx5: prepare virtqueue resource creation Date: Mon, 6 Jun 2022 14:21:09 +0300 Message-ID: <20220606112109.208873-33-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 071330bf-dd87-4811-6cac-08da47aeeffb X-MS-TrafficTypeDiagnostic: DS0PR12MB6632:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pyDrL+z2mKvEPNbu3GFPQnNFogVS0Sbmk5iRqdd1TXfk6Gq47NfIm9on5sHw/kzY4V9DSJmmz+Nez/PTCqTN6Rc4vIeynHhUthxkxFxMoa5Tise6JKXHAXupaCPTokShPz4Wpucsf/3uwjo3ABP9xOiRN9tLymBmJNr46HPHdK8rYMqclzqQm7u5vB7/UfEN7wXXduXK6ElgwrAWqNnkPqVThglMC07/onrCI7aY/KIHlBV41sqrr0tkSap7hAOt8Hl7UdXlUP+ZOAi0ZopW/02MbdPcTdUIGTe7xHn0uMN9Io37ZOWENHHrj6S3/Svyns+PfcoQJPwIxH8NGg/ywi//uQLAyC3MDDhl2ELhdwCwBCTUu7T1TPRTX41X1foX6KYe5qd6FuFAbwKiE7qEgAxhfCHU3rMPrDjozS1rjlctQMsaGQTEv/VXfU5E+NhPCrkyGM6qN6gtal6bT2HXL4utrzqTQyaQr3qyVv5emmKLGP7VDqK9KY58WWwYIFVXRCD6n2CC3YDB2O5bMtfwEyViubAK7PPivlOpyuLTtf881mO5SQY3qXU0CAaDHWoXn0XSXDZ7z7xzUCwy61rmxzKOdfbKMrNp4QMmVqNIsGybx8Fank1aXhXwM1HpgNMy6utT1gFnqC8lqOklRLgdayFOBOHgD5EndLKL4rmtIuewdxZV+9tANDVT5/D+ta6s4ju0fUs10I8I7v+zieNO5A== X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(30864003)(81166007)(6286002)(5660300002)(356005)(82310400005)(26005)(2616005)(36860700001)(107886003)(1076003)(86362001)(55016003)(8936002)(40460700003)(508600001)(54906003)(2906002)(6636002)(110136005)(70586007)(7696005)(316002)(70206006)(47076005)(426003)(83380400001)(8676002)(336012)(4326008)(36756003)(16526019)(186003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:23:10.0741 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 071330bf-dd87-4811-6cac-08da47aeeffb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6632 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Split the virtqs virt-queue resource between the configuration threads. Also need pre-created virt-queue resource after virtq destruction. This accelerates the LM process and reduces its time by 30%. Signed-off-by: Li Zhang --- drivers/vdpa/mlx5/mlx5_vdpa.c | 115 ++++++++++++++++++++------ drivers/vdpa/mlx5/mlx5_vdpa.h | 12 ++- drivers/vdpa/mlx5/mlx5_vdpa_cthread.c | 15 +++- drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 111 +++++++++++++++++++++---- 4 files changed, 208 insertions(+), 45 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c index f006a9cd3f..c5d82872c7 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa.c @@ -275,23 +275,18 @@ mlx5_vdpa_wait_dev_close_tasks_done(struct mlx5_vdpa_priv *priv) } static int -mlx5_vdpa_dev_close(int vid) +_internal_mlx5_vdpa_dev_close(struct mlx5_vdpa_priv *priv, + bool release_resource) { - struct rte_vdpa_device *vdev = rte_vhost_get_vdpa_device(vid); - struct mlx5_vdpa_priv *priv = - mlx5_vdpa_find_priv_resource_by_vdev(vdev); int ret = 0; + int vid = priv->vid; - if (priv == NULL) { - DRV_LOG(ERR, "Invalid vDPA device: %s.", vdev->device->name); - return -1; - } mlx5_vdpa_cqe_event_unset(priv); if (priv->state == MLX5_VDPA_STATE_CONFIGURED) { ret |= mlx5_vdpa_lm_log(priv); priv->state = MLX5_VDPA_STATE_IN_PROGRESS; } - if (priv->use_c_thread) { + if (priv->use_c_thread && !release_resource) { if (priv->last_c_thrd_idx >= (conf_thread_mng.max_thrds - 1)) priv->last_c_thrd_idx = 0; @@ -315,7 +310,7 @@ mlx5_vdpa_dev_close(int vid) pthread_mutex_lock(&priv->steer_update_lock); mlx5_vdpa_steer_unset(priv); pthread_mutex_unlock(&priv->steer_update_lock); - mlx5_vdpa_virtqs_release(priv); + mlx5_vdpa_virtqs_release(priv, release_resource); mlx5_vdpa_drain_cq(priv); if (priv->lm_mr.addr) mlx5_os_wrapped_mkey_destroy(&priv->lm_mr); @@ -329,6 +324,24 @@ mlx5_vdpa_dev_close(int vid) return ret; } +static int +mlx5_vdpa_dev_close(int vid) +{ + struct rte_vdpa_device *vdev = rte_vhost_get_vdpa_device(vid); + struct mlx5_vdpa_priv *priv; + + if (!vdev) { + DRV_LOG(ERR, "Invalid vDPA device."); + return -1; + } + priv = mlx5_vdpa_find_priv_resource_by_vdev(vdev); + if (priv == NULL) { + DRV_LOG(ERR, "Invalid vDPA device: %s.", vdev->device->name); + return -1; + } + return _internal_mlx5_vdpa_dev_close(priv, false); +} + static int mlx5_vdpa_dev_config(int vid) { @@ -624,11 +637,33 @@ mlx5_vdpa_config_get(struct mlx5_kvargs_ctrl *mkvlist, priv->queue_size); } +void +mlx5_vdpa_prepare_virtq_destroy(struct mlx5_vdpa_priv *priv) +{ + uint32_t max_queues, index; + struct mlx5_vdpa_virtq *virtq; + + if (!priv->queues || !priv->queue_size) + return; + max_queues = ((priv->queues * 2) < priv->caps.max_num_virtio_queues) ? + (priv->queues * 2) : (priv->caps.max_num_virtio_queues); + if (mlx5_vdpa_is_modify_virtq_supported(priv)) + mlx5_vdpa_steer_unset(priv); + for (index = 0; index < max_queues; ++index) { + virtq = &priv->virtqs[index]; + if (virtq->virtq) { + pthread_mutex_lock(&virtq->virtq_lock); + mlx5_vdpa_virtq_unset(virtq); + pthread_mutex_unlock(&virtq->virtq_lock); + } + } +} + static int mlx5_vdpa_virtq_resource_prepare(struct mlx5_vdpa_priv *priv) { - uint32_t max_queues; - uint32_t index; + uint32_t remaining_cnt = 0, err_cnt = 0, task_num = 0; + uint32_t max_queues, index, thrd_idx, data[1]; struct mlx5_vdpa_virtq *virtq; for (index = 0; index < priv->caps.max_num_virtio_queues; @@ -640,25 +675,53 @@ mlx5_vdpa_virtq_resource_prepare(struct mlx5_vdpa_priv *priv) return 0; max_queues = (priv->queues < priv->caps.max_num_virtio_queues) ? (priv->queues * 2) : (priv->caps.max_num_virtio_queues); - for (index = 0; index < max_queues; ++index) - if (mlx5_vdpa_virtq_single_resource_prepare(priv, - index)) + if (priv->use_c_thread) { + uint32_t main_task_idx[max_queues]; + + for (index = 0; index < max_queues; ++index) { + thrd_idx = index % (conf_thread_mng.max_thrds + 1); + if (!thrd_idx) { + main_task_idx[task_num] = index; + task_num++; + continue; + } + thrd_idx = priv->last_c_thrd_idx + 1; + if (thrd_idx >= conf_thread_mng.max_thrds) + thrd_idx = 0; + priv->last_c_thrd_idx = thrd_idx; + data[0] = index; + if (mlx5_vdpa_task_add(priv, thrd_idx, + MLX5_VDPA_TASK_PREPARE_VIRTQ, + &remaining_cnt, &err_cnt, + (void **)&data, 1)) { + DRV_LOG(ERR, "Fail to add " + "task prepare virtq (%d).", index); + main_task_idx[task_num] = index; + task_num++; + } + } + for (index = 0; index < task_num; ++index) + if (mlx5_vdpa_virtq_single_resource_prepare(priv, + main_task_idx[index])) + goto error; + if (mlx5_vdpa_c_thread_wait_bulk_tasks_done(&remaining_cnt, + &err_cnt, 2000)) { + DRV_LOG(ERR, + "Failed to wait virt-queue prepare tasks ready."); goto error; + } + } else { + for (index = 0; index < max_queues; ++index) + if (mlx5_vdpa_virtq_single_resource_prepare(priv, + index)) + goto error; + } if (mlx5_vdpa_is_modify_virtq_supported(priv)) if (mlx5_vdpa_steer_update(priv, true)) goto error; return 0; error: - for (index = 0; index < max_queues; ++index) { - virtq = &priv->virtqs[index]; - if (virtq->virtq) { - pthread_mutex_lock(&virtq->virtq_lock); - mlx5_vdpa_virtq_unset(virtq); - pthread_mutex_unlock(&virtq->virtq_lock); - } - } - if (mlx5_vdpa_is_modify_virtq_supported(priv)) - mlx5_vdpa_steer_unset(priv); + mlx5_vdpa_prepare_virtq_destroy(priv); return -1; } @@ -860,7 +923,7 @@ static void mlx5_vdpa_dev_release(struct mlx5_vdpa_priv *priv) { if (priv->state == MLX5_VDPA_STATE_CONFIGURED) - mlx5_vdpa_dev_close(priv->vid); + _internal_mlx5_vdpa_dev_close(priv, true); if (priv->use_c_thread) mlx5_vdpa_wait_dev_close_tasks_done(priv); mlx5_vdpa_release_dev_resources(priv); diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index f353db62ac..dc4dfba5ed 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -85,6 +85,7 @@ enum mlx5_vdpa_task_type { MLX5_VDPA_TASK_SETUP_VIRTQ, MLX5_VDPA_TASK_STOP_VIRTQ, MLX5_VDPA_TASK_DEV_CLOSE_NOWAIT, + MLX5_VDPA_TASK_PREPARE_VIRTQ, }; /* Generic task information and size must be multiple of 4B. */ @@ -128,6 +129,9 @@ struct mlx5_vdpa_virtq { uint32_t configured:1; uint32_t enable:1; uint32_t stopped:1; + uint32_t rx_csum:1; + uint32_t virtio_version_1_0:1; + uint32_t event_mode:3; uint32_t version; pthread_mutex_t virtq_lock; struct mlx5_vdpa_priv *priv; @@ -355,8 +359,12 @@ void mlx5_vdpa_err_event_unset(struct mlx5_vdpa_priv *priv); * * @param[in] priv * The vdpa driver private structure. + * @param[in] release_resource + * The vdpa driver release resource without prepare resource. */ -void mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv); +void +mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv, + bool release_resource); /** * Cleanup cached resources of all virtqs. @@ -595,4 +603,6 @@ int mlx5_vdpa_qps2rst2rts(struct mlx5_vdpa_event_qp *eqp); void mlx5_vdpa_virtq_unset(struct mlx5_vdpa_virtq *virtq); +void +mlx5_vdpa_prepare_virtq_destroy(struct mlx5_vdpa_priv *priv); #endif /* RTE_PMD_MLX5_VDPA_H_ */ diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c index bb2279440b..6e6624e5a3 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c @@ -153,6 +153,7 @@ mlx5_vdpa_c_thread_handle(void *arg) __atomic_fetch_add( task.err_cnt, 1, __ATOMIC_RELAXED); } + virtq->enable = 1; pthread_mutex_unlock(&virtq->virtq_lock); break; case MLX5_VDPA_TASK_STOP_VIRTQ: @@ -193,7 +194,7 @@ mlx5_vdpa_c_thread_handle(void *arg) pthread_mutex_lock(&priv->steer_update_lock); mlx5_vdpa_steer_unset(priv); pthread_mutex_unlock(&priv->steer_update_lock); - mlx5_vdpa_virtqs_release(priv); + mlx5_vdpa_virtqs_release(priv, false); mlx5_vdpa_drain_cq(priv); if (priv->lm_mr.addr) mlx5_os_wrapped_mkey_destroy( @@ -205,6 +206,18 @@ mlx5_vdpa_c_thread_handle(void *arg) &priv->dev_close_progress, 0, __ATOMIC_RELAXED); break; + case MLX5_VDPA_TASK_PREPARE_VIRTQ: + ret = mlx5_vdpa_virtq_single_resource_prepare( + priv, task.idx); + if (ret) { + DRV_LOG(ERR, + "Failed to prepare virtq %d.", + task.idx); + __atomic_fetch_add( + task.err_cnt, 1, + __ATOMIC_RELAXED); + } + break; default: DRV_LOG(ERR, "Invalid vdpa task type %d.", task.type); diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c index 20ce382487..d4dd73f861 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c @@ -116,18 +116,29 @@ mlx5_vdpa_virtq_unreg_intr_handle_all(struct mlx5_vdpa_priv *priv) } } +static void +mlx5_vdpa_vq_destroy(struct mlx5_vdpa_virtq *virtq) +{ + /* Clean pre-created resource in dev removal only */ + claim_zero(mlx5_devx_cmd_destroy(virtq->virtq)); + virtq->index = 0; + virtq->virtq = NULL; + virtq->configured = 0; +} + /* Release cached VQ resources. */ void mlx5_vdpa_virtqs_cleanup(struct mlx5_vdpa_priv *priv) { unsigned int i, j; + mlx5_vdpa_steer_unset(priv); for (i = 0; i < priv->caps.max_num_virtio_queues; i++) { struct mlx5_vdpa_virtq *virtq = &priv->virtqs[i]; - if (virtq->index != i) - continue; pthread_mutex_lock(&virtq->virtq_lock); + if (virtq->virtq) + mlx5_vdpa_vq_destroy(virtq); for (j = 0; j < RTE_DIM(virtq->umems); ++j) { if (virtq->umems[j].obj) { claim_zero(mlx5_glue->devx_umem_dereg @@ -157,29 +168,37 @@ mlx5_vdpa_virtq_unset(struct mlx5_vdpa_virtq *virtq) if (ret) DRV_LOG(WARNING, "Failed to stop virtq %d.", virtq->index); - claim_zero(mlx5_devx_cmd_destroy(virtq->virtq)); - virtq->index = 0; - virtq->virtq = NULL; - virtq->configured = 0; } + mlx5_vdpa_vq_destroy(virtq); virtq->notifier_state = MLX5_VDPA_NOTIFIER_STATE_DISABLED; } void -mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv) +mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv, + bool release_resource) { struct mlx5_vdpa_virtq *virtq; - int i; - - for (i = 0; i < priv->nr_virtqs; i++) { + uint32_t i, max_virtq, valid_vq_num; + + valid_vq_num = ((priv->queues * 2) < priv->caps.max_num_virtio_queues) ? + (priv->queues * 2) : priv->caps.max_num_virtio_queues; + max_virtq = (release_resource && + (valid_vq_num) > priv->nr_virtqs) ? + (valid_vq_num) : priv->nr_virtqs; + for (i = 0; i < max_virtq; i++) { virtq = &priv->virtqs[i]; pthread_mutex_lock(&virtq->virtq_lock); mlx5_vdpa_virtq_unset(virtq); - if (i < (priv->queues * 2)) + virtq->enable = 0; + if (!release_resource && i < valid_vq_num) mlx5_vdpa_virtq_single_resource_prepare( priv, i); pthread_mutex_unlock(&virtq->virtq_lock); } + if (!release_resource && priv->queues && + mlx5_vdpa_is_modify_virtq_supported(priv)) + if (mlx5_vdpa_steer_update(priv, true)) + mlx5_vdpa_steer_unset(priv); priv->features = 0; priv->nr_virtqs = 0; } @@ -455,6 +474,9 @@ mlx5_vdpa_virtq_single_resource_prepare(struct mlx5_vdpa_priv *priv, virtq->priv = priv; if (!virtq->virtq) return true; + virtq->rx_csum = attr.rx_csum; + virtq->virtio_version_1_0 = attr.virtio_version_1_0; + virtq->event_mode = attr.event_mode; } return false; } @@ -538,6 +560,9 @@ mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index, bool reg_kick) goto error; } claim_zero(rte_vhost_enable_guest_notification(priv->vid, index, 1)); + virtq->rx_csum = attr.rx_csum; + virtq->virtio_version_1_0 = attr.virtio_version_1_0; + virtq->event_mode = attr.event_mode; virtq->configured = 1; rte_spinlock_lock(&priv->db_lock); rte_write32(virtq->index, priv->virtq_db_addr); @@ -629,6 +654,31 @@ mlx5_vdpa_features_validate(struct mlx5_vdpa_priv *priv) return 0; } +static bool +mlx5_vdpa_is_pre_created_vq_mismatch(struct mlx5_vdpa_priv *priv, + struct mlx5_vdpa_virtq *virtq) +{ + struct rte_vhost_vring vq; + uint32_t event_mode; + + if (virtq->rx_csum != + !!(priv->features & (1ULL << VIRTIO_NET_F_GUEST_CSUM))) + return true; + if (virtq->virtio_version_1_0 != + !!(priv->features & (1ULL << VIRTIO_F_VERSION_1))) + return true; + if (rte_vhost_get_vhost_vring(priv->vid, virtq->index, &vq)) + return true; + if (vq.size != virtq->vq_size) + return true; + event_mode = vq.callfd != -1 || !(priv->caps.event_mode & + (1 << MLX5_VIRTQ_EVENT_MODE_NO_MSIX)) ? + MLX5_VIRTQ_EVENT_MODE_QP : MLX5_VIRTQ_EVENT_MODE_NO_MSIX; + if (virtq->event_mode != event_mode) + return true; + return false; +} + int mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv) { @@ -664,6 +714,15 @@ mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv) virtq = &priv->virtqs[i]; if (!virtq->enable) continue; + if (priv->queues && virtq->virtq) { + if (mlx5_vdpa_is_pre_created_vq_mismatch(priv, virtq)) { + mlx5_vdpa_prepare_virtq_destroy(priv); + i = 0; + virtq = &priv->virtqs[i]; + if (!virtq->enable) + continue; + } + } thrd_idx = i % (conf_thread_mng.max_thrds + 1); if (!thrd_idx) { main_task_idx[task_num] = i; @@ -693,6 +752,7 @@ mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv) pthread_mutex_unlock(&virtq->virtq_lock); goto error; } + virtq->enable = 1; pthread_mutex_unlock(&virtq->virtq_lock); } if (mlx5_vdpa_c_thread_wait_bulk_tasks_done(&remaining_cnt, @@ -724,20 +784,32 @@ mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv) } else { for (i = 0; i < nr_vring; i++) { virtq = &priv->virtqs[i]; + if (!virtq->enable) + continue; + if (priv->queues && virtq->virtq) { + if (mlx5_vdpa_is_pre_created_vq_mismatch(priv, + virtq)) { + mlx5_vdpa_prepare_virtq_destroy( + priv); + i = 0; + virtq = &priv->virtqs[i]; + if (!virtq->enable) + continue; + } + } pthread_mutex_lock(&virtq->virtq_lock); - if (virtq->enable) { - if (mlx5_vdpa_virtq_setup(priv, i, true)) { - pthread_mutex_unlock( + if (mlx5_vdpa_virtq_setup(priv, i, true)) { + pthread_mutex_unlock( &virtq->virtq_lock); - goto error; - } + goto error; } + virtq->enable = 1; pthread_mutex_unlock(&virtq->virtq_lock); } } return 0; error: - mlx5_vdpa_virtqs_release(priv); + mlx5_vdpa_virtqs_release(priv, true); return -1; } @@ -795,6 +867,11 @@ mlx5_vdpa_virtq_enable(struct mlx5_vdpa_priv *priv, int index, int enable) "for virtq %d.", index); } mlx5_vdpa_virtq_unset(virtq); + } else { + if (virtq->virtq && + mlx5_vdpa_is_pre_created_vq_mismatch(priv, virtq)) + DRV_LOG(WARNING, + "Configuration mismatch dummy virtq %d.", index); } if (enable) { ret = mlx5_vdpa_virtq_setup(priv, index, true);