From patchwork Mon Jun 20 07:55:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113087 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1C789A0545; Mon, 20 Jun 2022 09:47:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1CE5D427EB; Mon, 20 Jun 2022 09:47:06 +0200 (CEST) Received: from smtpbg511.qq.com (smtpbg511.qq.com [203.205.250.109]) by mails.dpdk.org (Postfix) with ESMTP id 962DA427EB for ; Mon, 20 Jun 2022 09:47:02 +0200 (CEST) X-QQ-mid: bizesmtp72t1655711216tgophcsm Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 20 Jun 2022 15:46:56 +0800 (CST) X-QQ-SSF: 01400000002000F0P000B00A0000000 X-QQ-FEAT: F3yR32iATbipYq8mhcmWxLcnLngExH1GFp7WAPxotDo5JKlyjYk59S3MF9ioI 73lCOjCQB+xr0zN4pl36y6D+HiMr2JlCrG7VQ4FJ+SH78YIZnC+wf9cLif6txLvEmFCslRl mAd+GMcPAtya7rXaZi011xpg1bCCq3QBv2dYI5aDMFI4OyzFkHG+o/b2vFRWsWhPjBSUOZl RWtT3VSSG6QlTk65KdIYjas7X1yqjIURjRxWjH+XdNJULU0/yk3YjLq5CIA/XKdPIH6oNyC quY/mkKSUR4tD2y6iyn3MfGk59C0uGih9kd7MKu1zLU2/wNDu/JZgcwVygfQd2ED+wg2a1L Vg7fkRwyIeZLCoM9zM= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH 1/7] net/txgbe: support OEM subsystem vendor ID Date: Mon, 20 Jun 2022 15:55:06 +0800 Message-Id: <20220620075512.588744-2-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220620075512.588744-1-jiawenwu@trustnetic.com> References: <20220620075512.588744-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign3 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for OEM subsystem vendor ID. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_22_07.rst | 4 +++ drivers/net/txgbe/base/txgbe_hw.c | 37 ++++++++++++++++++++++++++ drivers/net/txgbe/base/txgbe_hw.h | 2 ++ drivers/net/txgbe/txgbe_ethdev.c | 12 +++++++++ 4 files changed, 55 insertions(+) diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 6fc044edaa..96db85a707 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -167,6 +167,10 @@ New Features * Added support for yt8531s PHY. +* **Updated Wangxun txgbe driver.** + + * Added support for OEM subsystem vendor ID. + * **Added Elliptic Curve Diffie-Hellman (ECDH) algorithm in cryptodev.** Added support for Elliptic Curve Diffie Hellman (ECDH) asymmetric diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 6a045cba79..8acebf8b60 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -2608,6 +2608,43 @@ s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 autoc) return err; } +/* cmd_addr is used for some special command: + * 1. to be sector address, when implemented erase sector command + * 2. to be flash address when implemented read, write flash address + */ +u32 txgbe_fmgr_cmd_op(struct txgbe_hw *hw, u32 cmd, u32 cmd_addr) +{ + u32 cmd_val = 0; + u32 i = 0; + + cmd_val = TXGBE_SPICMD_CMD(cmd) | TXGBE_SPICMD_CLK(3) | cmd_addr; + wr32(hw, TXGBE_SPICMD, cmd_val); + + for (i = 0; i < 10000; i++) { + if (rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_OPDONE) + break; + + usec_delay(10); + } + if (i == 10000) + return 1; + + return 0; +} + +u32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr) +{ + u32 status = 0; + + status = txgbe_fmgr_cmd_op(hw, 1, addr); + if (status) { + DEBUGOUT("Read flash timeout."); + return status; + } + + return rd32(hw, TXGBE_SPIDAT); +} + /** * txgbe_init_ops_pf - Inits func ptrs and MAC type * @hw: pointer to hardware structure diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h index fd2f7d784c..7031589f7c 100644 --- a/drivers/net/txgbe/base/txgbe_hw.h +++ b/drivers/net/txgbe/base/txgbe_hw.h @@ -111,4 +111,6 @@ s32 txgbe_prot_autoc_read_raptor(struct txgbe_hw *hw, bool *locked, u64 *value); s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 value); s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw); bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw); +u32 txgbe_fmgr_cmd_op(struct txgbe_hw *hw, u32 cmd, u32 cmd_addr); +u32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr); #endif /* _TXGBE_HW_H_ */ diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index f0994f028d..6fb91cdf07 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -552,6 +552,7 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) const struct rte_memzone *mz; uint32_t ctrl_ext; uint16_t csum; + u32 ssid = 0; int err, i, ret; PMD_INIT_FUNC_TRACE(); @@ -594,6 +595,17 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) /* Vendor and Device ID need to be set before init of shared code */ hw->device_id = pci_dev->id.device_id; hw->vendor_id = pci_dev->id.vendor_id; + if (pci_dev->id.subsystem_vendor_id == PCI_VENDOR_ID_WANGXUN) { + hw->subsystem_device_id = pci_dev->id.subsystem_device_id; + } else { + ssid = txgbe_flash_read_dword(hw, 0xFFFDC); + if (ssid == 0x1) { + PMD_INIT_LOG(ERR, + "Read of internal subsystem device id failed\n"); + return -ENODEV; + } + hw->subsystem_device_id = (u16)ssid >> 8 | (u16)ssid << 8; + } hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; hw->allow_unsupported_sfp = 1; From patchwork Mon Jun 20 07:55:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113088 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3DAC8A0545; Mon, 20 Jun 2022 09:47:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1957C427F7; Mon, 20 Jun 2022 09:47:07 +0200 (CEST) Received: from smtpbg156.qq.com (smtpbg156.qq.com [15.184.82.18]) by mails.dpdk.org (Postfix) with ESMTP id 184AE40150 for ; Mon, 20 Jun 2022 09:47:04 +0200 (CEST) X-QQ-mid: bizesmtp72t1655711219t4znu5sh Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 20 Jun 2022 15:46:59 +0800 (CST) X-QQ-SSF: 01400000002000F0P000B00A0000000 X-QQ-FEAT: 3uawQE1sH+3yErTkBMlLPSvXYRvpDbwnHHFJYcfikCBXe1/BFa1qJJk4QQml/ QBh8hJBF+fioSSAhHYc6Gl5GaT+1MVTPonyqzw+Fz43WSnH/PILY7Bo+gauQT+b+Sqn6mrF tr0NhPK0LXLaD65Vq/DRh0LZaTBJCa+lpcBWq5GAYbma/tbUYPqB8k2YSh0PIBQirRlqyRt sZ0wUGfHLg4AsDXHJwIQnZcdkkUPTbT5o47Aj9PFvirvzzxRA8zA8e4vG/ZYzCB0rhc2F9l DpfjtQNkYHLLqY2T0F5KLYklxsHeM4VOhP1liP5JeewnM2BAxvuFgyYTpyYkxEVcKrxzHK2 +Ouk9barDobki3P0kY= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH 2/7] net/ngbe: support OEM subsystem vendor ID Date: Mon, 20 Jun 2022 15:55:07 +0800 Message-Id: <20220620075512.588744-3-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220620075512.588744-1-jiawenwu@trustnetic.com> References: <20220620075512.588744-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign4 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for OEM subsystem vendor ID. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_22_07.rst | 1 + drivers/net/ngbe/ngbe_ethdev.c | 13 ++++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 96db85a707..b26efb8719 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -166,6 +166,7 @@ New Features * **Updated Wangxun ngbe driver.** * Added support for yt8531s PHY. + * Added support for OEM subsystem vendor ID. * **Updated Wangxun txgbe driver.** diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index 5ac1c27a58..c4216f7e34 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -315,6 +315,7 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) const struct rte_memzone *mz; uint32_t ctrl_ext; u32 led_conf = 0; + u32 ssid = 0; int err, ret; PMD_INIT_FUNC_TRACE(); @@ -359,7 +360,17 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) hw->back = pci_dev; hw->device_id = pci_dev->id.device_id; hw->vendor_id = pci_dev->id.vendor_id; - hw->sub_system_id = pci_dev->id.subsystem_device_id; + if (pci_dev->id.subsystem_vendor_id == PCI_VENDOR_ID_WANGXUN) { + hw->sub_system_id = pci_dev->id.subsystem_device_id; + } else { + ssid = ngbe_flash_read_dword(hw, 0xFFFDC); + if (ssid == 0x1) { + PMD_INIT_LOG(ERR, + "Read of internal subsystem device id failed\n"); + return -ENODEV; + } + hw->sub_system_id = (u16)ssid >> 8 | (u16)ssid << 8; + } ngbe_map_device_id(hw); hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; From patchwork Mon Jun 20 07:55:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113090 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0D9E8A0545; Mon, 20 Jun 2022 09:47:25 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BFBA84282C; Mon, 20 Jun 2022 09:47:18 +0200 (CEST) Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by mails.dpdk.org (Postfix) with ESMTP id C60124282C for ; Mon, 20 Jun 2022 09:47:16 +0200 (CEST) X-QQ-mid: bizesmtp72t1655711222tbap07kv Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 20 Jun 2022 15:47:02 +0800 (CST) X-QQ-SSF: 01400000002000F0P000B00A0000000 X-QQ-FEAT: 4dZ4olfoUCtPMKZdXa+bpqXeWTuyFKCuskMHeoNQHpoB6JDi/F/vRkT0mDVM4 IOONuNHLGiJ59RxjOxFsmN3TIWTzz9lmXmEor8S/9/jIc+qll4wV1SQuD2J+SFXAOce/Wa+ rEoToQu6ByKxIGeUk6dSROJnwBcI3AUKcKPRHYWsPLD488YcY4RaEpLqTN2r1uegTQCXpAW B3dca+9PQx7f0BU+U02W7DJm/4mPsDC/+Sk5OlvV/7P5LRyQQUkkU1A7JSW2FgImnO26mV2 jrMozWLhLqJzZ5vo2OjJIodn3zDUQBHPHNF510E+t6JwVs16rQFCGvNJJzgc54dzVG1me06 5OGmzRA X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH 3/7] net/txgbe: fix register polling Date: Mon, 20 Jun 2022 15:55:08 +0800 Message-Id: <20220620075512.588744-4-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220620075512.588744-1-jiawenwu@trustnetic.com> References: <20220620075512.588744-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign3 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix to poll some specific registers, which expect bit 0. Fixes: 24a4c76aff4d ("net/txgbe: add error types and registers") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_regs.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 3139796911..911bb6e04e 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1864,8 +1864,13 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, } do { - all |= rd32(hw, reg); - value |= mask & all; + if (expect != 0) { + all |= rd32(hw, reg); + value |= mask & all; + } else { + all = rd32(hw, reg); + value = mask & all; + } if (value == expect) break; @@ -1898,7 +1903,7 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, #define wr32w(hw, reg, val, mask, slice) do { \ wr32((hw), reg, val); \ - po32m((hw), reg, mask, mask, NULL, 5, slice); \ + po32m((hw), reg, mask, 0, NULL, 5, slice); \ } while (0) #define TXGBE_XPCS_IDAADDR 0x13000 From patchwork Mon Jun 20 07:55:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113089 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6F89FA0545; Mon, 20 Jun 2022 09:47:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A0D5142823; Mon, 20 Jun 2022 09:47:16 +0200 (CEST) Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by mails.dpdk.org (Postfix) with ESMTP id 0D2654280E for ; Mon, 20 Jun 2022 09:47:15 +0200 (CEST) X-QQ-mid: bizesmtp72t1655711225tzso4zup Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 20 Jun 2022 15:47:05 +0800 (CST) X-QQ-SSF: 01400000002000F0P000B00A0000000 X-QQ-FEAT: q6FcPYdgG0jfM5cEDZ1HHhmRsI9UgNTYjfkZdCh08gRYS280Zb88FbLwpEoDv /gjjTaka6y1eJ3Bbms8eyNakCd2PEU7JeSw3820cZ7HtvlUo746aXMx8CBpMZs0xBniR/bL adhgL1FkPncjh7Sd8ZbS01BlQaMQeL3mUSNbapshVMc5MzY6W/Dz4gS1dgmpBvFbPiCkq5c eHN3wFG+2nQZRCkK+++Bt9IlFeOOKGZsVXN0I+HEvhkDfCKGQNhvYjfj8e0ALBBfdDpHRx7 D9Xr9Ko/26rW+xL4qfsN+mcEwxR14pDaokwy9MjcguYfCQz2muaFPvWR2Pijlyt3lvftQJT q5itzfAXpcwXf/L4Ds= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH 4/7] net/ngbe: add more packet statistics Date: Mon, 20 Jun 2022 15:55:09 +0800 Message-Id: <20220620075512.588744-5-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220620075512.588744-1-jiawenwu@trustnetic.com> References: <20220620075512.588744-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign10 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add more hardware extended statistics. Fixes: 8b433d04adc9 ("net/ngbe: support device xstats") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/ngbe_ethdev.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index c4216f7e34..33a2f335e1 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -164,6 +164,8 @@ static const struct rte_ngbe_xstats_name_off rte_ngbe_stats_strings[] = { HW_XSTAT(rx_management_packets), HW_XSTAT(tx_management_packets), HW_XSTAT(rx_management_dropped), + HW_XSTAT(rx_dma_drop), + HW_XSTAT(tx_secdrp_packets), /* Basic Error */ HW_XSTAT(rx_crc_errors), @@ -179,6 +181,12 @@ static const struct rte_ngbe_xstats_name_off rte_ngbe_stats_strings[] = { HW_XSTAT(mac_local_errors), HW_XSTAT(mac_remote_errors), + /* PB Stats */ + HW_XSTAT(rx_up_dropped), + HW_XSTAT(rdb_pkt_cnt), + HW_XSTAT(rdb_repli_cnt), + HW_XSTAT(rdb_drp_cnt), + /* MACSEC */ HW_XSTAT(tx_macsec_pkts_untagged), HW_XSTAT(tx_macsec_pkts_encrypted), From patchwork Mon Jun 20 07:55:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113092 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C5FE1A0545; Mon, 20 Jun 2022 09:47:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0F62642B70; Mon, 20 Jun 2022 09:47:23 +0200 (CEST) Received: from smtpbgau1.qq.com. (smtpbgau1.qq.com [54.206.16.166]) by mails.dpdk.org (Postfix) with ESMTP id D97C24282D for ; Mon, 20 Jun 2022 09:47:18 +0200 (CEST) X-QQ-mid: bizesmtp72t1655711229t7v5y9kj Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 20 Jun 2022 15:47:08 +0800 (CST) X-QQ-SSF: 01400000002000F0P000B00A0000000 X-QQ-FEAT: rCzLTtzQ0gcM0i6O49HQ+wc2gvdSalW5Fud34GZgfrFKQx/89PpjUWPhOIcwI zkcDSps17ZGOp1Ca822kug89+4+spLCip3JVZKUSLmzqgF4CIFCmh3u562swD6+Kpip8uLl uZRC6mHOh0e+J7x6UTm2AQVICLSJSI0pyyygEnDMQJvRs8DZnBYjZY0L8u8lqJCr0uiLL9O sEg0MyFLPVJGW7SK2YFZAeY+sDT9ga+cOwIib2orx3GBWKukC3wS8Smusrp02PS2p0lwqVh VxkMLdIzAoDtiEQvGe642lVX6qpgAREgR/oN/UxVemjVSASF498MI1s7mDvsihHrzMalodV a+zQYAlWHi/8wgbtFc= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH 5/7] net/ngbe: fix YT PHY UTP mode to link up Date: Mon, 20 Jun 2022 15:55:10 +0800 Message-Id: <20220620075512.588744-6-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220620075512.588744-1-jiawenwu@trustnetic.com> References: <20220620075512.588744-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign10 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix to read and write the correct register fields for yt8521s and yt8531s PHY, since mode check was added. Fixes: 1c44384fce76 ("net/ngbe: support custom PHY interfaces") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/base/ngbe_phy_yt.c | 42 ++++++++++++++--------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c index f46121b8d1..9dd2b2264f 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.c +++ b/drivers/net/ngbe/base/ngbe_phy_yt.c @@ -146,21 +146,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } /* duplex full */ value |= YT_BCR_DUPLEX | YT_BCR_RESET; - hw->phy.write_reg(hw, YT_BCR, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); goto skip_an; } /*disable 100/10base-T Self-negotiation ability*/ - hw->phy.read_reg(hw, YT_ANA, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF | YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF); - hw->phy.write_reg(hw, YT_ANA, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value); /*disable 1000base-T Self-negotiation ability*/ - hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value); value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF); - hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value); if (speed & NGBE_LINK_SPEED_1GB_FULL) { hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; @@ -176,19 +176,19 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } /* enable 1000base-T Self-negotiation ability */ - hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value); value |= value_r9; - hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value); /* enable 100/10base-T Self-negotiation ability */ - hw->phy.read_reg(hw, YT_ANA, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value |= value_r4; - hw->phy.write_reg(hw, YT_ANA, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value); /* software reset to make the above configuration take effect*/ - hw->phy.read_reg(hw, YT_BCR, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value); value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN; - hw->phy.write_reg(hw, YT_BCR, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); skip_an: hw->phy.set_phy_power(hw, true); } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) { @@ -219,15 +219,15 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } else { /* utp up */ /*disable 100/10base-T Self-negotiation ability*/ - hw->phy.read_reg(hw, YT_ANA, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF | YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF); - hw->phy.write_reg(hw, YT_ANA, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value); /*disable 1000base-T Self-negotiation ability*/ - hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value); value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF); - hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value); if (speed & NGBE_LINK_SPEED_1GB_FULL) { hw->phy.autoneg_advertised |= @@ -246,21 +246,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } /* enable 1000base-T Self-negotiation ability */ - hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value); value |= value_r9; - hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value); /* enable 100/10base-T Self-negotiation ability */ - hw->phy.read_reg(hw, YT_ANA, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value |= value_r4; - hw->phy.write_reg(hw, YT_ANA, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value); /* software reset to make the above configuration * take effect */ - hw->phy.read_reg(hw, YT_BCR, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value); value |= YT_BCR_RESET; - hw->phy.write_reg(hw, YT_BCR, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); } } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(4)) { hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; From patchwork Mon Jun 20 07:55:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113093 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8287CA0545; Mon, 20 Jun 2022 09:47:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F099842B73; Mon, 20 Jun 2022 09:47:23 +0200 (CEST) Received: from smtpproxy21.qq.com (smtpbg703.qq.com [203.205.195.89]) by mails.dpdk.org (Postfix) with ESMTP id 9A0AD42847 for ; Mon, 20 Jun 2022 09:47:19 +0200 (CEST) X-QQ-mid: bizesmtp72t1655711231t7mkwn3z Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 20 Jun 2022 15:47:10 +0800 (CST) X-QQ-SSF: 01400000002000F0P000B00A0000000 X-QQ-FEAT: QR3/Kz8aADM+JDZkz4ARusEQDGQ7EILIjk13CsAsLz7CwBciuWtXBV0CO3XbE i9cDL14IuvCDrP/PrEn83JG9miFSfrhmr3egjTmDtTa+uAdV/8iTelkrrz+0VfmyN8IF6cD eqDFDeeswPexf3m7bvR5puLr9QIg3NxWH1k8ix3Eo3tkem7AoGibdMpWZhM3r9yKtB1YOhR TNW+AKGdrGcJVt1JVMdN62SUHclQqCWFF+Ube8Nn6lPrCZALShMPzTGO9PiWfUkfwd+Ek39 bjNwgqzfw6gni0YI8Fws8QRi1UVA7bjDZlRkTODxseVA7GB9yiQJ/pOmeK1hKYq5c93dory +02Y/CwDhtDLf495CZoIX8P4eR4qg== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH 6/7] net/ngbe: support autoneg on/off for external PHY SFI mode Date: Mon, 20 Jun 2022 15:55:11 +0800 Message-Id: <20220620075512.588744-7-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220620075512.588744-1-jiawenwu@trustnetic.com> References: <20220620075512.588744-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign9 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for external PHY to switch autoneg on/off on their SFI mode. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_22_07.rst | 1 + drivers/net/ngbe/base/ngbe_phy_mvl.c | 16 +++++++++++++--- drivers/net/ngbe/base/ngbe_phy_yt.c | 20 +++++++++++++++++++- drivers/net/ngbe/base/ngbe_phy_yt.h | 5 +++++ 4 files changed, 38 insertions(+), 4 deletions(-) diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index b26efb8719..a84c5b486b 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -167,6 +167,7 @@ New Features * Added support for yt8531s PHY. * Added support for OEM subsystem vendor ID. + * Added autoneg on/off for external PHY SFI mode. * **Updated Wangxun txgbe driver.** diff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.c b/drivers/net/ngbe/base/ngbe_phy_mvl.c index c5256359ed..8746a72eb3 100644 --- a/drivers/net/ngbe/base/ngbe_phy_mvl.c +++ b/drivers/net/ngbe/base/ngbe_phy_mvl.c @@ -203,6 +203,10 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed, MVL_PHY_1000BASET_HALF); value_r9 |= value; hw->phy.write_reg(hw, MVL_PHY_1000BASET, 0, value_r9); + + value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE | + MVL_CTRL_RESET | MVL_CTRL_DUPLEX; + ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value); } else { hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; @@ -210,10 +214,16 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed, value &= ~(MVL_PHY_1000BASEX_HALF | MVL_PHY_1000BASEX_FULL); value |= MVL_PHY_1000BASEX_FULL; hw->phy.write_reg(hw, MVL_ANA, 0, value); - } - value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE | MVL_CTRL_RESET; - ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value); + if (hw->mac.autoneg) + value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE | + MVL_CTRL_RESET | MVL_CTRL_DUPLEX | + MVL_CTRL_SPEED_SELECT1; + else + value = MVL_CTRL_RESET | MVL_CTRL_DUPLEX | + MVL_CTRL_SPEED_SELECT1; + ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value); + } skip_an: hw->phy.set_phy_power(hw, true); diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c index 9dd2b2264f..bc1921e68a 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.c +++ b/drivers/net/ngbe/base/ngbe_phy_yt.c @@ -205,8 +205,26 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, YT_CHIP_SW_RST; ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value); + ngbe_read_phy_reg_sds_ext_yt(hw, YT_AUTO, 0, &value); + value &= ~YT_AUTO_SENSING; + ngbe_write_phy_reg_sds_ext_yt(hw, YT_AUTO, 0, value); + + ngbe_read_phy_reg_ext_yt(hw, YT_MISC, 0, &value); + value |= YT_MISC_RESV; + ngbe_write_phy_reg_ext_yt(hw, YT_MISC, 0, value); + + ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value); + value &= ~YT_CHIP_SW_RST; + ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value); + /* software reset */ - ngbe_write_phy_reg_sds_ext_yt(hw, 0x0, 0, 0x9140); + if (hw->mac.autoneg) + value = YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN | + YT_BCR_DUPLEX | YT_BCR_SPEED_SELECT1; + else + value = YT_BCR_RESET | YT_BCR_DUPLEX | + YT_BCR_SPEED_SELECT1; + hw->phy.write_reg(hw, YT_BCR, 0, value); hw->phy.set_phy_power(hw, true); } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(2)) { diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.h b/drivers/net/ngbe/base/ngbe_phy_yt.h index 06e8f77261..ddf992e79a 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.h +++ b/drivers/net/ngbe/base/ngbe_phy_yt.h @@ -31,6 +31,11 @@ #define YT_RGMII_CONF2_LINKUP MS16(4, 0x1) #define YT_MISC 0xA006 #define YT_MISC_FIBER_PRIO MS16(8, 0x1) /* 0 for UTP */ +#define YT_MISC_RESV MS16(0, 0x1) + +/* SDS EXT */ +#define YT_AUTO 0xA5 +#define YT_AUTO_SENSING MS16(15, 0x1) /* MII common registers in UTP and SDS */ #define YT_BCR 0x0 From patchwork Mon Jun 20 07:55:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113091 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B43DAA0545; Mon, 20 Jun 2022 09:47:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0400E4281C; Mon, 20 Jun 2022 09:47:22 +0200 (CEST) Received: from smtpbguseast2.qq.com. (smtpbguseast2.qq.com [54.204.34.130]) by mails.dpdk.org (Postfix) with ESMTP id 03DDB4281B for ; Mon, 20 Jun 2022 09:47:17 +0200 (CEST) X-QQ-mid: bizesmtp72t1655711233tivrbfym Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 20 Jun 2022 15:47:13 +0800 (CST) X-QQ-SSF: 01400000002000F0P000B00A0000000 X-QQ-FEAT: Y/4E1fKPEOpwyqfWTPdG+tvUXHJ6rRp0N1+BhxDM+3K8YbdYuU9MTjbFsJFPo pyzoPb6FoWEgaId3xyfZ5LDq/NoPF2sHVhIGDAb83O2eXNK1aWX8RwzEE37zUElFqUr1gAn 8exwTB/hIA/Svs/hjaQLv8ujpTsnWbt3QK6otb1f6qA7xFYpMfv6CwKg8qDe2imw+x1e1vq X3zWtGGGV5F12FUvAle2kIa4GSeh4rK7IkVUOUgtVFchg7cdbKdNtLGtf9uphM7n63Oy+x+ hEt13BnccS+YPzraoz3ougM+uFSj1fHS52xcaKY2a6cTfPFpDVTtNmKvofSMtp2txmiSxzk aLHofrM676qWeqozktFkQMNvgGlFQ== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH 7/7] net/ngbe: support YT PHY SGMII to RGMII mode Date: Mon, 20 Jun 2022 15:55:12 +0800 Message-Id: <20220620075512.588744-8-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220620075512.588744-1-jiawenwu@trustnetic.com> References: <20220620075512.588744-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign10 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add SGMII to RGMII mode for yt8521s and yt8531s PHY. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_22_07.rst | 1 + drivers/net/ngbe/base/ngbe_phy_yt.c | 49 ++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index a84c5b486b..6baa63e3bf 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -168,6 +168,7 @@ New Features * Added support for yt8531s PHY. * Added support for OEM subsystem vendor ID. * Added autoneg on/off for external PHY SFI mode. + * Added support for yt8521s/yt8531s PHY SGMII to RGMII mode. * **Updated Wangxun txgbe driver.** diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c index bc1921e68a..562a0dede5 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.c +++ b/drivers/net/ngbe/base/ngbe_phy_yt.c @@ -298,6 +298,55 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, value &= ~YT_SMI_PHY_SW_RST; ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value); + hw->phy.set_phy_power(hw, true); + } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(5)) { + /* sgmii_to_rgmii */ + if (!hw->mac.autoneg) { + switch (speed) { + case NGBE_LINK_SPEED_1GB_FULL: + value = YT_BCR_SPEED_SELECT1; + break; + case NGBE_LINK_SPEED_100M_FULL: + value = YT_BCR_SPEED_SELECT0; + break; + case NGBE_LINK_SPEED_10M_FULL: + value = 0; + break; + default: + value = YT_BCR_SPEED_SELECT0 | + YT_BCR_SPEED_SELECT1; + DEBUGOUT("unknown speed = 0x%x", speed); + break; + } + /* duplex full */ + value |= YT_BCR_DUPLEX | YT_BCR_RESET; + hw->phy.write_reg(hw, YT_BCR, 0, value); + + goto skip_an_sr; + } + + value = 0; + if (speed & NGBE_LINK_SPEED_1GB_FULL) { + hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; + value |= YT_BCR_SPEED_SELECT1; + } + if (speed & NGBE_LINK_SPEED_100M_FULL) { + hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_100M_FULL; + value |= YT_BCR_SPEED_SELECT0; + } + if (speed & NGBE_LINK_SPEED_10M_FULL) + hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_10M_FULL; + + /* duplex full */ + value |= YT_BCR_DUPLEX | YT_BCR_RESET; + hw->phy.write_reg(hw, YT_BCR, 0, value); + + /* software reset to make the above configuration take effect */ + hw->phy.read_reg(hw, YT_BCR, 0, &value); + value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN; + hw->phy.write_reg(hw, 0x0, 0, value); + +skip_an_sr: hw->phy.set_phy_power(hw, true); }