From patchwork Wed Jun 22 06:56:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113219 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CA084A04FD; Wed, 22 Jun 2022 08:48:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 59A354280C; Wed, 22 Jun 2022 08:48:14 +0200 (CEST) Received: from smtpbgsg1.qq.com. (smtpbgsg1.qq.com [54.254.200.92]) by mails.dpdk.org (Postfix) with ESMTP id E28B8427F8 for ; Wed, 22 Jun 2022 08:48:12 +0200 (CEST) X-QQ-mid: bizesmtp66t1655880482tmqkmqp2 Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Jun 2022 14:48:01 +0800 (CST) X-QQ-SSF: 01400000002000F0Q000B00A0000000 X-QQ-FEAT: TskX/GkkryD6csM+0w+uMvW8t3eQ84NRNrMzNocyzI4eUgzbtbyPGUHJLGpxd JHA+6gT1RdZG0Jnixud+wH9vtPiIP1nF+T2jS7bEXH55l3FXXKmi3wAm/uTweEWC+mztib/ slG8qdzOgaWQ/Bqzf6yWmEHhjI6AaTrCLsIkgCzUeBfpo1F/IydyJpfiXEaa5IhdK0xxIQA LOW+Vq2VEFQzw55pw0hlUuIKKb1nYBqe8d+AWIvwC8iu9A1CwURyuyCSGKZlG/xOBP01Z5W juJU0IlmtU00OcN8SiDw6L4YpKlZ/t6oi9MOUiRQs3yjy7389PgByu9mwlvjfvLv4crzdKs tTaN89t2SrW5Gdvfve02kA8s2ED9BqDD40jsxDy X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH v2 1/7] net/txgbe: support OEM subsystem vendor ID Date: Wed, 22 Jun 2022 14:56:07 +0800 Message-Id: <20220622065613.661679-2-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220622065613.661679-1-jiawenwu@trustnetic.com> References: <20220622065613.661679-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign4 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for OEM subsystem vendor ID. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_22_07.rst | 4 +++ drivers/net/txgbe/base/txgbe_hw.c | 39 ++++++++++++++++++++++++++ drivers/net/txgbe/base/txgbe_hw.h | 2 ++ drivers/net/txgbe/base/txgbe_type.h | 1 + drivers/net/txgbe/txgbe_ethdev.c | 13 +++++++++ 5 files changed, 59 insertions(+) diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 6fc044edaa..96db85a707 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -167,6 +167,10 @@ New Features * Added support for yt8531s PHY. +* **Updated Wangxun txgbe driver.** + + * Added support for OEM subsystem vendor ID. + * **Added Elliptic Curve Diffie-Hellman (ECDH) algorithm in cryptodev.** Added support for Elliptic Curve Diffie Hellman (ECDH) asymmetric diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 6a045cba79..8966453a03 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -2608,6 +2608,45 @@ s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 autoc) return err; } +/* cmd_addr is used for some special command: + * 1. to be sector address, when implemented erase sector command + * 2. to be flash address when implemented read, write flash address + * + * Return 0 on success, return 1 on failure. + */ +u32 txgbe_fmgr_cmd_op(struct txgbe_hw *hw, u32 cmd, u32 cmd_addr) +{ + u32 cmd_val, i; + + cmd_val = TXGBE_SPICMD_CMD(cmd) | TXGBE_SPICMD_CLK(3) | cmd_addr; + wr32(hw, TXGBE_SPICMD, cmd_val); + + for (i = 0; i < TXGBE_SPI_TIMEOUT; i++) { + if (rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_OPDONE) + break; + + usec_delay(10); + } + + if (i == TXGBE_SPI_TIMEOUT) + return 1; + + return 0; +} + +u32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr) +{ + u32 status; + + status = txgbe_fmgr_cmd_op(hw, 1, addr); + if (status == 0x1) { + DEBUGOUT("Read flash timeout."); + return status; + } + + return rd32(hw, TXGBE_SPIDAT); +} + /** * txgbe_init_ops_pf - Inits func ptrs and MAC type * @hw: pointer to hardware structure diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h index fd2f7d784c..7031589f7c 100644 --- a/drivers/net/txgbe/base/txgbe_hw.h +++ b/drivers/net/txgbe/base/txgbe_hw.h @@ -111,4 +111,6 @@ s32 txgbe_prot_autoc_read_raptor(struct txgbe_hw *hw, bool *locked, u64 *value); s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 value); s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw); bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw); +u32 txgbe_fmgr_cmd_op(struct txgbe_hw *hw, u32 cmd, u32 cmd_addr); +u32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr); #endif /* _TXGBE_HW_H_ */ diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index d95467f9f8..343279127f 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -28,6 +28,7 @@ #define TXGBE_FDIR_INIT_DONE_POLL 10 #define TXGBE_FDIRCMD_CMD_POLL 10 #define TXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ +#define TXGBE_SPI_TIMEOUT 10000 #define TXGBE_ALIGN 128 /* as intel did */ diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index f0994f028d..dc8c3c70a9 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -594,6 +594,19 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) /* Vendor and Device ID need to be set before init of shared code */ hw->device_id = pci_dev->id.device_id; hw->vendor_id = pci_dev->id.vendor_id; + if (pci_dev->id.subsystem_vendor_id == PCI_VENDOR_ID_WANGXUN) { + hw->subsystem_device_id = pci_dev->id.subsystem_device_id; + } else { + u32 ssid; + + ssid = txgbe_flash_read_dword(hw, 0xFFFDC); + if (ssid == 0x1) { + PMD_INIT_LOG(ERR, + "Read of internal subsystem device id failed\n"); + return -ENODEV; + } + hw->subsystem_device_id = (u16)ssid >> 8 | (u16)ssid << 8; + } hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; hw->allow_unsupported_sfp = 1; From patchwork Wed Jun 22 06:56:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113218 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2F725A04FD; Wed, 22 Jun 2022 08:48:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 254F740DDB; Wed, 22 Jun 2022 08:48:11 +0200 (CEST) Received: from smtpbgau1.qq.com. (smtpbgau1.qq.com [54.206.16.166]) by mails.dpdk.org (Postfix) with ESMTP id CD59240DDB for ; Wed, 22 Jun 2022 08:48:09 +0200 (CEST) X-QQ-mid: bizesmtp66t1655880485t4a6nc9h Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Jun 2022 14:48:04 +0800 (CST) X-QQ-SSF: 01400000002000F0Q000B00A0000000 X-QQ-FEAT: xoS364mEyr3Uz+2KJxazXlbcmk2PM4FyY5uvbQGyVAKT1BGO/2+CdGOwkFHZw hmvjKQ4IB8QwVrdvfV5HGXwhq1UYgiM8vkhuUpJm7TXQKtKXON7FuEx02E8GLSE3spUhvqh Xb3LjtT4YBQn4NBc+EBim+sfqH/pVH9rwRog8UpBPg1ZWa9eWkr17nyVHjnXVD2dHNadLjC ECpOkHhxe6zXSVFjWnZqIY6qwvdqByHelSW0HfZRnOBl5m0OiQGCENAVHiuSpxJ6Ul3nvwy htRmNRt971b84frRiud6Guw4pm/n2P8ikCi+bMP9QfmblRd4wbpb4oR1AO29HT6v/nwfQ6V JbpyeXTYp5Xw6RgZ3St1/wpLtgviZL20jaGbHnqkshbQU8CpkE= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH v2 2/7] net/ngbe: support OEM subsystem vendor ID Date: Wed, 22 Jun 2022 14:56:08 +0800 Message-Id: <20220622065613.661679-3-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220622065613.661679-1-jiawenwu@trustnetic.com> References: <20220622065613.661679-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign8 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for OEM subsystem vendor ID. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_22_07.rst | 1 + drivers/net/ngbe/base/ngbe_hw.c | 13 +++++++------ drivers/net/ngbe/base/ngbe_type.h | 2 +- drivers/net/ngbe/ngbe_ethdev.c | 14 +++++++++++++- 4 files changed, 22 insertions(+), 8 deletions(-) diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 96db85a707..b26efb8719 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -166,6 +166,7 @@ New Features * **Updated Wangxun ngbe driver.** * Added support for yt8531s PHY. + * Added support for OEM subsystem vendor ID. * **Updated Wangxun txgbe driver.** diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c index c1114ba3b1..283cdca367 100644 --- a/drivers/net/ngbe/base/ngbe_hw.c +++ b/drivers/net/ngbe/base/ngbe_hw.c @@ -1822,22 +1822,23 @@ s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval) /* cmd_addr is used for some special command: * 1. to be sector address, when implemented erase sector command * 2. to be flash address when implemented read, write flash address + * + * Return 0 on success, return 1 on failure. */ u32 ngbe_fmgr_cmd_op(struct ngbe_hw *hw, u32 cmd, u32 cmd_addr) { - u32 cmd_val = 0; - u32 i = 0; + u32 cmd_val, i; cmd_val = NGBE_SPICMD_CMD(cmd) | NGBE_SPICMD_CLK(3) | cmd_addr; wr32(hw, NGBE_SPICMD, cmd_val); - for (i = 0; i < 10000; i++) { + for (i = 0; i < NGBE_SPI_TIMEOUT; i++) { if (rd32(hw, NGBE_SPISTAT) & NGBE_SPISTAT_OPDONE) break; usec_delay(10); } - if (i == 10000) + if (i == NGBE_SPI_TIMEOUT) return 1; return 0; @@ -1845,10 +1846,10 @@ u32 ngbe_fmgr_cmd_op(struct ngbe_hw *hw, u32 cmd, u32 cmd_addr) u32 ngbe_flash_read_dword(struct ngbe_hw *hw, u32 addr) { - u32 status = 0; + u32 status; status = ngbe_fmgr_cmd_op(hw, 1, addr); - if (status) { + if (status == 0x1) { DEBUGOUT("Read flash timeout."); return status; } diff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h index 0ad4766d2a..4a6c273f1e 100644 --- a/drivers/net/ngbe/base/ngbe_type.h +++ b/drivers/net/ngbe/base/ngbe_type.h @@ -18,7 +18,7 @@ #define NGBE_MAX_UTA 128 #define NGBE_PCI_MASTER_DISABLE_TIMEOUT 800 - +#define NGBE_SPI_TIMEOUT 10000 #define NGBE_ALIGN 128 /* as intel did */ #define NGBE_ISB_SIZE 16 diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index 5ac1c27a58..ee09d54c2f 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -359,7 +359,19 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) hw->back = pci_dev; hw->device_id = pci_dev->id.device_id; hw->vendor_id = pci_dev->id.vendor_id; - hw->sub_system_id = pci_dev->id.subsystem_device_id; + if (pci_dev->id.subsystem_vendor_id == PCI_VENDOR_ID_WANGXUN) { + hw->sub_system_id = pci_dev->id.subsystem_device_id; + } else { + u32 ssid; + + ssid = ngbe_flash_read_dword(hw, 0xFFFDC); + if (ssid == 0x1) { + PMD_INIT_LOG(ERR, + "Read of internal subsystem device id failed\n"); + return -ENODEV; + } + hw->sub_system_id = (u16)ssid >> 8 | (u16)ssid << 8; + } ngbe_map_device_id(hw); hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; From patchwork Wed Jun 22 06:56:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113220 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 82368A04FD; Wed, 22 Jun 2022 08:48:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 639FF427F4; Wed, 22 Jun 2022 08:48:19 +0200 (CEST) Received: from smtpbgbr2.qq.com. (smtpbgbr2.qq.com [54.207.22.56]) by mails.dpdk.org (Postfix) with ESMTP id 7A55942820 for ; Wed, 22 Jun 2022 08:48:17 +0200 (CEST) X-QQ-mid: bizesmtp66t1655880488t0njnr5x Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Jun 2022 14:48:06 +0800 (CST) X-QQ-SSF: 01400000002000F0Q000B00A0000000 X-QQ-FEAT: Mzskoac49OiYGAtVeEUig2nInjyN51+mmj8RommEP48s8SE34VYP7aas7nmnm rk6AgTBuQYIVQbDZjW8fmvHfZPbytDBedIfF8biztPlwY5qYWLA0M1GxQ2jIQKbQHZwRy7K 8nu8E1Sw8WiV+f2xTkJsIwxrcffcPAbIvFQV8gMsHQHtjc8Sq2AZ0p9gg6BHkrN2wqNSY+3 dBelqpmIcZzyrDgU7Xs9A0srGr1yQtgFMp2wh088uIzGZnl/WpBfkn3uXGOYfw1zSEtZO+F GxjeB3aiSyJ+p77o3x/2a8jP4cItABbdiYKh8gNwifhuqJZtZp+0uoCUkHwZmFePhOgbc4/ /MCkC9eAUZUTRzg0VP3DX3IDWrfFDjdBsTNYe0h X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 3/7] net/txgbe: fix register polling Date: Wed, 22 Jun 2022 14:56:09 +0800 Message-Id: <20220622065613.661679-4-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220622065613.661679-1-jiawenwu@trustnetic.com> References: <20220622065613.661679-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign8 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix to poll some specific registers, which expect bit value 0. 'w32w' is used in registers where the write command bit is set and waits for the bit clear to complete the write. Fixes: 24a4c76aff4d ("net/txgbe: add error types and registers") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_regs.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 3139796911..911bb6e04e 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1864,8 +1864,13 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, } do { - all |= rd32(hw, reg); - value |= mask & all; + if (expect != 0) { + all |= rd32(hw, reg); + value |= mask & all; + } else { + all = rd32(hw, reg); + value = mask & all; + } if (value == expect) break; @@ -1898,7 +1903,7 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, #define wr32w(hw, reg, val, mask, slice) do { \ wr32((hw), reg, val); \ - po32m((hw), reg, mask, mask, NULL, 5, slice); \ + po32m((hw), reg, mask, 0, NULL, 5, slice); \ } while (0) #define TXGBE_XPCS_IDAADDR 0x13000 From patchwork Wed Jun 22 06:56:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113221 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 531F2A04FD; Wed, 22 Jun 2022 08:48:33 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 663BE4282D; Wed, 22 Jun 2022 08:48:23 +0200 (CEST) Received: from smtpproxy21.qq.com (smtpbg703.qq.com [203.205.195.89]) by mails.dpdk.org (Postfix) with ESMTP id ED75D4282A for ; Wed, 22 Jun 2022 08:48:20 +0200 (CEST) X-QQ-mid: bizesmtp66t1655880491tvzdcb69 Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Jun 2022 14:48:10 +0800 (CST) X-QQ-SSF: 01400000002000F0Q000B00A0000000 X-QQ-FEAT: F3yR32iATbj57DaptpeFQ/3bR2NfsXL8VSJVAo4xVCsIW/psnadmt2+pSSj/9 m45MujEiMAb6yPj/wE/KxE48QM+Qv9G/6r0ddUacNj4gst+X681+jA3X7+u9Xr4d/svCTzZ WYJU0c86QJYBnFJgDirCHp/HHm1udla249DnjzhG/ky/fG1cx1LDAXokHA2BPwcFF4kfG8x 7pQ8FtOunwglC0u4GvQmFcfoiFt2BUqYbp4ZhOkYugE4Am+zqoJP+DXTmZNbS/ziXglH6n8 ydpcQxBsDXeEVbXO36rir5iMUWU9+l/0VmIiEw9pSzosxF3u/ckIbv1hzgguz0KR1BmAwmL usMMwpoVR3RJjJAm5YjJCZO2w/rOjzARh5xZpRX/CMVaVeDbKM= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 4/7] net/ngbe: add more packet statistics Date: Wed, 22 Jun 2022 14:56:10 +0800 Message-Id: <20220622065613.661679-5-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220622065613.661679-1-jiawenwu@trustnetic.com> References: <20220622065613.661679-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign4 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add more hardware extended statistics. Fixes: 8b433d04adc9 ("net/ngbe: support device xstats") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/ngbe_ethdev.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index ee09d54c2f..308c231183 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -164,6 +164,8 @@ static const struct rte_ngbe_xstats_name_off rte_ngbe_stats_strings[] = { HW_XSTAT(rx_management_packets), HW_XSTAT(tx_management_packets), HW_XSTAT(rx_management_dropped), + HW_XSTAT(rx_dma_drop), + HW_XSTAT(tx_secdrp_packets), /* Basic Error */ HW_XSTAT(rx_crc_errors), @@ -179,6 +181,12 @@ static const struct rte_ngbe_xstats_name_off rte_ngbe_stats_strings[] = { HW_XSTAT(mac_local_errors), HW_XSTAT(mac_remote_errors), + /* PB Stats */ + HW_XSTAT(rx_up_dropped), + HW_XSTAT(rdb_pkt_cnt), + HW_XSTAT(rdb_repli_cnt), + HW_XSTAT(rdb_drp_cnt), + /* MACSEC */ HW_XSTAT(tx_macsec_pkts_untagged), HW_XSTAT(tx_macsec_pkts_encrypted), From patchwork Wed Jun 22 06:56:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113223 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6B283A04FD; Wed, 22 Jun 2022 08:48:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 53CE242B6E; Wed, 22 Jun 2022 08:48:26 +0200 (CEST) Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by mails.dpdk.org (Postfix) with ESMTP id EC66842823 for ; Wed, 22 Jun 2022 08:48:22 +0200 (CEST) X-QQ-mid: bizesmtp66t1655880494t3rj2844 Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Jun 2022 14:48:13 +0800 (CST) X-QQ-SSF: 01400000002000F0Q000B00A0000000 X-QQ-FEAT: 3u0oYPVhaeMZSqMS51syWg1ajYydTN6C1BlT5RdoQDPws35N5o9tiS+Nn4+3t iiWHH/uU2XVpKgZo2u1QZBdhSMdsyrT/MpKxhD2nPetXWIeD3XKw/iRvLtXIa3Du8Vh8eYu 0MDql9tSXTRJArtnGd56mbNVJznVsuKPx7s8NeTwupKfRjm1vgR/5qqoszX8NS1FWwShO74 sdCGiw0mvVMzyEGp0WNQf3RRq7dghBb64vVz/rp0uR9yJ1/9QPw8jevVOXiXFGV7QVjqyq1 cYdUZ6xylaTMRazcg/XBphxx+tAWWeW++J0VqytK0BdPtHz8pQEacQ5wWZJKXqw51zXAYFB L/Xok7c5WQ4AqwUTrvnkONBz9opcia1QI0SNYFJjkzEEe0eWko= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 5/7] net/ngbe: fix YT PHY UTP mode to link up Date: Wed, 22 Jun 2022 14:56:11 +0800 Message-Id: <20220622065613.661679-6-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220622065613.661679-1-jiawenwu@trustnetic.com> References: <20220622065613.661679-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign3 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix to read and write the correct register fields for yt8521s and yt8531s PHY, since mode check was added. Fixes: 1c44384fce76 ("net/ngbe: support custom PHY interfaces") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/base/ngbe_phy_yt.c | 42 ++++++++++++++--------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c index f46121b8d1..9dd2b2264f 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.c +++ b/drivers/net/ngbe/base/ngbe_phy_yt.c @@ -146,21 +146,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } /* duplex full */ value |= YT_BCR_DUPLEX | YT_BCR_RESET; - hw->phy.write_reg(hw, YT_BCR, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); goto skip_an; } /*disable 100/10base-T Self-negotiation ability*/ - hw->phy.read_reg(hw, YT_ANA, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF | YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF); - hw->phy.write_reg(hw, YT_ANA, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value); /*disable 1000base-T Self-negotiation ability*/ - hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value); value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF); - hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value); if (speed & NGBE_LINK_SPEED_1GB_FULL) { hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; @@ -176,19 +176,19 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } /* enable 1000base-T Self-negotiation ability */ - hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value); value |= value_r9; - hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value); /* enable 100/10base-T Self-negotiation ability */ - hw->phy.read_reg(hw, YT_ANA, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value |= value_r4; - hw->phy.write_reg(hw, YT_ANA, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value); /* software reset to make the above configuration take effect*/ - hw->phy.read_reg(hw, YT_BCR, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value); value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN; - hw->phy.write_reg(hw, YT_BCR, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); skip_an: hw->phy.set_phy_power(hw, true); } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) { @@ -219,15 +219,15 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } else { /* utp up */ /*disable 100/10base-T Self-negotiation ability*/ - hw->phy.read_reg(hw, YT_ANA, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF | YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF); - hw->phy.write_reg(hw, YT_ANA, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value); /*disable 1000base-T Self-negotiation ability*/ - hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value); value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF); - hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value); if (speed & NGBE_LINK_SPEED_1GB_FULL) { hw->phy.autoneg_advertised |= @@ -246,21 +246,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } /* enable 1000base-T Self-negotiation ability */ - hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value); value |= value_r9; - hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value); /* enable 100/10base-T Self-negotiation ability */ - hw->phy.read_reg(hw, YT_ANA, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value |= value_r4; - hw->phy.write_reg(hw, YT_ANA, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value); /* software reset to make the above configuration * take effect */ - hw->phy.read_reg(hw, YT_BCR, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value); value |= YT_BCR_RESET; - hw->phy.write_reg(hw, YT_BCR, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); } } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(4)) { hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; From patchwork Wed Jun 22 06:56:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113222 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 03038A04FD; Wed, 22 Jun 2022 08:48:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 67CF04282C; Wed, 22 Jun 2022 08:48:25 +0200 (CEST) Received: from smtpbg156.qq.com (smtpbg156.qq.com [15.184.82.18]) by mails.dpdk.org (Postfix) with ESMTP id 8CCD94069C for ; Wed, 22 Jun 2022 08:48:22 +0200 (CEST) X-QQ-mid: bizesmtp66t1655880497tgs42ajc Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Jun 2022 14:48:16 +0800 (CST) X-QQ-SSF: 01400000002000F0Q000B00A0000000 X-QQ-FEAT: rdJZyKtT4DhVDdhpEpOZEZl5Xt4H6mMn7BDrurzmei13YqdASx3o0na7RqmtU 2zVn55Zn85Q75kwUkOxJWXKRwfKTy3HvKhIva7iqPX0jLXryqBIfU4TXgynK42ZMpH4Gkyq 9qBB2Bl4BV8aEklv4dfNCBVm6LgnEAzP/u+z8dsPI9dip2l8T8skBKCiexNeG7tQTMdrVHr Lbk+ul/da4cyk+9+LnIcrJZLzIigr2OzA6vjOFRXyezPREXIL4tCCGkWO1vRypTUUqEpWQk q0GMDBG45Ct0S/uRwkW3pDBMyeKJ0mCk0nRIvRmpLsm3pDLp+6OH2mWNp+ZcvCP/B/CGVGs UADvxNhHutX0Z6kWJ2TEvrMjpsTJjMwXTbhMUC6xvsDbM9QuHY= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH v2 6/7] net/ngbe: support autoneg on/off for external PHY SFI mode Date: Wed, 22 Jun 2022 14:56:12 +0800 Message-Id: <20220622065613.661679-7-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220622065613.661679-1-jiawenwu@trustnetic.com> References: <20220622065613.661679-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign9 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for external PHY to switch autoneg on/off on their SFI mode. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_22_07.rst | 1 + drivers/net/ngbe/base/ngbe_phy_mvl.c | 16 +++++++++++++--- drivers/net/ngbe/base/ngbe_phy_yt.c | 20 +++++++++++++++++++- drivers/net/ngbe/base/ngbe_phy_yt.h | 5 +++++ 4 files changed, 38 insertions(+), 4 deletions(-) diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index b26efb8719..a84c5b486b 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -167,6 +167,7 @@ New Features * Added support for yt8531s PHY. * Added support for OEM subsystem vendor ID. + * Added autoneg on/off for external PHY SFI mode. * **Updated Wangxun txgbe driver.** diff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.c b/drivers/net/ngbe/base/ngbe_phy_mvl.c index c5256359ed..8746a72eb3 100644 --- a/drivers/net/ngbe/base/ngbe_phy_mvl.c +++ b/drivers/net/ngbe/base/ngbe_phy_mvl.c @@ -203,6 +203,10 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed, MVL_PHY_1000BASET_HALF); value_r9 |= value; hw->phy.write_reg(hw, MVL_PHY_1000BASET, 0, value_r9); + + value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE | + MVL_CTRL_RESET | MVL_CTRL_DUPLEX; + ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value); } else { hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; @@ -210,10 +214,16 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed, value &= ~(MVL_PHY_1000BASEX_HALF | MVL_PHY_1000BASEX_FULL); value |= MVL_PHY_1000BASEX_FULL; hw->phy.write_reg(hw, MVL_ANA, 0, value); - } - value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE | MVL_CTRL_RESET; - ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value); + if (hw->mac.autoneg) + value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE | + MVL_CTRL_RESET | MVL_CTRL_DUPLEX | + MVL_CTRL_SPEED_SELECT1; + else + value = MVL_CTRL_RESET | MVL_CTRL_DUPLEX | + MVL_CTRL_SPEED_SELECT1; + ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value); + } skip_an: hw->phy.set_phy_power(hw, true); diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c index 9dd2b2264f..bc1921e68a 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.c +++ b/drivers/net/ngbe/base/ngbe_phy_yt.c @@ -205,8 +205,26 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, YT_CHIP_SW_RST; ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value); + ngbe_read_phy_reg_sds_ext_yt(hw, YT_AUTO, 0, &value); + value &= ~YT_AUTO_SENSING; + ngbe_write_phy_reg_sds_ext_yt(hw, YT_AUTO, 0, value); + + ngbe_read_phy_reg_ext_yt(hw, YT_MISC, 0, &value); + value |= YT_MISC_RESV; + ngbe_write_phy_reg_ext_yt(hw, YT_MISC, 0, value); + + ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value); + value &= ~YT_CHIP_SW_RST; + ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value); + /* software reset */ - ngbe_write_phy_reg_sds_ext_yt(hw, 0x0, 0, 0x9140); + if (hw->mac.autoneg) + value = YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN | + YT_BCR_DUPLEX | YT_BCR_SPEED_SELECT1; + else + value = YT_BCR_RESET | YT_BCR_DUPLEX | + YT_BCR_SPEED_SELECT1; + hw->phy.write_reg(hw, YT_BCR, 0, value); hw->phy.set_phy_power(hw, true); } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(2)) { diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.h b/drivers/net/ngbe/base/ngbe_phy_yt.h index 06e8f77261..ddf992e79a 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.h +++ b/drivers/net/ngbe/base/ngbe_phy_yt.h @@ -31,6 +31,11 @@ #define YT_RGMII_CONF2_LINKUP MS16(4, 0x1) #define YT_MISC 0xA006 #define YT_MISC_FIBER_PRIO MS16(8, 0x1) /* 0 for UTP */ +#define YT_MISC_RESV MS16(0, 0x1) + +/* SDS EXT */ +#define YT_AUTO 0xA5 +#define YT_AUTO_SENSING MS16(15, 0x1) /* MII common registers in UTP and SDS */ #define YT_BCR 0x0 From patchwork Wed Jun 22 06:56:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113224 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B47E2A04FD; Wed, 22 Jun 2022 08:48:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3D1DB42B74; Wed, 22 Jun 2022 08:48:27 +0200 (CEST) Received: from smtpbg506.qq.com (smtpbg506.qq.com [203.205.250.33]) by mails.dpdk.org (Postfix) with ESMTP id 9A9BC42905 for ; Wed, 22 Jun 2022 08:48:24 +0200 (CEST) X-QQ-mid: bizesmtp66t1655880499tafqycmf Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Jun 2022 14:48:18 +0800 (CST) X-QQ-SSF: 01400000002000F0Q000B00A0000000 X-QQ-FEAT: +GNuArsXEgF3mRUZcS8v+Hoo6yniFzs+OQjNal7AaT770rchbfipDhlmNRjXg 0VUfTXoKb52NICrxKL/sea0yJtjDx4pLOegKt9fI+uzye16cVMNm4KFYEgtj+t/o4yZVDmM uM3olOYOdNUu2r+mktqmQXfauaORVYh51wI/VxElvhZlhmomDCZX9l91hMU1ib4Qrshzd1v tCgQ0LBK9nlydzY9KW6sY8pvDTPqAjEyt5G782cX34hvx2VgFVWrV7wiDc7wzY0mQDZ1Sjo N5LoOD3afEsaJ9TjjcZOm6/q7+nscahKeBts5saY1DELAsnQ1GpWdo2Ttg6awngj6rmaMM5 vXFbhiFsgpnOgLbOdbJJInsXd4cjhLc0a7HU1GR X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH v2 7/7] net/ngbe: support YT PHY SGMII to RGMII mode Date: Wed, 22 Jun 2022 14:56:13 +0800 Message-Id: <20220622065613.661679-8-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220622065613.661679-1-jiawenwu@trustnetic.com> References: <20220622065613.661679-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign9 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add SGMII to RGMII mode for yt8521s and yt8531s PHY. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_22_07.rst | 1 + drivers/net/ngbe/base/ngbe_phy_yt.c | 49 ++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index a84c5b486b..6baa63e3bf 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -168,6 +168,7 @@ New Features * Added support for yt8531s PHY. * Added support for OEM subsystem vendor ID. * Added autoneg on/off for external PHY SFI mode. + * Added support for yt8521s/yt8531s PHY SGMII to RGMII mode. * **Updated Wangxun txgbe driver.** diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c index bc1921e68a..562a0dede5 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.c +++ b/drivers/net/ngbe/base/ngbe_phy_yt.c @@ -298,6 +298,55 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, value &= ~YT_SMI_PHY_SW_RST; ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value); + hw->phy.set_phy_power(hw, true); + } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(5)) { + /* sgmii_to_rgmii */ + if (!hw->mac.autoneg) { + switch (speed) { + case NGBE_LINK_SPEED_1GB_FULL: + value = YT_BCR_SPEED_SELECT1; + break; + case NGBE_LINK_SPEED_100M_FULL: + value = YT_BCR_SPEED_SELECT0; + break; + case NGBE_LINK_SPEED_10M_FULL: + value = 0; + break; + default: + value = YT_BCR_SPEED_SELECT0 | + YT_BCR_SPEED_SELECT1; + DEBUGOUT("unknown speed = 0x%x", speed); + break; + } + /* duplex full */ + value |= YT_BCR_DUPLEX | YT_BCR_RESET; + hw->phy.write_reg(hw, YT_BCR, 0, value); + + goto skip_an_sr; + } + + value = 0; + if (speed & NGBE_LINK_SPEED_1GB_FULL) { + hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; + value |= YT_BCR_SPEED_SELECT1; + } + if (speed & NGBE_LINK_SPEED_100M_FULL) { + hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_100M_FULL; + value |= YT_BCR_SPEED_SELECT0; + } + if (speed & NGBE_LINK_SPEED_10M_FULL) + hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_10M_FULL; + + /* duplex full */ + value |= YT_BCR_DUPLEX | YT_BCR_RESET; + hw->phy.write_reg(hw, YT_BCR, 0, value); + + /* software reset to make the above configuration take effect */ + hw->phy.read_reg(hw, YT_BCR, 0, &value); + value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN; + hw->phy.write_reg(hw, 0x0, 0, value); + +skip_an_sr: hw->phy.set_phy_power(hw, true); }