From patchwork Sat Jul 2 16:22:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy McDaniel X-Patchwork-Id: 113643 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 227AFA0093; Sat, 2 Jul 2022 18:22:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C12A7427F3; Sat, 2 Jul 2022 18:22:44 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 16CD840E50 for ; Sat, 2 Jul 2022 18:22:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656778963; x=1688314963; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pqLK8ZaZHCwhwffFuW1EFiSddcFVVSyV6J+z01jxqTA=; b=aHUixCowxSe60ysng4PRH2SrZF2PtxxYEbZk8ovhd2LdmuiOZP5leASs SxmgvUlMuvyR9cC+n7MJz99m/WOvpP0YnhK1BM4r6abDrdFTsLqQyIRc0 r2QbMSzaRYwXy6+G7GU+FMCB5275rMJiyZ+Q8Eykaubifi8FrHSVYoeU4 vUeobiZoONxLLxqJlEFzCk+9qFqsMurSTS1AnPZFDU9yHgZ1HItFCt0WA Sc4Ae473rqSKEPIQUld93KiBxU0qSp8Dbl0b8WmDair4f8kNYy946u27W XZbL+083FtMeeHEMFYABm9DSk2SCXMS+5edhHgo3BCuH09ky8nmijsRyZ g==; X-IronPort-AV: E=McAfee;i="6400,9594,10396"; a="283957272" X-IronPort-AV: E=Sophos;i="5.92,240,1650956400"; d="scan'208";a="283957272" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2022 09:22:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,240,1650956400"; d="scan'208";a="648781614" Received: from txanpdk03.an.intel.com ([10.123.117.78]) by fmsmga008.fm.intel.com with ESMTP; 02 Jul 2022 09:22:41 -0700 From: Timothy McDaniel To: jerinj@marvell.com Cc: dev@dpdk.org, timothy.mcdaniel@intel.com Subject: [PATCH v3 1/5] event/dlb2: fix port_cos array sizing Date: Sat, 2 Jul 2022 11:22:35 -0500 Message-Id: <20220702162239.1646548-2-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20220702162239.1646548-1-timothy.mcdaniel@intel.com> References: <20220629153638.1269743-1-timothy.mcdaniel@intel.com> <20220702162239.1646548-1-timothy.mcdaniel@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit fixes a segfault that resulted from reading beyond the end of the port_cos array. The root cause was using the DLB num ports define instead of the eventdev num ports define. Fixes: bec8901bfe9f ("event/dlb2: support ldb port specific COS") Cc: timothy.mcdaniel@intel.com Signed-off-by: Timothy McDaniel --- drivers/event/dlb2/dlb2_priv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h index 528e2ede61..8744efa79d 100644 --- a/drivers/event/dlb2/dlb2_priv.h +++ b/drivers/event/dlb2/dlb2_priv.h @@ -640,7 +640,7 @@ struct dlb2_cq_weight { }; struct dlb2_port_cos { - int cos_id[DLB2_MAX_NUM_LDB_PORTS]; + int cos_id[DLB2_MAX_NUM_PORTS_ALL]; }; struct dlb2_cos_bw { From patchwork Sat Jul 2 16:22:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy McDaniel X-Patchwork-Id: 113644 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 50857A0093; Sat, 2 Jul 2022 18:22:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B980B42836; Sat, 2 Jul 2022 18:22:45 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 8BAF541132 for ; Sat, 2 Jul 2022 18:22:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656778963; x=1688314963; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0aLrf7QSkBNHNwkeMHrx6m9MhYVYwA3d+NYHll2MjSU=; b=bfDpasl52RqkS8ZzXmz+MAHrKe64hP2waJn0yCZLmjbw4Xx999+qzTut WyCrA4Tq5ca0XjWX30km6gRziqPcnIIsJ3bQYBJ2dUwpf//qK222FVA+O 6zqlP9kPAkqVUBlY9Vj3Q0bvMeqOyzaG5FbMMZnPZ6RTycVoGW5/IT6A/ hG3vkZewcylaoSXdb3V2+wBx+MjNlT4HSnZobIf+iIV8xrLgWOotU2AsL f20vCWEppZFdRvtyBR38dwbndt6Ec137tAgBbjr+ltoNIuCUH1j0E/d9z JpftiH3kUvU3y93sTjrbKLJ3jgXOVFAjOujXsU1DQfUn6dvOmKFdOBBX5 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10396"; a="283957273" X-IronPort-AV: E=Sophos;i="5.92,240,1650956400"; d="scan'208";a="283957273" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2022 09:22:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,240,1650956400"; d="scan'208";a="648781617" Received: from txanpdk03.an.intel.com ([10.123.117.78]) by fmsmga008.fm.intel.com with ESMTP; 02 Jul 2022 09:22:41 -0700 From: Timothy McDaniel To: jerinj@marvell.com Cc: dev@dpdk.org, timothy.mcdaniel@intel.com Subject: [PATCH v3 2/5] event/dlb2: fix initialization of cos bandwidth args Date: Sat, 2 Jul 2022 11:22:36 -0500 Message-Id: <20220702162239.1646548-3-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20220702162239.1646548-1-timothy.mcdaniel@intel.com> References: <20220629153638.1269743-1-timothy.mcdaniel@intel.com> <20220702162239.1646548-1-timothy.mcdaniel@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit fixes a typo and resultant bug that triggered a coverity warning. Coverity issue: 4607286 Fixes: bec8901bfe9f ("event/dlb2: support ldb port specific COS") Cc: timothy.mcdaniel@intel.com Signed-off-by: Timothy McDaniel --- drivers/event/dlb2/dlb2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index 78433d2fe0..a6182a1ac7 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -4540,7 +4540,7 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev, for (id = 0; id < DLB2_COS_NUM_VALS; id++) { set_cos_bw_args.cos_id = id; - set_cos_bw_args.cos_id = dlb2->cos_bw[id]; + set_cos_bw_args.bandwidth = dlb2->cos_bw[id]; ret = dlb2_iface_set_cos_bw(&dlb2->qm_instance, &set_cos_bw_args); if (ret != 0) From patchwork Sat Jul 2 16:22:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy McDaniel X-Patchwork-Id: 113645 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2730EA0093; Sat, 2 Jul 2022 18:23:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C2EA141133; Sat, 2 Jul 2022 18:22:46 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id B054440E50 for ; Sat, 2 Jul 2022 18:22:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656778963; x=1688314963; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0jazhvvuNDnxW1EBec2phsOx1f+WDm0lXEHz8d/OGjU=; b=ZOygY6cvVELtH9h3QuVPTxB8rCBEc+jWAjtl81e0HeNkS6Eiyy3weBl9 goHBORGLmGWFtFzmgq1U6ZnZ4mll1xWK1U06SnoaNayf4sHcGbfdw61s8 yOZNdYCtfcnTLSNsNYetskdOn3oc0wfZsaAZYVKA5Rcxz3vRGCY7h5VNY MlZPSQtKqJ+goryOncN9toyMsIIE7xqM5iHw8wgZaSNWT3Ea9qCV79zXc X+RWMONEL24/bix0E8JRgQf6bRO8znZItVKkwwNTvkeDgyWx4Pt9pjEC8 8t20mTLbSUyr3od6ssapFtOWODdvZ+km5GgyxNaDLEsPvjTb3tRKXer+7 Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10396"; a="283957275" X-IronPort-AV: E=Sophos;i="5.92,240,1650956400"; d="scan'208";a="283957275" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2022 09:22:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,240,1650956400"; d="scan'208";a="648781622" Received: from txanpdk03.an.intel.com ([10.123.117.78]) by fmsmga008.fm.intel.com with ESMTP; 02 Jul 2022 09:22:42 -0700 From: Timothy McDaniel To: jerinj@marvell.com Cc: dev@dpdk.org, timothy.mcdaniel@intel.com Subject: [PATCH v3 3/5] event/dlb2: fix cq depth override Date: Sat, 2 Jul 2022 11:22:37 -0500 Message-Id: <20220702162239.1646548-4-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20220702162239.1646548-1-timothy.mcdaniel@intel.com> References: <20220629153638.1269743-1-timothy.mcdaniel@intel.com> <20220702162239.1646548-1-timothy.mcdaniel@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit fixes a bug, where we could assign a cq depth of zero, leading to a subsequent divide-by-zero fault. It also fixes an issue where the original default cq depth was returned on a query, insgtead of the overridden value. Fixes: 86fe66d45667 ("event/dlb2: allow CQ depths up to 1024") Cc: timothy.mcdaniel@intel.com Signed-off-by: Timothy McDaniel --- drivers/event/dlb2/dlb2.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index a6182a1ac7..b50cd8e5ce 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -4505,7 +4505,14 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev, dlb2->hw_credit_quanta = dlb2_args->hw_credit_quanta; dlb2->default_depth_thresh = dlb2_args->default_depth_thresh; dlb2->vector_opts_enabled = dlb2_args->vector_opts_enabled; - dlb2->max_cq_depth = dlb2_args->max_cq_depth; + + + if (dlb2_args->max_cq_depth != 0) + dlb2->max_cq_depth = dlb2_args->max_cq_depth; + else + dlb2->max_cq_depth = DLB2_DEFAULT_CQ_DEPTH; + + evdev_dlb2_default_info.max_event_port_dequeue_depth = dlb2->max_cq_depth; err = dlb2_iface_open(&dlb2->qm_instance, name); if (err < 0) { From patchwork Sat Jul 2 16:22:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy McDaniel X-Patchwork-Id: 113646 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 89A0EA0093; Sat, 2 Jul 2022 18:23:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC69D42B70; Sat, 2 Jul 2022 18:22:47 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 2FD3B41132 for ; Sat, 2 Jul 2022 18:22:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656778964; x=1688314964; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iPgi5J2UBlJ7Taa4Usg5YEAsg77772/o3ji4TnWZ49k=; b=awLlflJ7HYMw4jlomaY43uAJTirPPGd0hnKahsJJQrMpfz2hgYW72EHB DhX27D4+6TE/YZd62XHCBICJm+4GDlgL/Znc0WQnH9s9zVlQ8cP90YH8c cecB9fj67puz31Kf37nD4s5u5t8cnJH3OWi3B9c1RwdHs0Xa2vkKS93tV n4taxpcB77aOf6V2NmHC/X1gMYN6lN1ZZAkv8M8xslXh6PxdyQSL9TGKo svwGA+0U0+LahhfoVYzdxLHhXPIrz2RXgQR52tg3Bh9cKeAfiUgIPVkDX hhaMzUcJfwGqUs155585EgsxJV6QNKjsgSWbGW99/gAoN9iAfah17kCD/ w==; X-IronPort-AV: E=McAfee;i="6400,9594,10396"; a="283957277" X-IronPort-AV: E=Sophos;i="5.92,240,1650956400"; d="scan'208";a="283957277" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2022 09:22:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,240,1650956400"; d="scan'208";a="648781629" Received: from txanpdk03.an.intel.com ([10.123.117.78]) by fmsmga008.fm.intel.com with ESMTP; 02 Jul 2022 09:22:42 -0700 From: Timothy McDaniel To: jerinj@marvell.com Cc: dev@dpdk.org, timothy.mcdaniel@intel.com Subject: [PATCH v3 4/5] event/dlb2: fix cq depth override credit deadlock Date: Sat, 2 Jul 2022 11:22:38 -0500 Message-Id: <20220702162239.1646548-5-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20220702162239.1646548-1-timothy.mcdaniel@intel.com> References: <20220629153638.1269743-1-timothy.mcdaniel@intel.com> <20220702162239.1646548-1-timothy.mcdaniel@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit fixes a bug, where we could encounter a credit deadlock due to changing the CQ depth. To remedy this situation, the commit reduces the maximum CQ depth from 1024 to 128, and also allows configuring the maximum enqueue depth. Maximum enqueue depth must be tuned to the CQ depth, if the CQ depth is increased. Fixes: 86fe66d45667 ("event/dlb2: allow CQ depths up to 1024") Cc: timothy.mcdaniel@intel.com Signed-off-by: Timothy McDaniel --- drivers/event/dlb2/dlb2.c | 51 +++++++++++++++++++++++++++++++++ drivers/event/dlb2/dlb2_priv.h | 8 +++++- drivers/event/dlb2/pf/dlb2_pf.c | 3 +- 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index b50cd8e5ce..8a68c25c93 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -326,6 +326,36 @@ set_max_cq_depth(const char *key __rte_unused, return 0; } +static int +set_max_enq_depth(const char *key __rte_unused, + const char *value, + void *opaque) +{ + int *max_enq_depth = opaque; + int ret; + + if (value == NULL || opaque == NULL) { + DLB2_LOG_ERR("NULL pointer\n"); + return -EINVAL; + } + + ret = dlb2_string_to_int(max_enq_depth, value); + if (ret < 0) + return ret; + + if (*max_enq_depth < DLB2_MIN_ENQ_DEPTH_OVERRIDE || + *max_enq_depth > DLB2_MAX_ENQ_DEPTH_OVERRIDE || + !rte_is_power_of_2(*max_enq_depth)) { + DLB2_LOG_ERR("dlb2: max_enq_depth %d and %d and a power of 2\n", + DLB2_MIN_ENQ_DEPTH_OVERRIDE, + DLB2_MAX_ENQ_DEPTH_OVERRIDE); + return -EINVAL; + } + + return 0; +} + + static int set_max_num_events(const char *key __rte_unused, const char *value, @@ -4514,6 +4544,15 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev, evdev_dlb2_default_info.max_event_port_dequeue_depth = dlb2->max_cq_depth; + if (dlb2_args->max_enq_depth != 0) + dlb2->max_enq_depth = dlb2_args->max_enq_depth; + else + dlb2->max_enq_depth = DLB2_DEFAULT_CQ_DEPTH; + + evdev_dlb2_default_info.max_event_port_enqueue_depth = + dlb2->max_enq_depth; + + err = dlb2_iface_open(&dlb2->qm_instance, name); if (err < 0) { DLB2_LOG_ERR("could not open event hardware device, err=%d\n", @@ -4650,6 +4689,7 @@ dlb2_parse_params(const char *params, DLB2_DEPTH_THRESH_ARG, DLB2_VECTOR_OPTS_ENAB_ARG, DLB2_MAX_CQ_DEPTH, + DLB2_MAX_ENQ_DEPTH, DLB2_CQ_WEIGHT, DLB2_PORT_COS, DLB2_COS_BW, @@ -4789,6 +4829,17 @@ dlb2_parse_params(const char *params, return ret; } + ret = rte_kvargs_process(kvlist, + DLB2_MAX_ENQ_DEPTH, + set_max_enq_depth, + &dlb2_args->max_enq_depth); + if (ret != 0) { + DLB2_LOG_ERR("%s: Error parsing vector opts enabled", + name); + rte_kvargs_free(kvlist); + return ret; + } + ret = rte_kvargs_process(kvlist, DLB2_CQ_WEIGHT, set_cq_weight, diff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h index 8744efa79d..1edea83a5b 100644 --- a/drivers/event/dlb2/dlb2_priv.h +++ b/drivers/event/dlb2/dlb2_priv.h @@ -29,7 +29,10 @@ #define DLB2_SW_CREDIT_C_QUANTA_DEFAULT 256 /* Consumer */ #define DLB2_DEPTH_THRESH_DEFAULT 256 #define DLB2_MIN_CQ_DEPTH_OVERRIDE 32 -#define DLB2_MAX_CQ_DEPTH_OVERRIDE 1024 +#define DLB2_MAX_CQ_DEPTH_OVERRIDE 128 +#define DLB2_MIN_ENQ_DEPTH_OVERRIDE 32 +#define DLB2_MAX_ENQ_DEPTH_OVERRIDE 1024 + /* command line arg strings */ #define NUMA_NODE_ARG "numa_node" @@ -44,6 +47,7 @@ #define DLB2_DEPTH_THRESH_ARG "default_depth_thresh" #define DLB2_VECTOR_OPTS_ENAB_ARG "vector_opts_enable" #define DLB2_MAX_CQ_DEPTH "max_cq_depth" +#define DLB2_MAX_ENQ_DEPTH "max_enqueue_depth" #define DLB2_CQ_WEIGHT "cq_weight" #define DLB2_PORT_COS "port_cos" #define DLB2_COS_BW "cos_bw" @@ -585,6 +589,7 @@ struct dlb2_eventdev { int num_dir_credits_override; bool vector_opts_enabled; int max_cq_depth; + int max_enq_depth; volatile enum dlb2_run_state run_state; uint16_t num_dir_queues; /* total num of evdev dir queues requested */ union { @@ -660,6 +665,7 @@ struct dlb2_devargs { int default_depth_thresh; bool vector_opts_enabled; int max_cq_depth; + int max_enq_depth; struct dlb2_cq_weight cq_weight; struct dlb2_port_cos port_cos; struct dlb2_cos_bw cos_bw; diff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c index 0627f06a6e..086d4a1cc7 100644 --- a/drivers/event/dlb2/pf/dlb2_pf.c +++ b/drivers/event/dlb2/pf/dlb2_pf.c @@ -708,7 +708,8 @@ dlb2_eventdev_pci_init(struct rte_eventdev *eventdev) .sw_credit_quanta = DLB2_SW_CREDIT_QUANTA_DEFAULT, .hw_credit_quanta = DLB2_SW_CREDIT_BATCH_SZ, .default_depth_thresh = DLB2_DEPTH_THRESH_DEFAULT, - .max_cq_depth = DLB2_DEFAULT_CQ_DEPTH + .max_cq_depth = DLB2_DEFAULT_CQ_DEPTH, + .max_enq_depth = DLB2_MAX_ENQUEUE_DEPTH }; struct dlb2_eventdev *dlb2; From patchwork Sat Jul 2 16:22:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy McDaniel X-Patchwork-Id: 113647 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9CA49A0093; Sat, 2 Jul 2022 18:23:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C9D3342B75; Sat, 2 Jul 2022 18:22:48 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 56E7640E50 for ; Sat, 2 Jul 2022 18:22:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656778964; x=1688314964; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QAjyIPKfUUm+lxGGmZpwpo2XscdDaowb4VrZ9oWj7K4=; b=ZNQ+1JRfPDBarFy54QdMHSl8r1g0Dq65AjWbDD8m5ANHhabhHL3orQoV NbLDrEPC83spJ3kJCzTexI7ingjXWAqTquMoSQpniLbIgHsy9FCFX7h0F cByOU4pH050TazliUk++pjWWUT1UiVwMw5pEYZmSuc6hXmUykBebgSM2C +vBLnqIokqf5235cmZ/UA4aBWPPnUvRrwZsIHx+OKt2yshgmYNXpFkjWR cL3zW7SkdcDpohfm0fr6I4MmDn3k3Xj6zm0notdPUxoCLhoVWu3xarFUm sdMwcNA787H5Qi4Mu3C1Xps0zq/avPMmdY5QwYCd5+pWsxhysLvPrsTnG Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10396"; a="283957278" X-IronPort-AV: E=Sophos;i="5.92,240,1650956400"; d="scan'208";a="283957278" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2022 09:22:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,240,1650956400"; d="scan'208";a="648781633" Received: from txanpdk03.an.intel.com ([10.123.117.78]) by fmsmga008.fm.intel.com with ESMTP; 02 Jul 2022 09:22:42 -0700 From: Timothy McDaniel To: jerinj@marvell.com Cc: dev@dpdk.org, timothy.mcdaniel@intel.com Subject: [PATCH v3 5/5] event/dlb2: fix port COS initialization Date: Sat, 2 Jul 2022 11:22:39 -0500 Message-Id: <20220702162239.1646548-6-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20220702162239.1646548-1-timothy.mcdaniel@intel.com> References: <20220629153638.1269743-1-timothy.mcdaniel@intel.com> <20220702162239.1646548-1-timothy.mcdaniel@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix cos initialization, handling the default case too. Substitute the semicolon for the comma that was expected in the cos_bw command line override. Commas are not allowed within a multifield option. The new format is cos_bw=%d:%d:%d:%d, where the sum of the 4 decimal values must be less than or equal to 100. Corrected probe-time initialization order. Fixes: bec8901bfe9f ("event/dlb2: support ldb port specific COS") Cc: timothy.mcdaniel@intel.com Signed-off-by: Timothy McDaniel --- drivers/event/dlb2/dlb2.c | 63 ++++++++++++---------- drivers/event/dlb2/pf/base/dlb2_resource.c | 3 -- drivers/event/dlb2/pf/dlb2_pf.c | 4 ++ 3 files changed, 39 insertions(+), 31 deletions(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index 8a68c25c93..26af75beb8 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -170,10 +170,11 @@ dlb2_init_port_cos(struct dlb2_eventdev *dlb2, int *port_cos) { int q; - for (q = 0; q < DLB2_MAX_NUM_PORTS_ALL; q++) { - dlb2->ev_ports[q].cos_id = port_cos[q]; - dlb2->cos_ports[port_cos[q]]++; - } + for (q = 0; q < DLB2_MAX_NUM_PORTS_ALL; q++) + if (port_cos[q] != DLB2_COS_DEFAULT) { + dlb2->ev_ports[q].cos_id = port_cos[q]; + dlb2->cos_ports[port_cos[q]]++; + } } static void @@ -181,6 +182,17 @@ dlb2_init_cos_bw(struct dlb2_eventdev *dlb2, struct dlb2_cos_bw *cos_bw) { int q; + + + /* If cos_bw not set, then split evenly */ + if (cos_bw->val[0] == 0 && cos_bw->val[1] == 0 && + cos_bw->val[2] == 0 && cos_bw->val[3] == 0) { + cos_bw->val[0] = 25; + cos_bw->val[1] = 25; + cos_bw->val[2] = 25; + cos_bw->val[3] = 25; + } + for (q = 0; q < DLB2_COS_NUM_VALS; q++) dlb2->cos_bw[q] = cos_bw->val[q]; @@ -464,19 +476,15 @@ set_port_cos(const char *key __rte_unused, } /* command line override may take one of the following 3 forms: - * port_cos=all: ... all ports * port_cos=port-port: ... a range of ports * port_cos=port: ... just one port */ - if (sscanf(value, "all:%d", &cos_id) == 1) { - first = 0; - last = DLB2_MAX_NUM_LDB_PORTS - 1; - } else if (sscanf(value, "%d-%d:%d", &first, &last, &cos_id) == 3) { + if (sscanf(value, "%d-%d:%d", &first, &last, &cos_id) == 3) { /* we have everything we need */ } else if (sscanf(value, "%d:%d", &first, &cos_id) == 2) { last = first; } else { - DLB2_LOG_ERR("Error parsing ldb port port_cos devarg. Should be all:val, port-port:val, or port:val\n"); + DLB2_LOG_ERR("Error parsing ldb port port_cos devarg. Should be port-port:val, or port:val\n"); return -EINVAL; } @@ -511,13 +519,13 @@ set_cos_bw(const char *key __rte_unused, /* format must be %d,%d,%d,%d */ - if (sscanf(value, "%d,%d,%d,%d", &cos_bw->val[0], &cos_bw->val[1], + if (sscanf(value, "%d:%d:%d:%d", &cos_bw->val[0], &cos_bw->val[1], &cos_bw->val[2], &cos_bw->val[3]) != 4) { - DLB2_LOG_ERR("Error parsing cos bandwidth devarg. Should be bw0,bw1,bw2,bw3 where all values combined are <= 100\n"); + DLB2_LOG_ERR("Error parsing cos bandwidth devarg. Should be bw0:bw1:bw2:bw3 where all values combined are <= 100\n"); return -EINVAL; } if (cos_bw->val[0] + cos_bw->val[1] + cos_bw->val[2] + cos_bw->val[3] > 100) { - DLB2_LOG_ERR("Error parsing cos bandwidth devarg. Should be bw0,bw1,bw2,bw3 where all values combined are <= 100\n"); + DLB2_LOG_ERR("Error parsing cos bandwidth devarg. Should be bw0:bw1:bw2:bw3 where all values combined are <= 100\n"); return -EINVAL; } @@ -781,9 +789,9 @@ dlb2_hw_create_sched_domain(struct dlb2_eventdev *dlb2, /* LDB ports */ - /* tally of ports with non default COS */ - cos_ports = dlb2->cos_ports[1] + dlb2->cos_ports[2] + - dlb2->cos_ports[3]; + /* tally of COS ports from cmd line */ + cos_ports = dlb2->cos_ports[0] + dlb2->cos_ports[1] + + dlb2->cos_ports[2] + dlb2->cos_ports[3]; if (cos_ports > resources_asked->num_ldb_ports) { DLB2_LOG_ERR("dlb2: num_ldb_ports < nonzero cos_ports\n"); @@ -4552,6 +4560,17 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev, evdev_dlb2_default_info.max_event_port_enqueue_depth = dlb2->max_enq_depth; + dlb2_init_queue_depth_thresholds(dlb2, + dlb2_args->qid_depth_thresholds.val); + + dlb2_init_cq_weight(dlb2, + dlb2_args->cq_weight.limit); + + dlb2_init_port_cos(dlb2, + dlb2_args->port_cos.cos_id); + + dlb2_init_cos_bw(dlb2, + &dlb2_args->cos_bw); err = dlb2_iface_open(&dlb2->qm_instance, name); if (err < 0) { @@ -4623,18 +4642,6 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev, dlb2_entry_points_init(dev); - dlb2_init_queue_depth_thresholds(dlb2, - dlb2_args->qid_depth_thresholds.val); - - dlb2_init_cq_weight(dlb2, - dlb2_args->cq_weight.limit); - - dlb2_init_port_cos(dlb2, - dlb2_args->port_cos.cos_id); - - dlb2_init_cos_bw(dlb2, - &dlb2_args->cos_bw); - return 0; } diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c index da1949c763..e73d289445 100644 --- a/drivers/event/dlb2/pf/base/dlb2_resource.c +++ b/drivers/event/dlb2/pf/base/dlb2_resource.c @@ -236,9 +236,6 @@ int dlb2_resource_init(struct dlb2_hw *hw, enum dlb2_hw_ver ver) hw->rsrcs.sn_groups[i].slot_use_bitmap = 0; } - for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) - hw->cos_reservation[i] = 100 / DLB2_NUM_COS_DOMAINS; - return 0; unwind: diff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c index 086d4a1cc7..dd3f2b8ece 100644 --- a/drivers/event/dlb2/pf/dlb2_pf.c +++ b/drivers/event/dlb2/pf/dlb2_pf.c @@ -712,10 +712,14 @@ dlb2_eventdev_pci_init(struct rte_eventdev *eventdev) .max_enq_depth = DLB2_MAX_ENQUEUE_DEPTH }; struct dlb2_eventdev *dlb2; + int q; DLB2_LOG_DBG("Enter with dev_id=%d socket_id=%d", eventdev->data->dev_id, eventdev->data->socket_id); + for (q = 0; q < DLB2_MAX_NUM_PORTS_ALL; q++) + dlb2_args.port_cos.cos_id[q] = DLB2_COS_DEFAULT; + dlb2_pf_iface_fn_ptrs_init(); pci_dev = RTE_DEV_TO_PCI(eventdev->dev);