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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF00010207.mail.protection.outlook.com (10.167.241.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5944.8 via Frontend Transport; Wed, 21 Dec 2022 08:43:35 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 21 Dec 2022 00:43:22 -0800 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 21 Dec 2022 00:43:19 -0800 From: Rongwei Liu To: , , , , Ferruh Yigit , Andrew Rybchenko , Olivier Matz CC: , Subject: [RFC 1/9] ethdev: add IPv6 routing extension header definition Date: Wed, 21 Dec 2022 10:42:56 +0200 Message-ID: <20221221084304.3680690-2-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221221084304.3680690-1-rongweil@nvidia.com> References: <20221221084304.3680690-1-rongweil@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00010207:EE_|SA0PR12MB4589:EE_ X-MS-Office365-Filtering-Correlation-Id: 703bb563-4fe5-4788-d649-08dae32f72dc X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2022 08:43:35.4357 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 703bb563-4fe5-4788-d649-08dae32f72dc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00010207.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4589 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add IPv6 routing extension header definition and no TLV support for now. At rte_flow layer, there are new items defined for matching type/nexthdr/segment_left field. Signed-off-by: Rongwei Liu --- doc/guides/prog_guide/rte_flow.rst | 9 ++++++ doc/guides/rel_notes/release_22_03.rst | 5 ++++ lib/ethdev/rte_flow.c | 15 ++++++++++ lib/ethdev/rte_flow.h | 39 ++++++++++++++++++++++++++ lib/net/rte_ip.h | 21 ++++++++++++++ 5 files changed, 89 insertions(+) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index 3e6242803d..1ebc159893 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -1544,6 +1544,15 @@ Matches Color Marker set by a Meter. - ``color``: Metering color marker. +Item: ``IPV6_ROUTING_EXT`` +^^^^^^^^^^^^^^^^^^^^^ + +Matches ipv6 routing extension header. + +- ``nexthdr``: Next layer header type. +- ``type``: IPv6 routing extension header type. +- ``segments_left``: How many IPv6 destination addresses carries on + Actions ~~~~~~~ diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst index 0923707cb8..cc050ff3e7 100644 --- a/doc/guides/rel_notes/release_22_03.rst +++ b/doc/guides/rel_notes/release_22_03.rst @@ -207,6 +207,11 @@ API Changes * ethdev: Old public macros and enumeration constants without ``RTE_ETH_`` prefix, which are kept for backward compatibility, are marked as deprecated. +* ethdev: added a new structure: + + - IPv6 routing extension header ``rte_flow_item_ipv6_routing_ext`` and + ``rte_ipv6_routing_ext`` + * cryptodev: The asymmetric session handling was modified to use a single mempool object. An API ``rte_cryptodev_asym_session_pool_create`` was added to create a mempool with element size big enough to hold the generic asymmetric diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c index 7d0c24366c..e08b690300 100644 --- a/lib/ethdev/rte_flow.c +++ b/lib/ethdev/rte_flow.c @@ -76,6 +76,19 @@ rte_flow_item_flex_conv(void *buf, const void *data) return src->length; } +static size_t +rte_flow_item_ipv6_routing_ext_conv(void *buf, const void *data) +{ + struct rte_flow_item_ipv6_routing_ext *dst = buf; + const struct rte_flow_item_ipv6_routing_ext *src = data; + + if (buf) + rte_memcpy((void *)((uintptr_t)(dst->hdr.segments)), + src->hdr.segments, + src->hdr.segments_left << 4); + return src->hdr.segments_left << 4; +} + /** Generate flow_item[] entry. */ #define MK_FLOW_ITEM(t, s) \ [RTE_FLOW_ITEM_TYPE_ ## t] = { \ @@ -157,6 +170,8 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = { MK_FLOW_ITEM(L2TPV2, sizeof(struct rte_flow_item_l2tpv2)), MK_FLOW_ITEM(PPP, sizeof(struct rte_flow_item_ppp)), MK_FLOW_ITEM(METER_COLOR, sizeof(struct rte_flow_item_meter_color)), + MK_FLOW_ITEM_FN(IPV6_ROUTING_EXT, sizeof(struct rte_flow_item_ipv6_routing_ext), + rte_flow_item_ipv6_routing_ext_conv), }; /** Generate flow_action[] entry. */ diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h index b60987db4b..f8f1d6f9dd 100644 --- a/lib/ethdev/rte_flow.h +++ b/lib/ethdev/rte_flow.h @@ -624,6 +624,33 @@ enum rte_flow_item_type { * See struct rte_flow_item_meter_color. */ RTE_FLOW_ITEM_TYPE_METER_COLOR, + /** + * Matches the presence of IPv6 routing extension header. + * + * See struct rte_flow_item_ipv6_routing_ext. + */ + RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT, + + /** + * Matches IPv6 routing extension header next header. + * + * See struct rte_flow_item_ipv6_routing_ext. + */ + RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT_NEXT_HDR, + + /** + * Matches IPv6 routing extension header type. + * + * See struct rte_flow_item_ipv6_routing_ext. + */ + RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT_TYPE, + + /** + * Matches IPv6 routing extension header segment left. + * + * See struct rte_flow_item_ipv6_routing_ext. + */ + RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT_SEG_LEFT, }; /** @@ -873,6 +900,18 @@ struct rte_flow_item_ipv6 { uint32_t reserved:23; }; +/** + * @warning + * @b EXPERIMENTAL: this structure may change without prior notice + * + * RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT. + * + * Matches an IPv6 routing extension header. + */ +struct rte_flow_item_ipv6_routing_ext { + struct rte_ipv6_routing_ext hdr; +}; + /** Default mask for RTE_FLOW_ITEM_TYPE_IPV6. */ #ifndef __cplusplus static const struct rte_flow_item_ipv6 rte_flow_item_ipv6_mask = { diff --git a/lib/net/rte_ip.h b/lib/net/rte_ip.h index 9c8e8206f0..2b9a65dfcb 100644 --- a/lib/net/rte_ip.h +++ b/lib/net/rte_ip.h @@ -539,6 +539,27 @@ struct rte_ipv6_hdr { uint8_t dst_addr[16]; /**< IP address of destination host(s). */ } __rte_packed; +/** + * IPv6 Routing Extension Header + */ +struct rte_ipv6_routing_ext { + uint8_t nexthdr; /**< Protocol, next header. */ + uint8_t hdrlen; /**< Header length. */ + uint8_t type; /**< Extension header type. */ + uint8_t segments_left; /**< Valid segments number. */ + __extension__ + union { + uint32_t flags; + struct { + uint8_t last_entry; /**< The last_entry field of SRH */ + uint8_t flag; /**< Packet flag. */ + uint16_t tag; /**< Packet tag. */ + }; + }; + __extension__ + uint32_t segments[0]; /**< Each hop IPv6 address. */ +} __rte_packed; + /* IPv6 vtc_flow: IPv / TC / flow_label */ #define RTE_IPV6_HDR_FL_SHIFT 0 #define RTE_IPV6_HDR_TC_SHIFT 20 From patchwork Wed Dec 21 08:42:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: rongwei liu X-Patchwork-Id: 121182 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A2506A034C; Wed, 21 Dec 2022 09:43:38 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1791541141; Wed, 21 Dec 2022 09:43:38 +0100 (CET) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2089.outbound.protection.outlook.com [40.107.220.89]) by mails.dpdk.org (Postfix) with ESMTP id B844241141 for ; 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Signed-off-by: Rongwei Liu --- app/test-pmd/cmdline_flow.c | 41 ++++++++++++++++++++++++++ doc/guides/rel_notes/release_22_03.rst | 6 ++++ 2 files changed, 47 insertions(+) diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c index 88108498e0..70685aafb1 100644 --- a/app/test-pmd/cmdline_flow.c +++ b/app/test-pmd/cmdline_flow.c @@ -298,6 +298,10 @@ enum index { ITEM_IPV6_SRC, ITEM_IPV6_DST, ITEM_IPV6_HAS_FRAG_EXT, + ITEM_IPV6_ROUTING_EXT, + ITEM_IPV6_ROUTING_EXT_TYPE, + ITEM_IPV6_ROUTING_EXT_NEXT_HDR, + ITEM_IPV6_ROUTING_EXT_SEG_LEFT, ITEM_ICMP, ITEM_ICMP_TYPE, ITEM_ICMP_CODE, @@ -1326,6 +1330,7 @@ static const enum index next_item[] = { ITEM_ARP_ETH_IPV4, ITEM_IPV6_EXT, ITEM_IPV6_FRAG_EXT, + ITEM_IPV6_ROUTING_EXT, ITEM_ICMP6, ITEM_ICMP6_ND_NS, ITEM_ICMP6_ND_NA, @@ -1435,6 +1440,10 @@ static const enum index item_ipv6[] = { ITEM_IPV6_SRC, ITEM_IPV6_DST, ITEM_IPV6_HAS_FRAG_EXT, + ITEM_IPV6_ROUTING_EXT, + ITEM_IPV6_ROUTING_EXT_TYPE, + ITEM_IPV6_ROUTING_EXT_NEXT_HDR, + ITEM_IPV6_ROUTING_EXT_SEG_LEFT, ITEM_NEXT, ZERO, }; @@ -3844,6 +3853,38 @@ static const struct token token_list[] = { .args = ARGS(ARGS_ENTRY_BF(struct rte_flow_item_ipv6, has_frag_ext, 1)), }, + [ITEM_IPV6_ROUTING_EXT] = { + .name = "ipv6_routing_ext", + .help = "match IPv6 routing extension header", + .priv = PRIV_ITEM(IPV6_ROUTING_EXT, + sizeof(struct rte_flow_item_ipv6_routing_ext)), + .next = NEXT(item_ipv6), + .call = parse_vc, + }, + [ITEM_IPV6_ROUTING_EXT_TYPE] = { + .name = "ipv6_routing_ext_type", + .help = "match IPv6 routing extension header type", + .next = NEXT(item_ipv6, NEXT_ENTRY(COMMON_UNSIGNED), + item_param), + .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_ipv6_routing_ext, + hdr.type)), + }, + [ITEM_IPV6_ROUTING_EXT_NEXT_HDR] = { + .name = "ipv6_routing_ext_next_hdr", + .help = "match IPv6 routing extension header next header type", + .next = NEXT(item_ipv6, NEXT_ENTRY(COMMON_UNSIGNED), + item_param), + .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_ipv6_routing_ext, + hdr.nexthdr)), + }, + [ITEM_IPV6_ROUTING_EXT_SEG_LEFT] = { + .name = "ipv6_routing_ext_seg_left", + .help = "match IPv6 routing extension header segment left", + .next = NEXT(item_ipv6, NEXT_ENTRY(COMMON_UNSIGNED), + item_param), + .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_ipv6_routing_ext, + hdr.segments_left)), + }, [ITEM_ICMP] = { .name = "icmp", .help = "match ICMP header", diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst index cc050ff3e7..6208f2677c 100644 --- a/doc/guides/rel_notes/release_22_03.rst +++ b/doc/guides/rel_notes/release_22_03.rst @@ -58,6 +58,12 @@ New Features Added ``gre_option`` item in rte_flow to support checksum/key/sequence matching in GRE packets. +* **Added rte_flow support for matching IPv6 routing extension header fields.** + + Added ``ipv6_routing_ext`` ``ipv6_routing_ext_type`` ``ipv6_routing_ext_seg_left`` + and ``ipv6_routing_ext_next_hdr`` items in rte_flow to match IPv6 routing extension + header. + * **Added new RSS offload types for L2TPv2 in RSS flow.** Added ``RTE_ETH_RSS_L2TPV2`` macro so that he L2TPv2 session ID field can be used as From patchwork Wed Dec 21 08:42:58 2022 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2022 08:43:36.3106 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0cd6b11-c285-4f0e-8bb5-08dae32f735d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT077.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6861 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Per newest PRM definition, sample_id stands for 3 parts of information instead of single uint32_t id: sample_id + modify_filed_id + formate_select_dw. Also new FW capability bits have been introduces to identify the new capability. Signed-off-by: Rongwei Liu --- drivers/common/mlx5/mlx5_devx_cmds.c | 13 +++++++++++-- drivers/common/mlx5/mlx5_devx_cmds.h | 7 ++++++- drivers/common/mlx5/mlx5_prm.h | 22 ++++++++++++++++++++-- drivers/net/mlx5/mlx5.c | 15 +++++++++++---- drivers/net/mlx5/mlx5.h | 3 ++- drivers/net/mlx5/mlx5_flow_flex.c | 14 +++++++++++--- 6 files changed, 61 insertions(+), 13 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 59cebb530f..ccd03e2a94 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -607,7 +607,8 @@ mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, - uint32_t ids[], uint32_t num) + struct mlx5_ext_sample_id ids[], + uint32_t num, uint8_t *anchor) { uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; @@ -636,6 +637,7 @@ mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, (void *)flex_obj); return -rte_errno; } + *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { void *s_off = (void *)((char *)sample + i * MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); @@ -645,8 +647,9 @@ mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, flow_match_sample_en); if (!en) continue; - ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, + ids[idx++].id = MLX5_GET(parse_graph_flow_match_sample, s_off, flow_match_sample_field_id); + printf("id index %d val %x\n", idx - 1, ids[idx-1].id); } if (num != idx) { rte_errno = EINVAL; @@ -794,6 +797,12 @@ mlx5_devx_cmd_query_hca_parse_graph_node_cap max_num_arc_out); attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, max_num_sample); + attr->anchor_en = MLX5_GET(parse_graph_node_cap, hcattr, anchor_en); + attr->ext_sample_id = MLX5_GET(parse_graph_node_cap, hcattr, ext_sample_id); + attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, + sample_tunnel_inner2); + attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, + zero_size_supported); attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, sample_id_in_out); attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index c94b9eac06..5b33010155 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -114,6 +114,10 @@ struct mlx5_hca_flex_attr { uint8_t max_num_arc_out; uint8_t max_num_sample; uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ + uint8_t anchor_en:1; + uint8_t ext_sample_id:1; + uint8_t sample_tunnel_inner2:1; + uint8_t zero_size_supported:1; uint8_t sample_id_in_out:1; uint16_t max_base_header_length; uint8_t max_sample_base_offset; @@ -706,7 +710,8 @@ int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, struct mlx5_devx_modify_tir_attr *tir_attr); __rte_internal int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, - uint32_t ids[], uint32_t num); + struct mlx5_ext_sample_id ids[], + uint32_t num, uint8_t *anchor); __rte_internal struct mlx5_devx_obj * diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 2b5c43ee6e..1545b929b6 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1890,7 +1890,11 @@ struct mlx5_ifc_parse_graph_node_cap_bits { u8 max_num_arc_in[0x08]; u8 max_num_arc_out[0x08]; u8 max_num_sample[0x08]; - u8 reserved_at_78[0x07]; + u8 reserved_at_78[0x03]; + u8 anchor_en[0x1]; + u8 ext_sample_id[0x1]; + u8 sample_tunnel_inner2[0x1]; + u8 zero_size_supported[0x1]; u8 sample_id_in_out[0x1]; u8 max_base_header_length[0x10]; u8 reserved_at_90[0x08]; @@ -1900,6 +1904,18 @@ struct mlx5_ifc_parse_graph_node_cap_bits { u8 header_length_mask_width[0x08]; }; +/* ext_sample_id structure, see PRM Table 539. */ +struct mlx5_ext_sample_id { + union { + struct { + uint32_t format_select_dw:8; + uint32_t modify_field_id:12; + uint32_t sample_id:12; + }; + uint32_t id; + }; +}; + struct mlx5_ifc_flow_table_prop_layout_bits { u8 ft_support[0x1]; u8 flow_tag[0x1]; @@ -4455,7 +4471,9 @@ struct mlx5_ifc_parse_graph_flex_bits { u8 header_length_mode[0x4]; u8 header_length_field_offset[0x10]; u8 next_header_field_offset[0x10]; - u8 reserved_at_160[0x1b]; + u8 reserved_at_160[0x12]; + u8 head_anchor_id[0x6]; + u8 reserved_at_178[0x3]; u8 next_header_field_size[0x5]; u8 header_length_field_mask[0x20]; u8 reserved_at_224[0x20]; diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index e55be8720e..04b641aa75 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -964,11 +964,13 @@ int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) { struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex; struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; struct mlx5_devx_graph_node_attr node = { .modify_field_select = 0, }; - uint32_t ids[8]; + struct mlx5_ext_sample_id ids[8]; + uint8_t anchor_id; int ret; if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) { @@ -1004,15 +1006,20 @@ mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) return (rte_errno == 0) ? -ENODEV : -rte_errno; } prf->num = 2; - ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num); + ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num, &anchor_id); if (ret) { DRV_LOG(ERR, "Failed to query sample IDs."); return (rte_errno == 0) ? -ENODEV : -rte_errno; } prf->offset[0] = 0x0; prf->offset[1] = sizeof(uint32_t); - prf->ids[0] = ids[0]; - prf->ids[1] = ids[1]; + if (attr->ext_sample_id) { + prf->ids[0] = ids[0].sample_id; + prf->ids[1] = ids[1].sample_id; + } else { + prf->ids[0] = ids[0].id; + prf->ids[1] = ids[1].id; + } return 0; } diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 31982002ee..1c11b77ac3 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1307,9 +1307,10 @@ struct mlx5_lag { struct mlx5_flex_parser_devx { struct mlx5_list_entry entry; /* List element at the beginning. */ uint32_t num_samples; + uint8_t anchor_id; void *devx_obj; struct mlx5_devx_graph_node_attr devx_conf; - uint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; + struct mlx5_ext_sample_id sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; }; /* Pattern field descriptor - how to translate flex pattern into samples. */ diff --git a/drivers/net/mlx5/mlx5_flow_flex.c b/drivers/net/mlx5/mlx5_flow_flex.c index fb08910ddb..35f2a9923d 100644 --- a/drivers/net/mlx5/mlx5_flow_flex.c +++ b/drivers/net/mlx5/mlx5_flow_flex.c @@ -226,15 +226,18 @@ mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_4); void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4); + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex; struct mlx5_flex_item *tp; uint32_t i, pos = 0; + uint32_t sample_id; RTE_SET_USED(dev); MLX5_ASSERT(item->spec && item->mask); spec = item->spec; mask = item->mask; tp = (struct mlx5_flex_item *)spec->handle; - MLX5_ASSERT(mlx5_flex_index(dev->data->dev_private, tp) >= 0); + MLX5_ASSERT(mlx5_flex_index(priv, tp) >= 0); for (i = 0; i < tp->mapnum; i++) { struct mlx5_flex_pattern_field *map = tp->map + i; uint32_t id = map->reg_id; @@ -257,9 +260,13 @@ mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, MLX5_ASSERT(id < num_samples); id += num_samples; } + if (attr->ext_sample_id) + sample_id = tp->devx_fp->sample_ids[id].sample_id; + else + sample_id = tp->devx_fp->sample_ids[id].id; mlx5_flex_set_match_sample(misc4_m, misc4_v, def, msk & def, val & msk & def, - tp->devx_fp->sample_ids[id], id); + sample_id, id); pos += map->width; } } @@ -1298,7 +1305,8 @@ mlx5_flex_parser_create_cb(void *list_ctx, void *ctx) /* Query the firmware assigned sample ids. */ ret = mlx5_devx_cmd_query_parse_samples(fp->devx_obj, fp->sample_ids, - fp->num_samples); + fp->num_samples, + &fp->anchor_id); if (ret) goto error; DRV_LOG(DEBUG, "DEVx flex parser %p created, samples num: %u", From patchwork Wed Dec 21 08:42:59 2022 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2022 08:43:40.9086 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8271ffba-4072-46ee-f0b6-08dae32f761f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00010209.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7101 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org New mlx5dr_context member replaces mlx5dr_cmd_query_caps. Capabilities structure is a member of mlx5dr_context. Signed-off-by: Gregory Etelson Signed-off-by: Rongwei Liu --- drivers/net/mlx5/hws/mlx5dr_definer.c | 41 ++++++++++++++------------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 6b98eb8c96..10b1e43d6e 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -100,7 +100,7 @@ struct mlx5dr_definer_sel_ctrl { }; struct mlx5dr_definer_conv_data { - struct mlx5dr_cmd_query_caps *caps; + struct mlx5dr_context *ctx; struct mlx5dr_definer_fc *fc; uint8_t relaxed; uint8_t tunnel; @@ -815,6 +815,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, int item_idx) { + struct mlx5dr_cmd_query_caps *caps = cd->ctx->caps; const struct rte_flow_item_gtp *m = item->mask; struct mlx5dr_definer_fc *fc; @@ -836,7 +837,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, } if (m->teid) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_TEID_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_TEID_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -844,11 +845,11 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_gtp_teid_set; fc->bit_mask = __mlx5_mask(header_gtp, teid); - fc->byte_off = cd->caps->format_select_gtpu_dw_1 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_1 * DW_SIZE; } if (m->v_pt_rsv_flags) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -857,12 +858,12 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_ext_flag_set; fc->bit_mask = __mlx5_mask(header_gtp, ext_hdr_flag); fc->bit_off = __mlx5_dw_bit_off(header_gtp, ext_hdr_flag); - fc->byte_off = cd->caps->format_select_gtpu_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE; } if (m->msg_type) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -871,7 +872,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_msg_type_set; fc->bit_mask = __mlx5_mask(header_gtp, msg_type); fc->bit_off = __mlx5_dw_bit_off(header_gtp, msg_type); - fc->byte_off = cd->caps->format_select_gtpu_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE; } return 0; @@ -882,12 +883,13 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, int item_idx) { + struct mlx5dr_cmd_query_caps *caps = cd->ctx->caps; const struct rte_flow_item_gtp_psc *m = item->mask; struct mlx5dr_definer_fc *fc; /* Overwrite GTP extension flag to be 1 */ if (!cd->relaxed) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -896,12 +898,12 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_ones_set; fc->bit_mask = __mlx5_mask(header_gtp, ext_hdr_flag); fc->bit_off = __mlx5_dw_bit_off(header_gtp, ext_hdr_flag); - fc->byte_off = cd->caps->format_select_gtpu_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE; } /* Overwrite next extension header type */ if (!cd->relaxed) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_2_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_2_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -911,14 +913,14 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_mask_set = &mlx5dr_definer_ones_set; fc->bit_mask = __mlx5_mask(header_opt_gtp, next_ext_hdr_type); fc->bit_off = __mlx5_dw_bit_off(header_opt_gtp, next_ext_hdr_type); - fc->byte_off = cd->caps->format_select_gtpu_dw_2 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_2 * DW_SIZE; } if (!m) return 0; if (m->hdr.type) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -927,11 +929,11 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_ext_hdr_pdu_set; fc->bit_mask = __mlx5_mask(header_gtp_psc, pdu_type); fc->bit_off = __mlx5_dw_bit_off(header_gtp_psc, pdu_type); - fc->byte_off = cd->caps->format_select_gtpu_ext_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_ext_dw_0 * DW_SIZE; } if (m->hdr.qfi) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -940,7 +942,7 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_ext_hdr_qfi_set; fc->bit_mask = __mlx5_mask(header_gtp_psc, qfi); fc->bit_off = __mlx5_dw_bit_off(header_gtp_psc, qfi); - fc->byte_off = cd->caps->format_select_gtpu_ext_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_ext_dw_0 * DW_SIZE; } return 0; @@ -951,18 +953,19 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, int item_idx) { + struct mlx5dr_cmd_query_caps *caps = cd->ctx->caps; const struct rte_flow_item_ethdev *m = item->mask; struct mlx5dr_definer_fc *fc; uint8_t bit_offset = 0; if (m->port_id) { - if (!cd->caps->wire_regc_mask) { + if (!caps->wire_regc_mask) { DR_LOG(ERR, "Port ID item not supported, missing wire REGC mask"); rte_errno = ENOTSUP; return rte_errno; } - while (!(cd->caps->wire_regc_mask & (1 << bit_offset))) + while (!(caps->wire_regc_mask & (1 << bit_offset))) bit_offset++; fc = &cd->fc[MLX5DR_DEFINER_FNAME_VPORT_REG_C_0]; @@ -971,7 +974,7 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd, fc->tag_mask_set = &mlx5dr_definer_ones_set; DR_CALC_SET_HDR(fc, registers, register_c_0); fc->bit_off = bit_offset; - fc->bit_mask = cd->caps->wire_regc_mask >> bit_offset; + fc->bit_mask = caps->wire_regc_mask >> bit_offset; } else { DR_LOG(ERR, "Pord ID item mask must specify ID mask"); rte_errno = EINVAL; @@ -1480,7 +1483,7 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, cd.fc = fc; cd.hl = hl; - cd.caps = ctx->caps; + cd.ctx = ctx; cd.relaxed = mt->flags & MLX5DR_MATCH_TEMPLATE_FLAG_RELAXED_MATCH; /* Collect all RTE fields to the field array and set header layout */ From patchwork Wed Dec 21 08:43:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: rongwei liu X-Patchwork-Id: 121186 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 25EAAA034C; Wed, 21 Dec 2022 09:44:04 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6C8F942D3E; Wed, 21 Dec 2022 09:43:47 +0100 (CET) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2048.outbound.protection.outlook.com [40.107.244.48]) by mails.dpdk.org (Postfix) with ESMTP id C2EAD42D32 for ; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2022 08:43:43.1899 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a97ea8c8-e7e8-442e-664f-08dae32f777e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00010209.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6276 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add mlx5 HWS logic to match IPv6 routing extension header. Once detecting IPv6 matching extension items in pattern template create callback, PMD allocates a flex parser to sample the first dword of srv6 header. Only support next_hdr/segments_left/type for now. Signed-off-by: Rongwei Liu --- doc/guides/nics/features/mlx5.ini | 1 + doc/guides/nics/mlx5.rst | 1 + drivers/net/mlx5/hws/mlx5dr.h | 21 ++++++ drivers/net/mlx5/hws/mlx5dr_context.c | 81 +++++++++++++++++++- drivers/net/mlx5/hws/mlx5dr_context.h | 1 + drivers/net/mlx5/hws/mlx5dr_definer.c | 103 ++++++++++++++++++++++++++ drivers/net/mlx5/mlx5.h | 10 +++ drivers/net/mlx5/mlx5_flow.h | 3 + drivers/net/mlx5/mlx5_flow_hw.c | 39 ++++++++-- 9 files changed, 250 insertions(+), 10 deletions(-) diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini index 62fd330e2b..bd911a467b 100644 --- a/doc/guides/nics/features/mlx5.ini +++ b/doc/guides/nics/features/mlx5.ini @@ -87,6 +87,7 @@ vlan = Y vxlan = Y vxlan_gpe = Y represented_port = Y +ipv6_routing_ext = Y [rte_flow actions] age = I diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 51f51259e3..98dcf9af16 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -106,6 +106,7 @@ Features - Sub-Function representors. - Sub-Function. - Matching on represented port. +- Matching on IPv6 routing extension header. Limitations diff --git a/drivers/net/mlx5/hws/mlx5dr.h b/drivers/net/mlx5/hws/mlx5dr.h index f8de27c615..ba1566de9f 100644 --- a/drivers/net/mlx5/hws/mlx5dr.h +++ b/drivers/net/mlx5/hws/mlx5dr.h @@ -592,4 +592,25 @@ int mlx5dr_send_queue_action(struct mlx5dr_context *ctx, */ int mlx5dr_debug_dump(struct mlx5dr_context *ctx, FILE *f); +/* Allocate an internal flex parser for srv6 option. + * + * @param[in] dr_ctx + * The dr_context which the flex parser belongs to. + * @param[in] config + * Devx configuration per port. + * @param[in] ctx + * Device contex + * @return zero on success non zero otherwise. + */ +int mlx5dr_alloc_srh_flex_parser(struct mlx5dr_context *dr_ctx, + struct mlx5_common_dev_config *config, + void *ctx); + +/* Free srv6 flex parser. + * + * @param[in] dr_ctx + * The dr_context which the flex parser belongs to. + * @return zero on success non zero otherwise. + */ +int mlx5dr_free_srh_flex_parser(struct mlx5dr_context *dr_ctx); #endif diff --git a/drivers/net/mlx5/hws/mlx5dr_context.c b/drivers/net/mlx5/hws/mlx5dr_context.c index 76ada7bb7f..6329271ff6 100644 --- a/drivers/net/mlx5/hws/mlx5dr_context.c +++ b/drivers/net/mlx5/hws/mlx5dr_context.c @@ -178,6 +178,76 @@ static void mlx5dr_context_uninit_hws(struct mlx5dr_context *ctx) mlx5dr_context_uninit_pd(ctx); } +int mlx5dr_alloc_srh_flex_parser(struct mlx5dr_context *dr_ctx, + struct mlx5_common_dev_config *config, + void *ctx) +{ + struct mlx5_devx_graph_node_attr node = { + .modify_field_select = 0, + }; + struct mlx5_ext_sample_id ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; + int ret; + + memset(ids, 0xff, sizeof(ids)); + if (!config->hca_attr.parse_graph_flex_node) { + DR_LOG(ERR, "Dynamic flex parser is not supported"); + return -ENOTSUP; + } + if (__atomic_add_fetch(&dr_ctx->srh_flex_parser->refcnt, 1, __ATOMIC_RELAXED) > 1) + return 0; + + node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIELD; + /* Srv6 first two DW are not counted in. */ + node.header_length_base_value = 0x8; + /* The unit is uint64_t. */ + node.header_length_field_shift = 0x3; + /* Header length is the 2nd byte. */ + node.header_length_field_offset = 0x8; + node.header_length_field_mask = 0xF; + /* One byte next header protocol. */ + node.next_header_field_size = 0x8; + node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IP; + node.in[0].compare_condition_value = IPPROTO_ROUTING; + node.sample[0].flow_match_sample_en = 1; + /* First come first serve not matter inner or outer. */ + node.sample[0].flow_match_sample_tunnel_mode = MLX5_GRAPH_SAMPLE_TUNNEL_FIRST; + node.out[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_TCP; + node.out[0].compare_condition_value = IPPROTO_TCP; + node.out[1].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_UDP; + node.out[1].compare_condition_value = IPPROTO_UDP; + node.out[2].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IPV6; + node.out[2].compare_condition_value = IPPROTO_IPV6; + + dr_ctx->srh_flex_parser->fp = mlx5_devx_cmd_create_flex_parser(ctx, &node); + if (!dr_ctx->srh_flex_parser->fp) { + DR_LOG(ERR, "Failed to create flex parser node object."); + return (rte_errno == 0) ? -ENODEV : -rte_errno; + } + dr_ctx->srh_flex_parser->num = 1; + ret = mlx5_devx_cmd_query_parse_samples(dr_ctx->srh_flex_parser->fp, ids, + dr_ctx->srh_flex_parser->num, + &dr_ctx->srh_flex_parser->anchor_id); + if (ret) { + DR_LOG(ERR, "Failed to query sample IDs."); + return (rte_errno == 0) ? -ENODEV : -rte_errno; + } + dr_ctx->srh_flex_parser->offset[0] = 0x0; + dr_ctx->srh_flex_parser->ids[0].id = ids[0].id; + return 0; +} + +int mlx5dr_free_srh_flex_parser(struct mlx5dr_context *dr_ctx) +{ + struct mlx5_internal_flex_parser_profile *fp = dr_ctx->srh_flex_parser; + + if (__atomic_sub_fetch(&fp->refcnt, 1, __ATOMIC_RELAXED)) + return 0; + if (fp->fp) + mlx5_devx_cmd_destroy(fp->fp); + fp->fp = NULL; + return 0; +} + struct mlx5dr_context *mlx5dr_context_open(struct ibv_context *ibv_ctx, struct mlx5dr_context_attr *attr) { @@ -197,16 +267,22 @@ struct mlx5dr_context *mlx5dr_context_open(struct ibv_context *ibv_ctx, if (!ctx->caps) goto free_ctx; + ctx->srh_flex_parser = simple_calloc(1, sizeof(*ctx->srh_flex_parser)); + if (!ctx->srh_flex_parser) + goto free_caps; + ret = mlx5dr_cmd_query_caps(ibv_ctx, ctx->caps); if (ret) - goto free_caps; + goto free_flex; ret = mlx5dr_context_init_hws(ctx, attr); if (ret) - goto free_caps; + goto free_flex; return ctx; +free_flex: + simple_free(ctx->srh_flex_parser); free_caps: simple_free(ctx->caps); free_ctx: @@ -217,6 +293,7 @@ struct mlx5dr_context *mlx5dr_context_open(struct ibv_context *ibv_ctx, int mlx5dr_context_close(struct mlx5dr_context *ctx) { mlx5dr_context_uninit_hws(ctx); + simple_free(ctx->srh_flex_parser); simple_free(ctx->caps); pthread_spin_destroy(&ctx->ctrl_lock); simple_free(ctx); diff --git a/drivers/net/mlx5/hws/mlx5dr_context.h b/drivers/net/mlx5/hws/mlx5dr_context.h index b0c7802daf..c1c627aced 100644 --- a/drivers/net/mlx5/hws/mlx5dr_context.h +++ b/drivers/net/mlx5/hws/mlx5dr_context.h @@ -35,6 +35,7 @@ struct mlx5dr_context { struct mlx5dr_send_engine *send_queue; size_t queues; LIST_HEAD(table_head, mlx5dr_table) head; + struct mlx5_internal_flex_parser_profile *srh_flex_parser; }; #endif /* MLX5DR_CONTEXT_H_ */ diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 10b1e43d6e..09acd5d719 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -125,6 +125,7 @@ struct mlx5dr_definer_conv_data { X(SET_BE16, ipv4_frag, v->fragment_offset, rte_ipv4_hdr) \ X(SET_BE16, ipv6_payload_len, v->hdr.payload_len, rte_flow_item_ipv6) \ X(SET, ipv6_proto, v->hdr.proto, rte_flow_item_ipv6) \ + X(SET, ipv6_routing_hdr, IPPROTO_ROUTING, rte_flow_item_ipv6) \ X(SET, ipv6_hop_limits, v->hdr.hop_limits, rte_flow_item_ipv6) \ X(SET_BE32P, ipv6_src_addr_127_96, &v->hdr.src_addr[0], rte_flow_item_ipv6) \ X(SET_BE32P, ipv6_src_addr_95_64, &v->hdr.src_addr[4], rte_flow_item_ipv6) \ @@ -293,6 +294,18 @@ mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc, DR_SET(tag, ok1_bits, fc->byte_off, fc->bit_off, fc->bit_mask); } +static void +mlx5dr_definer_ipv6_routing_ext_set(struct mlx5dr_definer_fc *fc, + const void *item, + uint8_t *tag) +{ + const struct rte_flow_item_ipv6_routing_ext *v = item; + uint32_t val = 0; + + val = v->hdr.nexthdr << 24 | v->hdr.type << 8 | v->hdr.segments_left; + DR_SET_BE32(tag, RTE_BE32(val), fc->byte_off, 0, fc->bit_mask); +} + static void mlx5dr_definer_gre_key_set(struct mlx5dr_definer_fc *fc, const void *item_spec, @@ -1468,6 +1481,91 @@ mlx5dr_definer_conv_item_meter_color(struct mlx5dr_definer_conv_data *cd, return 0; } +static int +mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd, + struct rte_flow_item *item, + int item_idx) +{ + struct mlx5_internal_flex_parser_profile *fp = cd->ctx->srh_flex_parser; + enum mlx5dr_definer_fname i = MLX5DR_DEFINER_FNAME_FLEX_PARSER_0; + const struct rte_flow_item_ipv6_routing_ext *m = item->mask; + uint32_t byte_off = fp->ids[0].format_select_dw * 4; + struct mlx5dr_definer_fc *fc; + bool inner = cd->tunnel; + + if (!m) + return 0; + + if (!fp->num) + return -1; + + if (!cd->relaxed) { + fc = &cd->fc[DR_CALC_FNAME(IP_VERSION, inner)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ipv6_version_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l3_type, inner); + + /* Overwrite - Unset ethertype if present */ + memset(&cd->fc[DR_CALC_FNAME(ETH_TYPE, inner)], 0, sizeof(*fc)); + fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)]; + if (!fc->tag_set) { + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ipv6_routing_hdr_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l3, protocol_next_header, inner); + } + } + + if (m->hdr.nexthdr || m->hdr.type || m->hdr.segments_left) { + for (; i <= MLX5DR_DEFINER_FNAME_FLEX_PARSER_7; i++) { + switch (i) { + case MLX5DR_DEFINER_FNAME_FLEX_PARSER_0: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_FLEX_PARSER_0]; + DR_CALC_SET_HDR(fc, flex_parser, flex_parser_0); + break; + case MLX5DR_DEFINER_FNAME_FLEX_PARSER_1: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_FLEX_PARSER_1]; + DR_CALC_SET_HDR(fc, flex_parser, flex_parser_1); + break; + case MLX5DR_DEFINER_FNAME_FLEX_PARSER_2: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_FLEX_PARSER_2]; + DR_CALC_SET_HDR(fc, flex_parser, flex_parser_2); + break; + case MLX5DR_DEFINER_FNAME_FLEX_PARSER_3: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_FLEX_PARSER_3]; + DR_CALC_SET_HDR(fc, flex_parser, flex_parser_3); + break; + case MLX5DR_DEFINER_FNAME_FLEX_PARSER_4: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_FLEX_PARSER_4]; + DR_CALC_SET_HDR(fc, flex_parser, flex_parser_4); + break; + case MLX5DR_DEFINER_FNAME_FLEX_PARSER_5: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_FLEX_PARSER_5]; + DR_CALC_SET_HDR(fc, flex_parser, flex_parser_5); + break; + case MLX5DR_DEFINER_FNAME_FLEX_PARSER_6: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_FLEX_PARSER_6]; + DR_CALC_SET_HDR(fc, flex_parser, flex_parser_6); + break; + case MLX5DR_DEFINER_FNAME_FLEX_PARSER_7: + default: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_FLEX_PARSER_7]; + DR_CALC_SET_HDR(fc, flex_parser, flex_parser_7); + break; + } + if (fc->byte_off == byte_off) + break; + } + if (i > MLX5DR_DEFINER_FNAME_FLEX_PARSER_7) + return -ENOTSUP; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ipv6_routing_ext_set; + fc->fname = i; + } + return 0; +} + static int mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, struct mlx5dr_match_template *mt, @@ -1584,6 +1682,11 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, ret = mlx5dr_definer_conv_item_meter_color(&cd, items, i); item_flags |= MLX5_FLOW_ITEM_METER_COLOR; break; + case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT: + ret = mlx5dr_definer_conv_item_ipv6_routing_ext(&cd, items, i); + item_flags |= cd.tunnel ? MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT : + MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT; + break; default: DR_LOG(ERR, "Unsupported item type %d", items->type); rte_errno = ENOTSUP; diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 1c11b77ac3..6dbd5f9622 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -543,6 +543,16 @@ struct mlx5_counter_stats_raw { volatile struct flow_counter_stats *data; }; +/* Mlx5 internal flex parser profile structure. */ +struct mlx5_internal_flex_parser_profile { + uint32_t num;/* Actual number of samples. */ + struct mlx5_ext_sample_id ids[MLX5_FLEX_ITEM_MAPPING_NUM];/* Sample IDs for this profile. */ + uint32_t offset[MLX5_FLEX_ITEM_MAPPING_NUM];/* Each ID sample offset. */ + uint8_t anchor_id; + uint32_t refcnt; + void *fp; /* DevX flex parser object. */ +}; + TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); /* Counter global management structure. */ diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 1f57ecd6e1..81e2bc47a0 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -218,6 +218,9 @@ enum mlx5_feature_name { /* Meter color item */ #define MLX5_FLOW_ITEM_METER_COLOR (UINT64_C(1) << 44) +/* IPv6 routing extension item */ +#define MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT (UINT64_C(1) << 45) +#define MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT (UINT64_C(1) << 46) /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 20c71ff7f0..ff52eb28f0 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -213,23 +213,25 @@ flow_hw_hashfields_set(struct mlx5_flow_rss_desc *rss_desc, } /** - * Generate the pattern item flags. + * Generate the matching pattern item flags. * Will be used for shared RSS action. * * @param[in] items * Pointer to the list of items. + * @param[out] flags + * Flags superset including non-RSS items. * * @return - * Item flags. + * RSS Item flags. */ static uint64_t -flow_hw_rss_item_flags_get(const struct rte_flow_item items[]) +flow_hw_matching_item_flags_get(const struct rte_flow_item items[], uint64_t *flags) { - uint64_t item_flags = 0; uint64_t last_item = 0; + *flags = 0; for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { - int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); + int tunnel = !!(*flags & MLX5_FLOW_LAYER_TUNNEL); int item_type = items->type; switch (item_type) { @@ -249,6 +251,10 @@ flow_hw_rss_item_flags_get(const struct rte_flow_item items[]) last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP : MLX5_FLOW_LAYER_OUTER_L4_UDP; break; + case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT: + last_item = tunnel ? MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT : + MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT; + break; case RTE_FLOW_ITEM_TYPE_GRE: last_item = MLX5_FLOW_LAYER_GRE; break; @@ -273,9 +279,10 @@ flow_hw_rss_item_flags_get(const struct rte_flow_item items[]) default: break; } - item_flags |= last_item; + *flags |= last_item; } - return item_flags; + return *flags & ~(MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT | + MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT); } /** @@ -4732,6 +4739,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, case RTE_FLOW_ITEM_TYPE_ICMP: case RTE_FLOW_ITEM_TYPE_ICMP6: case RTE_FLOW_ITEM_TYPE_CONNTRACK: + case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT: break; case RTE_FLOW_ITEM_TYPE_INTEGRITY: /* @@ -4809,6 +4817,8 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev, .mask = &tag_m, .last = NULL }; + struct mlx5dr_context *dr_ctx = priv->dr_ctx; + uint64_t flags; if (flow_hw_pattern_validate(dev, attr, items, error)) return NULL; @@ -4860,7 +4870,7 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev, "cannot create match template"); return NULL; } - it->item_flags = flow_hw_rss_item_flags_get(tmpl_items); + it->item_flags = flow_hw_matching_item_flags_get(tmpl_items, &flags); if (copied_items) { if (attr->ingress) it->implicit_port = true; @@ -4868,6 +4878,15 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev, it->implicit_tag = true; mlx5_free(copied_items); } + if (flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT | + MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) { + if (mlx5dr_alloc_srh_flex_parser(dr_ctx, &priv->sh->cdev->config, + priv->sh->cdev->ctx)) { + claim_zero(mlx5dr_match_template_destroy(it->mt)); + mlx5_free(it); + return NULL; + } + } __atomic_fetch_add(&it->refcnt, 1, __ATOMIC_RELAXED); LIST_INSERT_HEAD(&priv->flow_hw_itt, it, next); return it; @@ -4891,6 +4910,9 @@ flow_hw_pattern_template_destroy(struct rte_eth_dev *dev __rte_unused, struct rte_flow_pattern_template *template, struct rte_flow_error *error __rte_unused) { + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5dr_context *dr_ctx = priv->dr_ctx; + if (__atomic_load_n(&template->refcnt, __ATOMIC_RELAXED) > 1) { DRV_LOG(WARNING, "Item template %p is still in use.", (void *)template); @@ -4899,6 +4921,7 @@ flow_hw_pattern_template_destroy(struct rte_eth_dev *dev __rte_unused, NULL, "item template in using"); } + mlx5dr_free_srh_flex_parser(dr_ctx); LIST_REMOVE(template, next); claim_zero(mlx5dr_match_template_destroy(template->mt)); mlx5_free(template); From patchwork Wed Dec 21 08:43:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: rongwei liu X-Patchwork-Id: 121187 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A031DA034C; Wed, 21 Dec 2022 09:44:09 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D1B0740A7F; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2022 08:43:45.6446 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83f2ea85-1751-480f-6c1a-08dae32f78eb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4993 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add IPv6 routing extension header support in raw_encap command. 1. No TLV support now. 2. Assume header length equals to the current segment_left. Signed-off-by: Rongwei Liu --- app/test-pmd/cmdline_flow.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c index 70685aafb1..24fdb260e9 100644 --- a/app/test-pmd/cmdline_flow.c +++ b/app/test-pmd/cmdline_flow.c @@ -10920,6 +10920,13 @@ flow_item_default_mask(const struct rte_flow_item *item) { const void *mask = NULL; static rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); + static struct rte_flow_item_ipv6_routing_ext ipv6_routing_ext_default_mask = { + .hdr = { + .nexthdr = 0xff, + .type = 0xff, + .segments_left = 0xff, + }, + }; switch (item->type) { case RTE_FLOW_ITEM_TYPE_ANY: @@ -11022,6 +11029,9 @@ flow_item_default_mask(const struct rte_flow_item *item) case RTE_FLOW_ITEM_TYPE_METER_COLOR: mask = &rte_flow_item_meter_color_mask; break; + case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT: + mask = &ipv6_routing_ext_default_mask; + break; default: break; } @@ -11176,6 +11186,7 @@ cmd_set_raw_parsed(const struct buffer *in) for (i = n - 1 ; i >= 0; --i) { const struct rte_flow_item_gtp *gtp; const struct rte_flow_item_geneve_opt *opt; + struct rte_flow_item_ipv6_routing_ext *ext; item = in->args.vc.pattern + i; if (item->spec == NULL) @@ -11196,6 +11207,12 @@ cmd_set_raw_parsed(const struct buffer *in) size = sizeof(struct rte_ipv6_hdr); proto = RTE_ETHER_TYPE_IPV6; break; + case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT: + ext = (struct rte_flow_item_ipv6_routing_ext *)(uintptr_t)item->spec; + size = sizeof(struct rte_ipv6_routing_ext) + (ext->hdr.segments_left << 4); + ext->hdr.hdrlen = ext->hdr.segments_left << 1; + proto = IPPROTO_ROUTING; + break; case RTE_FLOW_ITEM_TYPE_UDP: size = sizeof(struct rte_udp_hdr); proto = 0x11; From patchwork Wed Dec 21 08:43:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: rongwei liu X-Patchwork-Id: 121188 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F3A72A034C; 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Signed-off-by: Rongwei Liu Acked-by: Ori Kam --- lib/ethdev/rte_flow.h | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h index f8f1d6f9dd..b1240b0cb0 100644 --- a/lib/ethdev/rte_flow.h +++ b/lib/ethdev/rte_flow.h @@ -3567,6 +3567,7 @@ enum rte_flow_field_id { RTE_FLOW_FIELD_IPV6_ECN, /**< IPv6 ECN. */ RTE_FLOW_FIELD_GTP_PSC_QFI, /**< GTP QFI. */ RTE_FLOW_FIELD_METER_COLOR, /**< Meter color marker. */ + RTE_FLOW_FIELD_IPV6_PROTO, /**< IPv6 next header. */ }; /** From patchwork Wed Dec 21 08:43:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: rongwei liu X-Patchwork-Id: 121189 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D9AB4A034C; Wed, 21 Dec 2022 09:44:21 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7CB7C40698; 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Signed-off-by: Rongwei Liu --- app/test-pmd/cmdline_flow.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c index 24fdb260e9..374c89d434 100644 --- a/app/test-pmd/cmdline_flow.c +++ b/app/test-pmd/cmdline_flow.c @@ -811,7 +811,8 @@ static const char *const modify_field_ids[] = { "udp_port_src", "udp_port_dst", "vxlan_vni", "geneve_vni", "gtp_teid", "tag", "mark", "meta", "pointer", "value", - "ipv4_ecn", "ipv6_ecn", "gtp_psc_qfi", "meter_color", NULL + "ipv4_ecn", "ipv6_ecn", "gtp_psc_qfi", "meter_color", + "ipv6_proto", NULL }; static const char *const meter_colors[] = { From patchwork Wed Dec 21 08:43:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: rongwei liu X-Patchwork-Id: 121190 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1C755A034C; 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Signed-off-by: Rongwei Liu --- drivers/common/mlx5/mlx5_prm.h | 1 + drivers/net/mlx5/mlx5_flow_dv.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 1545b929b6..c57d49e079 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -753,6 +753,7 @@ enum mlx5_modification_field { MLX5_MODI_OUT_IP_ECN = 0x73, MLX5_MODI_TUNNEL_HDR_DW_1 = 0x75, MLX5_MODI_GTPU_FIRST_EXT_DW_0 = 0x76, + MLX5_MODI_OUT_IPV6_NEXT_HDR = 0x82, }; /* Total number of metadata reg_c's. */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 7ca909999b..e972a2dc5a 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1357,6 +1357,7 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev, case RTE_FLOW_FIELD_IPV6_DSCP: return 6; case RTE_FLOW_FIELD_IPV6_HOPLIMIT: + case RTE_FLOW_FIELD_IPV6_PROTO: return 8; case RTE_FLOW_FIELD_IPV6_SRC: case RTE_FLOW_FIELD_IPV6_DST: @@ -1883,6 +1884,15 @@ mlx5_flow_field_id_to_modify_info info[idx].offset = data->offset; } break; + case RTE_FLOW_FIELD_IPV6_PROTO: + MLX5_ASSERT(data->offset + width <= 8); + off_be = 8 - (data->offset + width); + info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_IPV6_NEXT_HDR}; + if (mask) + mask[idx] = flow_modify_info_mask_8(width, off_be); + else + info[idx].offset = off_be; + break; case RTE_FLOW_FIELD_POINTER: case RTE_FLOW_FIELD_VALUE: default: