From patchwork Fri Feb 24 09:40:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 124507 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7FCD141D5F; Fri, 24 Feb 2023 10:40:27 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8769740EF0; Fri, 24 Feb 2023 10:40:25 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7C30B40DF6 for ; Fri, 24 Feb 2023 10:40:23 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 31O71rQB026911 for ; Fri, 24 Feb 2023 01:40:22 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=qPtgSi0zckcTvjqkVSrFdpltpqTLk+FdMFkDSJMg/AE=; b=AYLhFZExaHP9TkUBuIXm2TTpU2ZJkCIYgLyou90r/+sV0xn0DL6xUoMfy1m6Dwu0GqUr VZ8BcBDfLkcyz0zIpc5+yWKMvR+CWBux629ogG1PECA6fNb3vRuJrdfl6Y3o2DvwsGWY RnkUnN6Fe6swaGuDu/OYQheWYyzM5hDaNPwygcscMYm+wZeQaKx142QsY4I6+GtyH9fo BpJdmdEHU3Al0XPFnCnn3s1SI1H1LTNryWA42ZojD8N7SNyP5P8haFdpENqSiB2Of48i rV96F6geiec/VLVA88bHs+KMRPkTIzS0+mdk4X0adhAJSb6NdcipaBSns9nUztqDu/XJ Hg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nxfkwb2g7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 24 Feb 2023 01:40:22 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Feb 2023 01:40:20 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 24 Feb 2023 01:40:20 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 41A203F709A; Fri, 24 Feb 2023 01:40:17 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Gowrishankar Muthukrishnan , Anoob Joseph , Subject: [PATCH v2 01/11] common/cnxk: fix incorrect auth key length Date: Fri, 24 Feb 2023 15:10:04 +0530 Message-ID: <20230224094014.3246764-2-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: J3JEiiMi3kArJsOb4Jp9l7O6aaQzZdHB X-Proofpoint-ORIG-GUID: J3JEiiMi3kArJsOb4Jp9l7O6aaQzZdHB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-24_05,2023-02-23_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Gowrishankar Muthukrishnan Auth key length is stored as 8 bit value in SE context. It should be larger enough to accommodate supported auth key length of 1024 bytes maximum, as in HMAC. Fixes: a45859312ff ("common/cnxk: add SE definitions for symmetric crypto") Signed-off-by: Gowrishankar Muthukrishnan --- drivers/common/cnxk/roc_se.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h index 6758142214..a0c97b26c5 100644 --- a/drivers/common/cnxk/roc_se.h +++ b/drivers/common/cnxk/roc_se.h @@ -288,16 +288,15 @@ struct roc_se_ctx { uint64_t enc_cipher : 8; uint64_t hash_type : 8; uint64_t mac_len : 8; - uint64_t auth_key_len : 8; + uint64_t auth_key_len : 16; uint64_t fc_type : 4; uint64_t hmac : 1; uint64_t zsk_flags : 3; uint64_t k_ecb : 1; uint64_t pdcp_ci_alg : 2; uint64_t pdcp_auth_alg : 2; - uint16_t ciph_then_auth : 1; - uint16_t auth_then_ciph : 1; - uint64_t rsvd : 17; + uint64_t ciph_then_auth : 1; + uint64_t auth_then_ciph : 1; union cpt_inst_w4 template_w4; /* Below fields are accessed by hardware */ struct se_ctx_s { From patchwork Fri Feb 24 09:40:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 124508 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E2DB341D5F; Fri, 24 Feb 2023 10:40:35 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 05451410EA; Fri, 24 Feb 2023 10:40:28 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4DD4F40DF6 for ; Fri, 24 Feb 2023 10:40:24 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 31O71t03027270 for ; Fri, 24 Feb 2023 01:40:23 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=UwoXYDdfJ8qUyb0D7a/jgCmfcaTfQRnuDwANueriP1M=; b=B396B8zj95ApDTmNFUaAFkMW9qyvQ5ZwrHZy7aru7hs+PesYAB7Igpo+SWQVOpyTg1DW NuX+lKts7N358uPJx9+FDntqwTqoGtAa1o/RWckFO6PMONyPTiMXoDTslZklC+yjHDcE JH8A6NAJcVZUeLffsp4TF2yfOHJ5+ZasL9pZm3GxXeSVCPzRA9mHNp5uuqZSAwXBQvi9 NIXWn2QnD6SDflPBrVeOBD72IfdWKf4AfATCwW1n9BGp6lhsU5V8+C/eNrpX9HQTnPl1 rwHFAfuIoAfXeViLVlOLvSZ4rMn/QwFnlwQEDgSmgHcMmT04HdXuOTohKgGfxeyyyhzd tQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nxfkwb2ga-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 24 Feb 2023 01:40:23 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Feb 2023 01:40:21 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 24 Feb 2023 01:40:21 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 4B25D3F7048; Fri, 24 Feb 2023 01:40:19 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Gowrishankar Muthukrishnan , Subject: [PATCH v2 02/11] crypto/cnxk: make sg version check const Date: Fri, 24 Feb 2023 15:10:05 +0530 Message-ID: <20230224094014.3246764-3-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: GmNfIzKN70rXH3eSOEeouiGZKPbixSwu X-Proofpoint-ORIG-GUID: GmNfIzKN70rXH3eSOEeouiGZKPbixSwu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-24_05,2023-02-23_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove sg_ver2 from burst structure and make it as const argument for compiler optimized code. Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 26 +++++++++++------------ 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index 4ee6b944c4..92f7002db9 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -38,7 +38,6 @@ struct ops_burst { struct cn10k_sso_hws *ws; struct cnxk_cpt_qp *qp; uint16_t nb_ops; - bool is_sg_ver2; }; /* Holds information required to send vector of operations */ @@ -489,7 +488,8 @@ cn10k_cpt_vec_submit(struct vec_request vec_tbl[], uint16_t vec_tbl_len, struct } static inline int -ca_lmtst_vec_submit(struct ops_burst *burst, struct vec_request vec_tbl[], uint16_t *vec_tbl_len) +ca_lmtst_vec_submit(struct ops_burst *burst, struct vec_request vec_tbl[], uint16_t *vec_tbl_len, + const bool is_sg_ver2) { struct cpt_inflight_req *infl_reqs[PKTS_PER_LOOP]; uint64_t lmt_base, lmt_arg, io_addr; @@ -537,7 +537,7 @@ ca_lmtst_vec_submit(struct ops_burst *burst, struct vec_request vec_tbl[], uint1 infl_req = infl_reqs[i]; infl_req->op_flags = 0; - ret = cn10k_cpt_fill_inst(qp, &burst->op[i], inst, infl_req, burst->is_sg_ver2); + ret = cn10k_cpt_fill_inst(qp, &burst->op[i], inst, infl_req, is_sg_ver2); if (unlikely(ret != 1)) { plt_cpt_dbg("Could not process op: %p", burst->op[i]); if (i != 0) @@ -620,7 +620,7 @@ next_op:; } static inline uint16_t -ca_lmtst_burst_submit(struct ops_burst *burst) +ca_lmtst_burst_submit(struct ops_burst *burst, const bool is_sg_ver2) { struct cpt_inflight_req *infl_reqs[PKTS_PER_LOOP]; uint64_t lmt_base, lmt_arg, io_addr; @@ -660,7 +660,7 @@ ca_lmtst_burst_submit(struct ops_burst *burst) infl_req = infl_reqs[i]; infl_req->op_flags = 0; - ret = cn10k_cpt_fill_inst(qp, &burst->op[i], inst, infl_req, burst->is_sg_ver2); + ret = cn10k_cpt_fill_inst(qp, &burst->op[i], inst, infl_req, is_sg_ver2); if (unlikely(ret != 1)) { plt_dp_dbg("Could not process op: %p", burst->op[i]); if (i != 0) @@ -729,7 +729,6 @@ cn10k_cpt_crypto_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_ev burst.ws = ws; burst.qp = NULL; burst.nb_ops = 0; - burst.is_sg_ver2 = is_sg_ver2; for (i = 0; i < nb_events; i++) { op = ev[i].event_ptr; @@ -743,8 +742,8 @@ cn10k_cpt_crypto_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_ev if (qp != burst.qp) { if (burst.nb_ops) { if (is_vector) { - submitted = - ca_lmtst_vec_submit(&burst, vec_tbl, &vec_tbl_len); + submitted = ca_lmtst_vec_submit(&burst, vec_tbl, + &vec_tbl_len, is_sg_ver2); /* * Vector submission is required on qp change, but not in * other cases, since we could send several vectors per @@ -753,7 +752,7 @@ cn10k_cpt_crypto_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_ev cn10k_cpt_vec_submit(vec_tbl, vec_tbl_len, burst.qp); vec_tbl_len = 0; } else { - submitted = ca_lmtst_burst_submit(&burst); + submitted = ca_lmtst_burst_submit(&burst, is_sg_ver2); } count += submitted; if (unlikely(submitted != burst.nb_ops)) @@ -769,9 +768,10 @@ cn10k_cpt_crypto_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_ev /* Max nb_ops per burst check */ if (++burst.nb_ops == PKTS_PER_LOOP) { if (is_vector) - submitted = ca_lmtst_vec_submit(&burst, vec_tbl, &vec_tbl_len); + submitted = ca_lmtst_vec_submit(&burst, vec_tbl, &vec_tbl_len, + is_sg_ver2); else - submitted = ca_lmtst_burst_submit(&burst); + submitted = ca_lmtst_burst_submit(&burst, is_sg_ver2); count += submitted; if (unlikely(submitted != burst.nb_ops)) goto vec_submit; @@ -781,9 +781,9 @@ cn10k_cpt_crypto_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_ev /* Submit the rest of crypto operations */ if (burst.nb_ops) { if (is_vector) - count += ca_lmtst_vec_submit(&burst, vec_tbl, &vec_tbl_len); + count += ca_lmtst_vec_submit(&burst, vec_tbl, &vec_tbl_len, is_sg_ver2); else - count += ca_lmtst_burst_submit(&burst); + count += ca_lmtst_burst_submit(&burst, is_sg_ver2); } vec_submit: From patchwork Fri Feb 24 09:40:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 124509 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B8D8741D5F; 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Fri, 24 Feb 2023 01:40:24 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Feb 2023 01:40:22 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 24 Feb 2023 01:40:22 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 48AE65B6936; Fri, 24 Feb 2023 01:40:21 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Gowrishankar Muthukrishnan , Subject: [PATCH v2 03/11] crypto/cnxk: use version field directly Date: Fri, 24 Feb 2023 15:10:06 +0530 Message-ID: <20230224094014.3246764-4-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: dWxmM2HJsivoPJvoP_UuUkq8JB176LaD X-Proofpoint-ORIG-GUID: dWxmM2HJsivoPJvoP_UuUkq8JB176LaD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-24_05,2023-02-23_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph As version field is available in rte_ip_hdr, use it directly instead of masking version_ihl. Signed-off-by: Anoob Joseph --- drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 4 ++-- drivers/crypto/cnxk/cn9k_ipsec_la_ops.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c index 3a07842e4b..11541b6ab9 100644 --- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c @@ -546,10 +546,10 @@ cn9k_cpt_sec_post_process(struct rte_crypto_op *cop, } } - if (((ip->version_ihl & 0xf0) >> RTE_IPV4_IHL_MULTIPLIER) == IPVERSION) { + if (ip->version == IPVERSION) { m_len = rte_be_to_cpu_16(ip->total_length); } else { - PLT_ASSERT(((ip->version_ihl & 0xf0) >> RTE_IPV4_IHL_MULTIPLIER) == 6); + PLT_ASSERT((ip->version == 6)); ip6 = (struct rte_ipv6_hdr *)ip; m_len = rte_be_to_cpu_16(ip6->payload_len) + sizeof(struct rte_ipv6_hdr); } diff --git a/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h b/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h index 9df41bf65d..85aacb803f 100644 --- a/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h +++ b/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h @@ -28,13 +28,13 @@ ipsec_po_out_rlen_get(struct cn9k_sec_session *sess, uint32_t plen, struct rte_m uintptr_t data = (uintptr_t)m_src->buf_addr + m_src->data_off; struct rte_ipv4_hdr *ip = (struct rte_ipv4_hdr *)data; - if (unlikely(((ip->version_ihl & 0xf0) >> RTE_IPV4_IHL_MULTIPLIER) != IPVERSION)) { + if (unlikely(ip->version != IPVERSION)) { struct rte_ipv6_hdr *ip6 = (struct rte_ipv6_hdr *)ip; uint8_t *nxt_hdr = (uint8_t *)ip6; uint8_t dest_op_cnt = 0; int nh = ip6->proto; - PLT_ASSERT(((ip->version_ihl & 0xf0) >> RTE_IPV4_IHL_MULTIPLIER) == 6); + PLT_ASSERT(ip->version == 6); adj_len = ROC_CPT_TUNNEL_IPV6_HDR_LEN; nxt_hdr += ROC_CPT_TUNNEL_IPV6_HDR_LEN; From patchwork Fri Feb 24 09:40:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 124510 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1A11541D5F; Fri, 24 Feb 2023 10:40:48 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3C75941153; 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Fri, 24 Feb 2023 01:40:27 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Feb 2023 01:40:24 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 24 Feb 2023 01:40:24 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 4E2FF5B6929; Fri, 24 Feb 2023 01:40:23 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Gowrishankar Muthukrishnan , Subject: [PATCH v2 04/11] crypto/cnxk: use direct mode for zero aad length Date: Fri, 24 Feb 2023 15:10:07 +0530 Message-ID: <20230224094014.3246764-5-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: DxFmmJr_vcmeFMFNM862IoRLfrx1T6Ix X-Proofpoint-ORIG-GUID: DxFmmJr_vcmeFMFNM862IoRLfrx1T6Ix X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-24_05,2023-02-23_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Using direct mode if aad length is zero. Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cnxk_se.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index c16027ec75..69cd343eea 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -2258,9 +2258,9 @@ fill_fc_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess, aad_data = sym_op->aead.aad.data; aad_len = sess->aad_length; - if (likely((aad_data + aad_len) == - rte_pktmbuf_mtod_offset(m_src, uint8_t *, - sym_op->aead.data.offset))) { + if (likely((aad_len == 0) || + ((aad_data + aad_len) == + rte_pktmbuf_mtod_offset(m_src, uint8_t *, sym_op->aead.data.offset)))) { d_offs = (d_offs - aad_len) | (d_offs << 16); d_lens = (d_lens + aad_len) | (d_lens << 32); } else { From patchwork Fri Feb 24 09:40:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 124511 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3BE9E41D5F; Fri, 24 Feb 2023 10:40:55 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 43168427F5; Fri, 24 Feb 2023 10:40:32 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A8A0E41151 for ; Fri, 24 Feb 2023 10:40:29 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 31O6o4W9001318 for ; Fri, 24 Feb 2023 01:40:29 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=UsHqTZtUJCX7pJCUY0s6C1wnWwMa9qOc670Ut8TWQD8=; b=VDNCGluebZzOe3NA3M9b2LYXrELMcXtWqz9HERsVCpZrVb3ag2duf7MHSJoTcd9HrFJf FTo8rmMI1yKZrvzfBv7idhBlYGsly49mTfmkWX/y1JgVQmGqgqzoLRKQKnBY5HLuepDp EfevozlTubmBBp034625nfXwNBEc69+WX5GN1xRDuIXZ2FEsV7uoOr3eeXI0mzWR3t8q tJtjIIkxQaudhVQ8SuEjXlrTOAVqfdaumGs2hECtHd85XYBJqtQQCLQJmgkUdqa3vJp0 ExHJC9jcJ9XJesg9k/bnLC58zzCHZPgUPx960uIhnBA+ZJ3qzJuHB1iVdv5kCzuurXdC dw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nxfkwb2gx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 24 Feb 2023 01:40:28 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Feb 2023 01:40:26 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 24 Feb 2023 01:40:26 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 577B35B692C; Fri, 24 Feb 2023 01:40:25 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Gowrishankar Muthukrishnan , Subject: [PATCH v2 05/11] crypto/cnxk: set ctx for AE Date: Fri, 24 Feb 2023 15:10:08 +0530 Message-ID: <20230224094014.3246764-6-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Gf-hIGAgUY3RUCC_4fEXah9gIMe62e04 X-Proofpoint-ORIG-GUID: Gf-hIGAgUY3RUCC_4fEXah9gIMe62e04 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-24_05,2023-02-23_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Set ctx_val to 1 for asymmetric ops. Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 18 ++++--------- drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 16 +++-------- drivers/crypto/cnxk/cnxk_ae.h | 21 +++++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 33 ++++++++++++++++------- 4 files changed, 53 insertions(+), 35 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index 92f7002db9..d1a43eaf13 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -158,10 +158,8 @@ cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[], struct if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) { asym_op = op->asym; - ae_sess = (struct cnxk_ae_sess *) - asym_op->session->sess_private_data; - ret = cnxk_ae_enqueue(qp, op, infl_req, &inst[0], - ae_sess); + ae_sess = (struct cnxk_ae_sess *)asym_op->session; + ret = cnxk_ae_enqueue(qp, op, infl_req, &inst[0], ae_sess); if (unlikely(ret)) return 0; w7 = ae_sess->cpt_inst_w7; @@ -330,10 +328,9 @@ cn10k_cpt_crypto_adapter_ev_mdata_set(struct rte_cryptodev *dev __rte_unused, vo return -EINVAL; } else if (op_type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { if (sess_type == RTE_CRYPTO_OP_WITH_SESSION) { - struct rte_cryptodev_asym_session *asym_sess = sess; struct cnxk_ae_sess *priv; - priv = (struct cnxk_ae_sess *)asym_sess->sess_private_data; + priv = (struct cnxk_ae_sess *)sess; priv->qp = qp; priv->cpt_inst_w2 = w2; } else @@ -381,11 +378,9 @@ cn10k_ca_meta_info_extract(struct rte_crypto_op *op, struct cnxk_cpt_qp **qp, ui } } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) { - struct rte_cryptodev_asym_session *asym_sess; struct cnxk_ae_sess *priv; - asym_sess = op->asym->session; - priv = (struct cnxk_ae_sess *)asym_sess->sess_private_data; + priv = (struct cnxk_ae_sess *)op->asym->session; *qp = priv->qp; *w2 = priv->cpt_inst_w2; } else @@ -890,10 +885,7 @@ cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp, } else if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { struct rte_crypto_asym_op *op = cop->asym; uintptr_t *mdata = infl_req->mdata; - struct cnxk_ae_sess *sess; - - sess = (struct cnxk_ae_sess *) - op->session->sess_private_data; + struct cnxk_ae_sess *sess = (struct cnxk_ae_sess *)op->session; cnxk_ae_post_process(cop, sess, (uint8_t *)mdata[0]); } diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c index 11541b6ab9..34d40b07d4 100644 --- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c @@ -105,13 +105,10 @@ cn9k_cpt_inst_prep(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, inst->w7.u64 = sess->cpt_inst_w7; } } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { - struct rte_crypto_asym_op *asym_op; struct cnxk_ae_sess *sess; if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) { - asym_op = op->asym; - sess = (struct cnxk_ae_sess *) - asym_op->session->sess_private_data; + sess = (struct cnxk_ae_sess *)op->asym->session; ret = cnxk_ae_enqueue(qp, op, infl_req, inst, sess); inst->w7.u64 = sess->cpt_inst_w7; } else { @@ -345,7 +342,7 @@ cn9k_cpt_crypto_adapter_ev_mdata_set(struct rte_cryptodev *dev __rte_unused, struct rte_cryptodev_asym_session *asym_sess = sess; struct cnxk_ae_sess *priv; - priv = (struct cnxk_ae_sess *)asym_sess->sess_private_data; + priv = (struct cnxk_ae_sess *)asym_sess; priv->qp = qp; priv->cpt_inst_w2 = w2; } else @@ -393,11 +390,9 @@ cn9k_ca_meta_info_extract(struct rte_crypto_op *op, } } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) { - struct rte_cryptodev_asym_session *asym_sess; struct cnxk_ae_sess *priv; - asym_sess = op->asym->session; - priv = (struct cnxk_ae_sess *)asym_sess->sess_private_data; + priv = (struct cnxk_ae_sess *)op->asym->session; *qp = priv->qp; inst->w2.u64 = priv->cpt_inst_w2; } else @@ -609,10 +604,7 @@ cn9k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp, struct rte_crypto_op *cop, } else if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { struct rte_crypto_asym_op *op = cop->asym; uintptr_t *mdata = infl_req->mdata; - struct cnxk_ae_sess *sess; - - sess = (struct cnxk_ae_sess *) - op->session->sess_private_data; + struct cnxk_ae_sess *sess = (struct cnxk_ae_sess *)op->session; cnxk_ae_post_process(cop, sess, (uint8_t *)mdata[0]); } diff --git a/drivers/crypto/cnxk/cnxk_ae.h b/drivers/crypto/cnxk/cnxk_ae.h index 698c10129e..b7c13a9e01 100644 --- a/drivers/crypto/cnxk/cnxk_ae.h +++ b/drivers/crypto/cnxk/cnxk_ae.h @@ -13,7 +13,10 @@ #include "cnxk_cryptodev_ops.h" +#define ASYM_SESS_SIZE sizeof(struct rte_cryptodev_asym_session) + struct cnxk_ae_sess { + uint8_t rte_sess[ASYM_SESS_SIZE]; enum rte_crypto_asym_xform_type xfrm_type; union { struct rte_crypto_rsa_xform rsa_ctx; @@ -25,6 +28,24 @@ struct cnxk_ae_sess { uint64_t cpt_inst_w7; uint64_t cpt_inst_w2; struct cnxk_cpt_qp *qp; + struct roc_cpt_lf *lf; + struct hw_ctx_s { + union { + struct { + uint64_t rsvd : 48; + + uint64_t ctx_push_size : 7; + uint64_t rsvd1 : 1; + + uint64_t ctx_hdr_size : 2; + uint64_t aop_valid : 1; + uint64_t rsvd2 : 1; + uint64_t ctx_size : 4; + } s; + uint64_t u64; + } w0; + uint8_t rsvd[256]; + } hw_ctx __plt_aligned(ROC_ALIGN); }; static __rte_always_inline void diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 27f2846f74..f03646fe1a 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -760,14 +760,14 @@ cnxk_ae_session_size_get(struct rte_cryptodev *dev __rte_unused) } void -cnxk_ae_session_clear(struct rte_cryptodev *dev, - struct rte_cryptodev_asym_session *sess) +cnxk_ae_session_clear(struct rte_cryptodev *dev, struct rte_cryptodev_asym_session *sess) { - struct cnxk_ae_sess *priv; + struct cnxk_ae_sess *priv = (struct cnxk_ae_sess *)sess; - priv = (struct cnxk_ae_sess *) sess->sess_private_data; - if (priv == NULL) - return; + /* Trigger CTX flush + invalidate to remove from CTX_CACHE */ + roc_cpt_lf_ctx_flush(priv->lf, &priv->hw_ctx, true); + + plt_delay_ms(1); /* Free resources allocated in session_cfg */ cnxk_ae_free_session_parameters(priv); @@ -777,23 +777,36 @@ cnxk_ae_session_clear(struct rte_cryptodev *dev, } int -cnxk_ae_session_cfg(struct rte_cryptodev *dev, - struct rte_crypto_asym_xform *xform, +cnxk_ae_session_cfg(struct rte_cryptodev *dev, struct rte_crypto_asym_xform *xform, struct rte_cryptodev_asym_session *sess) { - struct cnxk_ae_sess *priv = - (struct cnxk_ae_sess *) sess->sess_private_data; + struct cnxk_ae_sess *priv = (struct cnxk_ae_sess *)sess; struct cnxk_cpt_vf *vf = dev->data->dev_private; struct roc_cpt *roc_cpt = &vf->cpt; union cpt_inst_w7 w7; + struct hw_ctx_s *hwc; int ret; ret = cnxk_ae_fill_session_parameters(priv, xform); if (ret) return ret; + priv->lf = roc_cpt->lf[0]; + w7.u64 = 0; w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_AE]; + + if (vf->cpt.cpt_revision == ROC_CPT_REVISION_ID_106XX) { + hwc = &priv->hw_ctx; + hwc->w0.s.aop_valid = 1; + hwc->w0.s.ctx_hdr_size = 0; + hwc->w0.s.ctx_size = 1; + hwc->w0.s.ctx_push_size = 1; + + w7.s.cptr = (uint64_t)hwc; + w7.s.ctx_val = 1; + } + priv->cpt_inst_w7 = w7.u64; priv->cnxk_fpm_iova = vf->cnxk_fpm_iova; priv->ec_grp = vf->ec_grp; From patchwork Fri Feb 24 09:40:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 124512 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4784A41D5F; Fri, 24 Feb 2023 10:41:02 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6C19F42BB1; Fri, 24 Feb 2023 10:40:34 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D03254161A for ; Fri, 24 Feb 2023 10:40:31 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 31O6nQhq032724 for ; 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Fri, 24 Feb 2023 01:40:28 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 24 Feb 2023 01:40:28 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 5BF935B692A; Fri, 24 Feb 2023 01:40:27 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Gowrishankar Muthukrishnan , Subject: [PATCH v2 06/11] common/cnxk: ensure flush inval completion with CSR read Date: Fri, 24 Feb 2023 15:10:09 +0530 Message-ID: <20230224094014.3246764-7-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: IwydD0UOwxrT287cIr1DpP9fTlwxyRIj X-Proofpoint-ORIG-GUID: IwydD0UOwxrT287cIr1DpP9fTlwxyRIj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-24_05,2023-02-23_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph If a CSR read is issued after a write, the read would block till the write operation is complete. This would help in determining when the FLUSH+INVALIDATE operation is complete. Signed-off-by: Anoob Joseph --- drivers/common/cnxk/hw/cpt.h | 11 +++++++++++ drivers/common/cnxk/roc_cpt.c | 16 ++++++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 4 ---- 3 files changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h index d378a4eadd..44ff8b08b2 100644 --- a/drivers/common/cnxk/hw/cpt.h +++ b/drivers/common/cnxk/hw/cpt.h @@ -100,6 +100,17 @@ union cpt_lf_ctx_flush { } s; }; +union cpt_lf_ctx_err { + uint64_t u; + struct { + uint64_t flush_st_flt : 1; + uint64_t busy_flr : 1; + uint64_t busy_sw_flush : 1; + uint64_t reload_faulted : 1; + uint64_t reserved_4_63 : 1; + } s; +}; + union cpt_lf_ctx_reload { uint64_t u; struct { diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index cf514be69f..dff2fbf2a4 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -783,6 +783,7 @@ int roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr, bool inval) { union cpt_lf_ctx_flush reg; + union cpt_lf_ctx_err err; if (lf == NULL) { plt_err("Could not trigger CTX flush"); @@ -795,6 +796,21 @@ roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr, bool inval) plt_write64(reg.u, lf->rbase + CPT_LF_CTX_FLUSH); + plt_atomic_thread_fence(__ATOMIC_ACQ_REL); + + /* Read a CSR to ensure that the FLUSH operation is complete */ + err.u = plt_read64(lf->rbase + CPT_LF_CTX_ERR); + + if (err.s.busy_sw_flush && inval) { + plt_err("CTX entry could not be invalidated due to active usage."); + return -EAGAIN; + } + + if (err.s.flush_st_flt) { + plt_err("CTX flush could not complete due to store fault"); + abort(); + } + return 0; } diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index f03646fe1a..67bd7e3243 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -737,8 +737,6 @@ sym_session_clear(struct rte_cryptodev_sym_session *sess, bool is_session_less) /* Trigger CTX flush + invalidate to remove from CTX_CACHE */ roc_cpt_lf_ctx_flush(sess_priv->lf, &sess_priv->roc_se_ctx.se_ctx, true); - plt_delay_ms(1); - if (sess_priv->roc_se_ctx.auth_key != NULL) plt_free(sess_priv->roc_se_ctx.auth_key); @@ -767,8 +765,6 @@ cnxk_ae_session_clear(struct rte_cryptodev *dev, struct rte_cryptodev_asym_sessi /* Trigger CTX flush + invalidate to remove from CTX_CACHE */ roc_cpt_lf_ctx_flush(priv->lf, &priv->hw_ctx, true); - plt_delay_ms(1); - /* Free resources allocated in session_cfg */ cnxk_ae_free_session_parameters(priv); From patchwork Fri Feb 24 09:40:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 124513 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C355241D5F; Fri, 24 Feb 2023 10:41:12 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E869A42D0C; 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Fri, 24 Feb 2023 01:40:32 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Feb 2023 01:40:30 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 24 Feb 2023 01:40:30 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 5E8983F706B; Fri, 24 Feb 2023 01:40:29 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Gowrishankar Muthukrishnan , Subject: [PATCH v2 07/11] common/cnxk: add errata function for CPT set ctx Date: Fri, 24 Feb 2023 15:10:10 +0530 Message-ID: <20230224094014.3246764-8-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: wTo08LqyO1CgTByqCpWH6MXkCCNqs_Ke X-Proofpoint-ORIG-GUID: wTo08LqyO1CgTByqCpWH6MXkCCNqs_Ke X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-24_05,2023-02-23_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding function in errata header file for CPT ctx_val and replace CPT revision_id checks with function call. Signed-off-by: Tejasree Kondoj --- drivers/common/cnxk/roc_errata.h | 9 +++++++++ drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 13 ++++++++----- 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h index 36e6db467a..9954b7da32 100644 --- a/drivers/common/cnxk/roc_errata.h +++ b/drivers/common/cnxk/roc_errata.h @@ -4,6 +4,8 @@ #ifndef _ROC_ERRATA_H_ #define _ROC_ERRATA_H_ +#include "roc_model.h" + /* Errata IPBUNIXRX-40129 */ static inline bool roc_errata_nix_has_no_drop_re(void) @@ -98,4 +100,11 @@ roc_errata_nix_sdp_send_has_mtu_size_16k(void) roc_model_is_cn96_a0() || roc_model_is_cn96_b0()); } +/* Errata IPBUCPT-38753 */ +static inline bool +roc_errata_cpt_hang_on_mixed_ctx_val(void) +{ + return roc_model_is_cn10ka_a0() || roc_model_is_cn10ka_a1(); +} + #endif /* _ROC_ERRATA_H_ */ diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 67bd7e3243..adc1c7652b 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -8,6 +8,7 @@ #include "roc_ae_fpm_tables.h" #include "roc_cpt.h" +#include "roc_errata.h" #include "roc_ie_on.h" #include "cnxk_ae.h" @@ -636,7 +637,7 @@ cnxk_cpt_inst_w7_get(struct cnxk_se_sess *sess, struct roc_cpt *roc_cpt) inst_w7.s.cptr = (uint64_t)&sess->roc_se_ctx.se_ctx; - if (roc_cpt->cpt_revision == ROC_CPT_REVISION_ID_106XX) + if (roc_errata_cpt_hang_on_mixed_ctx_val()) inst_w7.s.ctx_val = 1; else inst_w7.s.cptr += 8; @@ -709,7 +710,7 @@ sym_session_configure(struct roc_cpt *roc_cpt, struct rte_crypto_sym_xform *xfor sess_priv->cpt_inst_w7 = cnxk_cpt_inst_w7_get(sess_priv, roc_cpt); - if (roc_cpt->cpt_revision == ROC_CPT_REVISION_ID_106XX) + if (roc_errata_cpt_hang_on_mixed_ctx_val()) roc_se_ctx_init(&sess_priv->roc_se_ctx); return 0; @@ -735,7 +736,8 @@ sym_session_clear(struct rte_cryptodev_sym_session *sess, bool is_session_less) struct cnxk_se_sess *sess_priv = (struct cnxk_se_sess *)sess; /* Trigger CTX flush + invalidate to remove from CTX_CACHE */ - roc_cpt_lf_ctx_flush(sess_priv->lf, &sess_priv->roc_se_ctx.se_ctx, true); + if (roc_errata_cpt_hang_on_mixed_ctx_val()) + roc_cpt_lf_ctx_flush(sess_priv->lf, &sess_priv->roc_se_ctx.se_ctx, true); if (sess_priv->roc_se_ctx.auth_key != NULL) plt_free(sess_priv->roc_se_ctx.auth_key); @@ -763,7 +765,8 @@ cnxk_ae_session_clear(struct rte_cryptodev *dev, struct rte_cryptodev_asym_sessi struct cnxk_ae_sess *priv = (struct cnxk_ae_sess *)sess; /* Trigger CTX flush + invalidate to remove from CTX_CACHE */ - roc_cpt_lf_ctx_flush(priv->lf, &priv->hw_ctx, true); + if (roc_errata_cpt_hang_on_mixed_ctx_val()) + roc_cpt_lf_ctx_flush(priv->lf, &priv->hw_ctx, true); /* Free resources allocated in session_cfg */ cnxk_ae_free_session_parameters(priv); @@ -792,7 +795,7 @@ cnxk_ae_session_cfg(struct rte_cryptodev *dev, struct rte_crypto_asym_xform *xfo w7.u64 = 0; w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_AE]; - if (vf->cpt.cpt_revision == ROC_CPT_REVISION_ID_106XX) { + if (roc_errata_cpt_hang_on_mixed_ctx_val()) { hwc = &priv->hw_ctx; hwc->w0.s.aop_valid = 1; hwc->w0.s.ctx_hdr_size = 0; From patchwork Fri Feb 24 09:40:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 124514 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B5DA041D5F; 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Fri, 24 Feb 2023 01:40:34 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Feb 2023 01:40:32 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 24 Feb 2023 01:40:32 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 6718F3F7068; Fri, 24 Feb 2023 01:40:31 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Gowrishankar Muthukrishnan , Subject: [PATCH v2 08/11] common/cnxk: replace CPT revision check with caps Date: Fri, 24 Feb 2023 15:10:11 +0530 Message-ID: <20230224094014.3246764-9-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: iznAIdEglYIMexyGzA6RVdDC73O_U8O8 X-Proofpoint-ORIG-GUID: iznAIdEglYIMexyGzA6RVdDC73O_U8O8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-24_05,2023-02-23_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Replace SG version revision check with capabilities populated from microcode. Signed-off-by: Tejasree Kondoj --- drivers/common/cnxk/hw/cpt.h | 3 ++- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 2 +- drivers/event/cnxk/cn10k_eventdev.c | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h index 44ff8b08b2..82ea076e4c 100644 --- a/drivers/common/cnxk/hw/cpt.h +++ b/drivers/common/cnxk/hw/cpt.h @@ -75,7 +75,8 @@ union cpt_eng_caps { uint64_t __io mmul : 1; uint64_t __io reserved_15_33 : 19; uint64_t __io pdcp_chain : 1; - uint64_t __io reserved_35_63 : 29; + uint64_t __io sg_ver2 : 1; + uint64_t __io reserved_36_63 : 28; }; }; diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index d1a43eaf13..9f6fd4e411 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -1045,7 +1045,7 @@ cn10k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) void cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev, struct cnxk_cpt_vf *vf) { - if (vf->cpt.cpt_revision > ROC_CPT_REVISION_ID_106XX) + if (vf->cpt.hw_caps[CPT_ENG_TYPE_SE].sg_ver2 && vf->cpt.hw_caps[CPT_ENG_TYPE_IE].sg_ver2) dev->enqueue_burst = cn10k_cpt_sg_ver2_enqueue_burst; else dev->enqueue_burst = cn10k_cpt_sg_ver1_enqueue_burst; diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 8e74edff55..ee0428adc8 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -602,7 +602,8 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev) } } - if ((cpt != NULL) && (cpt->cpt_revision > ROC_CPT_REVISION_ID_106XX)) + if ((cpt != NULL) && cpt->hw_caps[CPT_ENG_TYPE_SE].sg_ver2 && + cpt->hw_caps[CPT_ENG_TYPE_IE].sg_ver2) event_dev->ca_enqueue = cn10k_cpt_sg_ver2_crypto_adapter_enqueue; else event_dev->ca_enqueue = cn10k_cpt_sg_ver1_crypto_adapter_enqueue; From patchwork Fri Feb 24 09:40:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 124515 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7788E41D5F; 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Fri, 24 Feb 2023 01:40:37 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Feb 2023 01:40:34 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 24 Feb 2023 01:40:34 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 6AD6E5B6929; Fri, 24 Feb 2023 01:40:33 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Gowrishankar Muthukrishnan , Subject: [PATCH v2 09/11] crypto/cnxk: support cn10k IPsec SG mode Date: Fri, 24 Feb 2023 15:10:12 +0530 Message-ID: <20230224094014.3246764-10-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: O6b8BJ4pz5Ao2nx54tNGADsRnjtSHUb- X-Proofpoint-ORIG-GUID: O6b8BJ4pz5Ao2nx54tNGADsRnjtSHUb- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-24_05,2023-02-23_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding support for scatter-gather mode in 103XX and 106XX lookaside IPsec. Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 21 +- drivers/crypto/cnxk/cn10k_ipsec_la_ops.h | 222 ++++++++++++++++++++-- drivers/crypto/cnxk/cnxk_sg.h | 23 +++ 3 files changed, 239 insertions(+), 27 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index 9f6fd4e411..e405a2ad9f 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -77,8 +77,8 @@ cn10k_cpt_sym_temp_sess_create(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op) } static __rte_always_inline int __rte_hot -cpt_sec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, - struct cn10k_sec_session *sess, struct cpt_inst_s *inst) +cpt_sec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, struct cn10k_sec_session *sess, + struct cpt_inst_s *inst, struct cpt_inflight_req *infl_req, const bool is_sg_ver2) { struct rte_crypto_sym_op *sym_op = op->sym; int ret; @@ -88,15 +88,11 @@ cpt_sec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, return -ENOTSUP; } - if (unlikely(!rte_pktmbuf_is_contiguous(sym_op->m_src))) { - plt_dp_err("Scatter Gather mode is not supported"); - return -ENOTSUP; - } - if (sess->is_outbound) - ret = process_outb_sa(&qp->lf, op, sess, inst); + ret = process_outb_sa(&qp->lf, op, sess, &qp->meta_info, infl_req, inst, + is_sg_ver2); else - ret = process_inb_sa(op, sess, inst); + ret = process_inb_sa(op, sess, inst, &qp->meta_info, infl_req, is_sg_ver2); return ret; } @@ -129,7 +125,7 @@ cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[], struct if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) { if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) { sec_sess = (struct cn10k_sec_session *)sym_op->session; - ret = cpt_sec_inst_fill(qp, op, sec_sess, &inst[0]); + ret = cpt_sec_inst_fill(qp, op, sec_sess, &inst[0], infl_req, is_sg_ver2); if (unlikely(ret)) return 0; w7 = sec_sess->inst.w7; @@ -827,7 +823,10 @@ cn10k_cpt_sec_post_process(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *re cop->status = RTE_CRYPTO_OP_STATUS_ERROR; return; } - mbuf->data_len = m_len; + + if (mbuf->next == NULL) + mbuf->data_len = m_len; + mbuf->pkt_len = m_len; } diff --git a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h index f2761a55a5..8e208eb2ca 100644 --- a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h +++ b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h @@ -8,9 +8,13 @@ #include #include +#include "roc_ie.h" + #include "cn10k_cryptodev.h" #include "cn10k_ipsec.h" #include "cnxk_cryptodev.h" +#include "cnxk_cryptodev_ops.h" +#include "cnxk_sg.h" static inline void ipsec_po_sa_iv_set(struct cn10k_sec_session *sess, struct rte_crypto_op *cop) @@ -44,18 +48,14 @@ ipsec_po_sa_aes_gcm_iv_set(struct cn10k_sec_session *sess, struct rte_crypto_op static __rte_always_inline int process_outb_sa(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k_sec_session *sess, - struct cpt_inst_s *inst) + struct cpt_qp_meta_info *m_info, struct cpt_inflight_req *infl_req, + struct cpt_inst_s *inst, const bool is_sg_ver2) { struct rte_crypto_sym_op *sym_op = cop->sym; struct rte_mbuf *m_src = sym_op->m_src; uint64_t inst_w4_u64 = sess->inst.w4; uint64_t dptr; - if (unlikely(rte_pktmbuf_tailroom(m_src) < sess->max_extended_len)) { - plt_dp_err("Not enough tail room"); - return -ENOMEM; - } - RTE_SET_USED(lf); #ifdef LA_IPSEC_DEBUG @@ -79,27 +79,217 @@ process_outb_sa(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k_s if (m_src->ol_flags & RTE_MBUF_F_TX_L4_MASK) inst_w4_u64 &= ~BIT_ULL(32); - /* Prepare CPT instruction */ - inst->w4.u64 = inst_w4_u64 | rte_pktmbuf_pkt_len(m_src); - dptr = rte_pktmbuf_mtod(m_src, uint64_t); - inst->dptr = dptr; + if (likely(m_src->next == NULL)) { + if (unlikely(rte_pktmbuf_tailroom(m_src) < sess->max_extended_len)) { + plt_dp_err("Not enough tail room"); + return -ENOMEM; + } + + /* Prepare CPT instruction */ + inst->w4.u64 = inst_w4_u64 | rte_pktmbuf_pkt_len(m_src); + dptr = rte_pktmbuf_mtod(m_src, uint64_t); + inst->dptr = dptr; + } else if (is_sg_ver2 == false) { + struct roc_sglist_comp *scatter_comp, *gather_comp; + uint32_t g_size_bytes, s_size_bytes; + struct rte_mbuf *last_seg; + uint8_t *in_buffer; + uint32_t dlen; + void *m_data; + int i; + + last_seg = rte_pktmbuf_lastseg(m_src); + + if (unlikely(rte_pktmbuf_tailroom(last_seg) < sess->max_extended_len)) { + plt_dp_err("Not enough tail room (required: %d, available: %d)", + sess->max_extended_len, rte_pktmbuf_tailroom(last_seg)); + return -ENOMEM; + } + + m_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req); + if (unlikely(m_data == NULL)) { + plt_dp_err("Error allocating meta buffer for request"); + return -ENOMEM; + } + + in_buffer = m_data; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* Input Gather List */ + i = 0; + gather_comp = (struct roc_sglist_comp *)((uint8_t *)m_data + 8); + + i = fill_ipsec_sg_comp_from_pkt(gather_comp, i, m_src); + ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); + + g_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp); + + /* Output Scatter List */ + last_seg->data_len += sess->max_extended_len; + + i = 0; + scatter_comp = (struct roc_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes); + + i = fill_ipsec_sg_comp_from_pkt(scatter_comp, i, m_src); + ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i); + + s_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp); + + dlen = g_size_bytes + s_size_bytes + ROC_SG_LIST_HDR_SIZE; + + inst->dptr = (uint64_t)in_buffer; + + inst->w4.u64 = sess->inst.w4 | dlen; + inst->w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG; + } else { + struct roc_sg2list_comp *scatter_comp, *gather_comp; + union cpt_inst_w5 cpt_inst_w5; + union cpt_inst_w6 cpt_inst_w6; + struct rte_mbuf *last_seg; + uint32_t g_size_bytes; + void *m_data; + int i; + + last_seg = rte_pktmbuf_lastseg(m_src); + + if (unlikely(rte_pktmbuf_tailroom(last_seg) < sess->max_extended_len)) { + plt_dp_err("Not enough tail room (required: %d, available: %d)", + sess->max_extended_len, rte_pktmbuf_tailroom(last_seg)); + return -ENOMEM; + } + + m_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req); + if (unlikely(m_data == NULL)) { + plt_dp_err("Error allocating meta buffer for request"); + return -ENOMEM; + } + + /* Input Gather List */ + i = 0; + gather_comp = (struct roc_sg2list_comp *)((uint8_t *)m_data); + + i = fill_ipsec_sg2_comp_from_pkt(gather_comp, i, m_src); + + cpt_inst_w5.s.gather_sz = ((i + 2) / 3); + g_size_bytes = ((i + 2) / 3) * sizeof(struct roc_sg2list_comp); + + /* Output Scatter List */ + last_seg->data_len += sess->max_extended_len; + + i = 0; + scatter_comp = (struct roc_sg2list_comp *)((uint8_t *)gather_comp + g_size_bytes); + + i = fill_ipsec_sg2_comp_from_pkt(scatter_comp, i, m_src); + + cpt_inst_w6.s.scatter_sz = ((i + 2) / 3); + + cpt_inst_w5.s.dptr = (uint64_t)gather_comp; + cpt_inst_w6.s.rptr = (uint64_t)scatter_comp; + + inst->w5.u64 = cpt_inst_w5.u64; + inst->w6.u64 = cpt_inst_w6.u64; + inst->w4.u64 = sess->inst.w4 | rte_pktmbuf_pkt_len(m_src); + inst->w4.s.opcode_major &= (~(ROC_IE_OT_INPLACE_BIT)); + } return 0; } static __rte_always_inline int -process_inb_sa(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, struct cpt_inst_s *inst) +process_inb_sa(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, struct cpt_inst_s *inst, + struct cpt_qp_meta_info *m_info, struct cpt_inflight_req *infl_req, + const bool is_sg_ver2) { struct rte_crypto_sym_op *sym_op = cop->sym; struct rte_mbuf *m_src = sym_op->m_src; uint64_t dptr; - /* Prepare CPT instruction */ - inst->w4.u64 = sess->inst.w4 | rte_pktmbuf_pkt_len(m_src); - dptr = rte_pktmbuf_mtod(m_src, uint64_t); - inst->dptr = dptr; - m_src->ol_flags |= (uint64_t)sess->ip_csum; + if (likely(m_src->next == NULL)) { + /* Prepare CPT instruction */ + inst->w4.u64 = sess->inst.w4 | rte_pktmbuf_pkt_len(m_src); + dptr = rte_pktmbuf_mtod(m_src, uint64_t); + inst->dptr = dptr; + m_src->ol_flags |= (uint64_t)sess->ip_csum; + } else if (is_sg_ver2 == false) { + struct roc_sglist_comp *scatter_comp, *gather_comp; + uint32_t g_size_bytes, s_size_bytes; + uint8_t *in_buffer; + uint32_t dlen; + void *m_data; + int i; + + m_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req); + if (unlikely(m_data == NULL)) { + plt_dp_err("Error allocating meta buffer for request"); + return -ENOMEM; + } + + in_buffer = m_data; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* Input Gather List */ + i = 0; + gather_comp = (struct roc_sglist_comp *)((uint8_t *)m_data + 8); + i = fill_ipsec_sg_comp_from_pkt(gather_comp, i, m_src); + ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); + + g_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp); + /* Output Scatter List */ + i = 0; + scatter_comp = (struct roc_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes); + i = fill_ipsec_sg_comp_from_pkt(scatter_comp, i, m_src); + ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i); + + s_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp); + + dlen = g_size_bytes + s_size_bytes + ROC_SG_LIST_HDR_SIZE; + + inst->dptr = (uint64_t)in_buffer; + inst->w4.u64 = sess->inst.w4 | dlen; + inst->w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG; + } else { + struct roc_sg2list_comp *scatter_comp, *gather_comp; + union cpt_inst_w5 cpt_inst_w5; + union cpt_inst_w6 cpt_inst_w6; + uint32_t g_size_bytes; + void *m_data; + int i; + + m_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req); + if (unlikely(m_data == NULL)) { + plt_dp_err("Error allocating meta buffer for request"); + return -ENOMEM; + } + + /* Input Gather List */ + i = 0; + gather_comp = (struct roc_sg2list_comp *)((uint8_t *)m_data); + + i = fill_ipsec_sg2_comp_from_pkt(gather_comp, i, m_src); + + cpt_inst_w5.s.gather_sz = ((i + 2) / 3); + g_size_bytes = ((i + 2) / 3) * sizeof(struct roc_sg2list_comp); + + /* Output Scatter List */ + i = 0; + scatter_comp = (struct roc_sg2list_comp *)((uint8_t *)gather_comp + g_size_bytes); + i = fill_ipsec_sg2_comp_from_pkt(scatter_comp, i, m_src); + + cpt_inst_w6.s.scatter_sz = ((i + 2) / 3); + + cpt_inst_w5.s.dptr = (uint64_t)gather_comp; + cpt_inst_w6.s.rptr = (uint64_t)scatter_comp; + + inst->w5.u64 = cpt_inst_w5.u64; + inst->w6.u64 = cpt_inst_w6.u64; + inst->w4.u64 = sess->inst.w4 | rte_pktmbuf_pkt_len(m_src); + inst->w4.s.opcode_major &= (~(ROC_IE_OT_INPLACE_BIT)); + } return 0; } diff --git a/drivers/crypto/cnxk/cnxk_sg.h b/drivers/crypto/cnxk/cnxk_sg.h index ead2886e99..65244199bd 100644 --- a/drivers/crypto/cnxk/cnxk_sg.h +++ b/drivers/crypto/cnxk/cnxk_sg.h @@ -6,6 +6,7 @@ #define _CNXK_SG_H_ #include "roc_cpt_sg.h" +#include "roc_se.h" static __rte_always_inline uint32_t fill_sg_comp(struct roc_sglist_comp *list, uint32_t i, phys_addr_t dma_addr, uint32_t size) @@ -148,6 +149,28 @@ fill_ipsec_sg_comp_from_pkt(struct roc_sglist_comp *list, uint32_t i, struct rte return i; } +static __rte_always_inline uint32_t +fill_ipsec_sg2_comp_from_pkt(struct roc_sg2list_comp *list, uint32_t i, struct rte_mbuf *pkt) +{ + uint32_t buf_sz; + void *vaddr; + + while (unlikely(pkt != NULL)) { + struct roc_sg2list_comp *to = &list[i / 3]; + buf_sz = pkt->data_len; + vaddr = rte_pktmbuf_mtod(pkt, void *); + + to->u.s.len[i % 3] = buf_sz; + to->ptr[i % 3] = (uint64_t)vaddr; + to->u.s.valid_segs = (i % 3) + 1; + + pkt = pkt->next; + i++; + } + + return i; +} + static __rte_always_inline uint32_t fill_sg2_comp(struct roc_sg2list_comp *list, uint32_t i, phys_addr_t dma_addr, uint32_t size) { From patchwork Fri Feb 24 09:40:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 124516 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5456F41D5F; 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Fri, 24 Feb 2023 01:40:38 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Feb 2023 01:40:37 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 24 Feb 2023 01:40:36 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 6DE585B692E; Fri, 24 Feb 2023 01:40:35 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Gowrishankar Muthukrishnan , Anoob Joseph , Subject: [PATCH v2 10/11] crypto/cnxk: fix order of ECFPM params Date: Fri, 24 Feb 2023 15:10:13 +0530 Message-ID: <20230224094014.3246764-11-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: kme_FtEBV7noaF4W_VvC1A9fspoWl3IT X-Proofpoint-ORIG-GUID: kme_FtEBV7noaF4W_VvC1A9fspoWl3IT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-24_05,2023-02-23_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Gowrishankar Muthukrishnan Fix the order of ECFPM parameters according to target board. Fixes: 8e39b133235 ("crypto/cnxk: support fixed point multiplication") Signed-off-by: Gowrishankar Muthukrishnan --- drivers/crypto/cnxk/cnxk_ae.h | 48 ++++++++++++++++++++--------------- 1 file changed, 28 insertions(+), 20 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_ae.h b/drivers/crypto/cnxk/cnxk_ae.h index b7c13a9e01..47f000dd5e 100644 --- a/drivers/crypto/cnxk/cnxk_ae.h +++ b/drivers/crypto/cnxk/cnxk_ae.h @@ -700,7 +700,7 @@ static __rte_always_inline int cnxk_ae_ecfpm_prep(struct rte_crypto_ecpm_op_param *ecpm, struct roc_ae_buf_ptr *meta_buf, uint64_t *fpm_iova, struct roc_ae_ec_group *ec_grp, uint8_t curveid, - struct cpt_inst_s *inst) + struct cpt_inst_s *inst, int cpt_ver) { uint16_t scalar_align, p_align; uint16_t dlen, prime_len; @@ -719,26 +719,33 @@ cnxk_ae_ecfpm_prep(struct rte_crypto_ecpm_op_param *ecpm, scalar_align = RTE_ALIGN_CEIL(ecpm->scalar.length, 8); /* - * Set dlen = sum(ROUNDUP8(input point(x and y coordinates), prime, - * scalar length), + * Set dlen = sum(prime, scalar length, table address and + * optionally ROUNDUP8(input point(x and y coordinates)). * Please note point length is equivalent to prime of the curve */ - dlen = sizeof(fpm_table_iova) + 3 * p_align + scalar_align; - - memset(dptr, 0, dlen); - - *(uint64_t *)dptr = fpm_table_iova; - dptr += sizeof(fpm_table_iova); - - /* Copy scalar, prime */ - memcpy(dptr, ecpm->scalar.data, ecpm->scalar.length); - dptr += scalar_align; - memcpy(dptr, ec_grp->prime.data, ec_grp->prime.length); - dptr += p_align; - memcpy(dptr, ec_grp->consta.data, ec_grp->consta.length); - dptr += p_align; - memcpy(dptr, ec_grp->constb.data, ec_grp->constb.length); - dptr += p_align; + if (cpt_ver == ROC_CPT_REVISION_ID_96XX_C0) { + dlen = sizeof(fpm_table_iova) + 3 * p_align + scalar_align; + memset(dptr, 0, dlen); + *(uint64_t *)dptr = fpm_table_iova; + dptr += sizeof(fpm_table_iova); + memcpy(dptr, ecpm->scalar.data, ecpm->scalar.length); + dptr += scalar_align; + memcpy(dptr, ec_grp->prime.data, ec_grp->prime.length); + dptr += p_align; + memcpy(dptr, ec_grp->consta.data, ec_grp->consta.length); + dptr += p_align; + memcpy(dptr, ec_grp->constb.data, ec_grp->constb.length); + dptr += p_align; + } else { + dlen = sizeof(fpm_table_iova) + p_align + scalar_align; + memset(dptr, 0, dlen); + memcpy(dptr, ecpm->scalar.data, ecpm->scalar.length); + dptr += scalar_align; + memcpy(dptr, ec_grp->prime.data, ec_grp->prime.length); + dptr += p_align; + *(uint64_t *)dptr = fpm_table_iova; + dptr += sizeof(fpm_table_iova); + } /* Setup opcodes */ w4.s.opcode_major = ROC_AE_MAJOR_OP_ECC; @@ -969,7 +976,8 @@ cnxk_ae_enqueue(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, ret = cnxk_ae_ecfpm_prep(&asym_op->ecpm, &meta_buf, sess->cnxk_fpm_iova, sess->ec_grp[sess->ec_ctx.curveid], - sess->ec_ctx.curveid, inst); + sess->ec_ctx.curveid, inst, + sess->lf->roc_cpt->cpt_revision); if (unlikely(ret)) goto req_fail; break; From patchwork Fri Feb 24 09:40:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 124517 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5549541D5F; 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Fri, 24 Feb 2023 01:40:41 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Feb 2023 01:40:39 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 24 Feb 2023 01:40:39 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 742D55B6921; Fri, 24 Feb 2023 01:40:37 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Gowrishankar Muthukrishnan , Subject: [PATCH v2 11/11] crypto/cnxk: add model check for pdcp chain Date: Fri, 24 Feb 2023 15:10:14 +0530 Message-ID: <20230224094014.3246764-12-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: wMWme1cOyaht3G8OzaWmnuk_UD5pazfl X-Proofpoint-ORIG-GUID: wMWme1cOyaht3G8OzaWmnuk_UD5pazfl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-24_05,2023-02-23_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding cn9k model check for pdcp_chain as it is not supported in cn10k. Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index adc1c7652b..86efe75cc3 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -479,7 +479,7 @@ cnxk_sess_fill(struct roc_cpt *roc_cpt, struct rte_crypto_sym_xform *xform, bool pdcp_chain_supported = false; bool ciph_then_auth = false; - if (roc_cpt->hw_caps[CPT_ENG_TYPE_SE].pdcp_chain) + if (roc_model_is_cn9k() && (roc_cpt->hw_caps[CPT_ENG_TYPE_SE].pdcp_chain)) pdcp_chain_supported = true; if (xform == NULL)