From patchwork Fri May 19 08:31:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 127103 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8495942B47; Fri, 19 May 2023 10:37:00 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 755604282D; Fri, 19 May 2023 10:37:00 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 8E27940F16; Fri, 19 May 2023 10:36:58 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684485418; x=1716021418; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ACqcnx8xDgGo6vtDtcl3UGmMonmAob34dU+jelCNfP4=; b=b7J8+8KGAgMT3KvYcm1UKF9S7f6MTrSIxYMNXwJks9jZxeeIzGfCfJEa RfZQtTEesZ/WVPfyjrOrFtkGoGofvhNIiyCLkLDCq2KdvuBW2cvYZ8Nab S47kcIIv5kaMvqkt7BWedMMD0gBOQFzwU6tCm/3np/4T6WsF/YbNB/4z+ L2mpzUimaOTwi/YvGSq+YIN6t5Irg1L0nQebsb3ktxtRrQzIXOOxYBUMP tT4VlvFVdDdmA6vJQcZZt/b/4qoKVwD/38PIYEXKBtbzaSSKpYT0ohXWe mHihlOp6KpyrTAgByZ4WnzPyK2GKTw/sV6Ygb4JLO6/+5i4d/03Uo3Xce w==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="354670369" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="354670369" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 01:36:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="772216212" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="772216212" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.161]) by fmsmga004.fm.intel.com with ESMTP; 19 May 2023 01:36:55 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v4 1/7] common/idpf: fix 64b timestamp roll over issue Date: Fri, 19 May 2023 04:31:04 -0400 Message-Id: <20230519083110.809913-2-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230519083110.809913-1-wenjing.qiao@intel.com> References: <20230424091707.488045-2-wenjing.qiao@intel.com> <20230519083110.809913-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Reading MTS register at first packet will cause timestamp roll over issue. To support calculating 64b timestamp, need an alarm to save main time from registers every 1 second. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao --- drivers/common/idpf/idpf_common_rxtx.c | 126 ++++++++++++++----------- drivers/common/idpf/idpf_common_rxtx.h | 6 +- drivers/common/idpf/version.map | 2 + 3 files changed, 77 insertions(+), 57 deletions(-) diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c index fc87e3e243..b487c2a8a6 100644 --- a/drivers/common/idpf/idpf_common_rxtx.c +++ b/drivers/common/idpf/idpf_common_rxtx.c @@ -4,6 +4,7 @@ #include #include +#include #include "idpf_common_rxtx.h" @@ -349,6 +350,46 @@ idpf_qc_tx_queue_release(void *txq) rte_free(q); } +#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000 +static void +idpf_dev_read_time_hw(void *cb_arg) +{ +#ifdef RTE_ARCH_X86_64 + struct idpf_adapter *ad = (struct idpf_adapter *)cb_arg; + uint32_t hi, lo, lo2; + int rc = 0; + struct idpf_hw *hw = &ad->hw; + + IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); + IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, + PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); + lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0); + hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0); + /* + * On typical system, the delta between lo and lo2 is ~1000ns, + * so 10000 seems a large-enough but not overly-big guard band. + */ + if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND)) + lo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0); + else + lo2 = lo; + + if (lo2 < lo) { + lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0); + hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0); + } + + ad->time_hw = ((uint64_t)hi << 32) | lo; +#else /* !RTE_ARCH_X86_64 */ + ad->time_hw = 0; +#endif /* RTE_ARCH_X86_64 */ + + /* re-alarm watchdog */ + rc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg); + if (rc) + DRV_LOG(ERR, "Failed to reset device watchdog alarm"); +} + int idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq) { @@ -366,6 +407,24 @@ idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq) return 0; } + +int +idpf_rx_timestamp_start(struct idpf_adapter *base) +{ + rte_eal_alarm_set(1000 * 1000, + &idpf_dev_read_time_hw, + (void *)base); + return 0; +} + +int +idpf_rx_timestamp_stop(struct idpf_adapter *base) +{ + rte_eal_alarm_cancel(idpf_dev_read_time_hw, + base); + return 0; +} + int idpf_qc_single_rxq_mbufs_alloc(struct idpf_rx_queue *rxq) { @@ -442,56 +501,23 @@ idpf_qc_split_rxq_mbufs_alloc(struct idpf_rx_queue *rxq) return 0; } -#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000 /* Helper function to convert a 32b nanoseconds timestamp to 64b. */ static inline uint64_t -idpf_tstamp_convert_32b_64b(struct idpf_adapter *ad, uint32_t flag, - uint32_t in_timestamp) +idpf_tstamp_convert_32b_64b(uint64_t time_hw, uint32_t in_timestamp) { -#ifdef RTE_ARCH_X86_64 - struct idpf_hw *hw = &ad->hw; const uint64_t mask = 0xFFFFFFFF; - uint32_t hi, lo, lo2, delta; + const uint32_t half_overflow_duration = 0x1 << 31; + uint32_t delta; uint64_t ns; - if (flag != 0) { - IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); - IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | - PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); - lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0); - hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0); - /* - * On typical system, the delta between lo and lo2 is ~1000ns, - * so 10000 seems a large-enough but not overly-big guard band. - */ - if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND)) - lo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0); - else - lo2 = lo; - - if (lo2 < lo) { - lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0); - hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0); - } - - ad->time_hw = ((uint64_t)hi << 32) | lo; - } - - delta = (in_timestamp - (uint32_t)(ad->time_hw & mask)); - if (delta > (mask / 2)) { - delta = ((uint32_t)(ad->time_hw & mask) - in_timestamp); - ns = ad->time_hw - delta; + delta = (in_timestamp - (uint32_t)(time_hw & mask)); + if (delta > half_overflow_duration) { + delta = ((uint32_t)(time_hw & mask) - in_timestamp); + ns = time_hw - delta; } else { - ns = ad->time_hw + delta; + ns = time_hw + delta; } - return ns; -#else /* !RTE_ARCH_X86_64 */ - RTE_SET_USED(ad); - RTE_SET_USED(flag); - RTE_SET_USED(in_timestamp); - return 0; -#endif /* RTE_ARCH_X86_64 */ } #define IDPF_RX_FLEX_DESC_ADV_STATUS0_XSUM_S \ @@ -659,9 +685,6 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, rx_desc_ring = rxq->rx_ring; ptype_tbl = rxq->adapter->ptype_tbl; - if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) - rxq->hw_register_set = 1; - while (nb_rx < nb_pkts) { rx_desc = &rx_desc_ring[rx_id]; @@ -720,10 +743,8 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, if (idpf_timestamp_dynflag > 0 && (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) { /* timestamp */ - ts_ns = idpf_tstamp_convert_32b_64b(ad, - rxq->hw_register_set, + ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw, rte_le_to_cpu_32(rx_desc->ts_high)); - rxq->hw_register_set = 0; *RTE_MBUF_DYNFIELD(rxm, idpf_timestamp_dynfield_offset, rte_mbuf_timestamp_t *) = ts_ns; @@ -1077,9 +1098,6 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, rx_ring = rxq->rx_ring; ptype_tbl = rxq->adapter->ptype_tbl; - if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) - rxq->hw_register_set = 1; - while (nb_rx < nb_pkts) { rxdp = &rx_ring[rx_id]; rx_status0 = rte_le_to_cpu_16(rxdp->flex_nic_wb.status_error0); @@ -1142,10 +1160,8 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, if (idpf_timestamp_dynflag > 0 && (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) { /* timestamp */ - ts_ns = idpf_tstamp_convert_32b_64b(ad, - rxq->hw_register_set, + ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw, rte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high)); - rxq->hw_register_set = 0; *RTE_MBUF_DYNFIELD(rxm, idpf_timestamp_dynfield_offset, rte_mbuf_timestamp_t *) = ts_ns; @@ -1272,10 +1288,8 @@ idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, if (idpf_timestamp_dynflag > 0 && (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) { /* timestamp */ - ts_ns = idpf_tstamp_convert_32b_64b(ad, - rxq->hw_register_set, + ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw, rte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high)); - rxq->hw_register_set = 0; *RTE_MBUF_DYNFIELD(rxm, idpf_timestamp_dynfield_offset, rte_mbuf_timestamp_t *) = ts_ns; diff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h index 6cb83fc0a6..53049b1a31 100644 --- a/drivers/common/idpf/idpf_common_rxtx.h +++ b/drivers/common/idpf/idpf_common_rxtx.h @@ -145,7 +145,6 @@ struct idpf_rx_queue { struct idpf_rx_queue *bufq2; uint64_t offloads; - uint32_t hw_register_set; }; struct idpf_tx_entry { @@ -303,4 +302,9 @@ __rte_internal uint16_t idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); +__rte_internal +int idpf_rx_timestamp_start(struct idpf_adapter *base); + +__rte_internal +int idpf_rx_timestamp_stop(struct idpf_adapter *base); #endif /* _IDPF_COMMON_RXTX_H_ */ diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map index 70334a1b03..661c7f5cb9 100644 --- a/drivers/common/idpf/version.map +++ b/drivers/common/idpf/version.map @@ -34,6 +34,8 @@ INTERNAL { idpf_qc_tx_thresh_check; idpf_qc_tx_vec_avx512_setup; idpf_qc_txq_mbufs_release; + idpf_rx_timestamp_start; + idpf_rx_timestamp_stop; idpf_vc_api_version_check; idpf_vc_caps_get; From patchwork Fri May 19 08:31:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 127104 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1723442B47; Fri, 19 May 2023 10:37:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E25CB42D3D; Fri, 19 May 2023 10:37:01 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id CAF7740F16; Fri, 19 May 2023 10:36:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; 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19 May 2023 01:36:57 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v4 2/7] net/idpf: save main time by alarm Date: Fri, 19 May 2023 04:31:05 -0400 Message-Id: <20230519083110.809913-3-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230519083110.809913-1-wenjing.qiao@intel.com> References: <20230424091707.488045-2-wenjing.qiao@intel.com> <20230519083110.809913-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Using alarm to save main time from registers every 1 second. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao --- drivers/net/idpf/idpf_ethdev.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c index 7a33b9eb6a..21f3d0f76a 100644 --- a/drivers/net/idpf/idpf_ethdev.c +++ b/drivers/net/idpf/idpf_ethdev.c @@ -761,6 +761,9 @@ idpf_dev_start(struct rte_eth_dev *dev) goto err_vec; } + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) + idpf_rx_timestamp_start(base); + ret = idpf_vc_vectors_alloc(vport, req_vecs_num); if (ret != 0) { PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors"); @@ -808,6 +811,7 @@ static int idpf_dev_stop(struct rte_eth_dev *dev) { struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *base = vport->adapter; if (dev->data->dev_started == 0) return 0; @@ -820,6 +824,9 @@ idpf_dev_stop(struct rte_eth_dev *dev) idpf_vc_vectors_dealloc(vport); + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) + idpf_rx_timestamp_stop(base); + return 0; } From patchwork Fri May 19 08:31:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 127105 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E48F142B47; Fri, 19 May 2023 10:37:11 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0A99742D37; Fri, 19 May 2023 10:37:04 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 99DB142D2D; Fri, 19 May 2023 10:37:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684485421; x=1716021421; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HrwRMFjw+OxVylIb8IK8lo6TbYMXS1yTkJHC5lMY6ts=; b=jCx8SIZOiSVJ3zvZdxOg5Xy8MhmpaAF+dFoAf2SqmYGjJk26Gk6sScL0 O2Xu7N6OCtOMmazTW9Hlr3Bo7J/O7/wigN5TJ6JwWKN1A+8unp9oNbnb0 QxF8kOVSE96hioccWeerG48DKXcE/QblNV1M31qFdztEOYPWbldAW8dUf BR9dMT2pppD0eOf/GBNVLO/5BCTVkQoiYEQEV6nrTsNaH9zunlux6AIAh XhPzbq0+LNz6X4i+J+WeJiM7EKpTMoj3rg3qIHw8Fr+fsjn/zI7KGE90t J65LdVKoDwYm7P1z9U09oGR59zXW56Dv2LxyRIA9tZEooXVUu9mx3Hfzz Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="354670390" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="354670390" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 01:37:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="772216238" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="772216238" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.161]) by fmsmga004.fm.intel.com with ESMTP; 19 May 2023 01:36:59 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v4 3/7] net/cpfl: save main time by alarm Date: Fri, 19 May 2023 04:31:06 -0400 Message-Id: <20230519083110.809913-4-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230519083110.809913-1-wenjing.qiao@intel.com> References: <20230424091707.488045-2-wenjing.qiao@intel.com> <20230519083110.809913-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Using alarm to save main time from registers every 1 second. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao --- drivers/net/cpfl/cpfl_ethdev.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 7528a14d05..702fd6f4ec 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -767,6 +767,9 @@ cpfl_dev_start(struct rte_eth_dev *dev) goto err_vec; } + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) + idpf_rx_timestamp_start(base); + ret = idpf_vc_vectors_alloc(vport, req_vecs_num); if (ret != 0) { PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors"); @@ -814,6 +817,7 @@ static int cpfl_dev_stop(struct rte_eth_dev *dev) { struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *base = vport->adapter; if (dev->data->dev_started == 0) return 0; @@ -826,6 +830,9 @@ cpfl_dev_stop(struct rte_eth_dev *dev) idpf_vc_vectors_dealloc(vport); + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) + idpf_rx_timestamp_stop(base); + return 0; } From patchwork Fri May 19 08:31:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 127106 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D005142B47; Fri, 19 May 2023 10:37:19 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 73EF742D51; Fri, 19 May 2023 10:37:05 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 021B542D2D; Fri, 19 May 2023 10:37:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684485424; x=1716021424; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KcoauCa+T8bBnh9bHnHPnvUS1ER/ylUeJxpIjDv7Ifw=; b=SpTrH26Z9oGEWo6OodJLhPPXb+5W6+aTdMkCX8jv8gSDAT8wyw1ze/KU PDQvx0Ii8CJ33Dz8GK0roRXc1sjHZHWRSH0nfkn2IP4K2i8ZA8SmsbDdN tMzV3JHaJrWpP/j7yxw4DhIc6rKbPfGaApxDcpPUo2dR7A69z/fVBXH8C A96Cg8GjOToQPx9fv2DdIfV+cSks632v050ochAwwBhJXUR/1sTSV9AAQ cJQQjqaQUuZNS1lcDup+yESLB8+45f7Z/eSNN6flQhq+4QWtOaSXqx0sW 7uvA+w2c5GybbVu9J/KvJin+xQ6u4IQMrmayxM5jqHePSAG0BOgV7ph0C g==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="354670399" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="354670399" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 01:37:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="772216246" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="772216246" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.161]) by fmsmga004.fm.intel.com with ESMTP; 19 May 2023 01:37:01 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v4 4/7] common/idpf: enhance timestamp offload feature for ACC Date: Fri, 19 May 2023 04:31:07 -0400 Message-Id: <20230519083110.809913-5-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230519083110.809913-1-wenjing.qiao@intel.com> References: <20230424091707.488045-2-wenjing.qiao@intel.com> <20230519083110.809913-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For ACC, getting main time from MTS registers by shared memory. Notice: it is a workaround, and it will be removed after generic solution are provided. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_osdep.h | 48 ++++++++++++++++++++++++++ drivers/common/idpf/idpf_common_rxtx.c | 30 +++++++++++++--- drivers/common/idpf/meson.build | 2 ++ 3 files changed, 76 insertions(+), 4 deletions(-) diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h index 2a817a9807..d1668aa603 100644 --- a/drivers/common/idpf/base/idpf_osdep.h +++ b/drivers/common/idpf/base/idpf_osdep.h @@ -25,6 +25,13 @@ #include #include +#ifdef IDPF_ACC_TIMESTAMP +#include +#include +#include +#include +#endif /* IDPF_ACC_TIMESTAMP */ + #define INLINE inline #define STATIC static @@ -346,4 +353,45 @@ idpf_hweight32(u32 num) #endif +#ifdef IDPF_ACC_TIMESTAMP +#define IDPF_ACC_TIMESYNC_BASE_ADDR 0x480D500000 +#define IDPF_ACC_GLTSYN_TIME_H (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x1C) +#define IDPF_ACC_GLTSYN_TIME_L (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x10) + +inline uint32_t +idpf_mmap_r32(uint64_t pa) +{ + int fd; + void *bp, *vp; + uint32_t rval = 0xdeadbeef; + uint32_t ps, ml, of; + + fd = open("/dev/mem", (O_RDWR | O_SYNC)); + if (fd == -1) { + perror("/dev/mem"); + return -1; + } + ml = ps = getpagesize(); + of = (uint32_t)pa & (ps - 1); + if (of + (sizeof(uint32_t) * 4) > ps) + ml *= 2; + bp = mmap(NULL, ml, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, pa & ~(uint64_t)(ps - 1)); + if (bp == MAP_FAILED) { + perror("mmap"); + goto done; + } + + vp = (char *)bp + of; + + rval = *(volatile uint32_t *)vp; + if (munmap(bp, ml) == -1) + perror("munmap"); +done: + close(fd); + + return rval; +} + +#endif /* IDPF_ACC_TIMESTAMP */ + #endif /* _IDPF_OSDEP_H_ */ diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c index b487c2a8a6..13e94dda43 100644 --- a/drivers/common/idpf/idpf_common_rxtx.c +++ b/drivers/common/idpf/idpf_common_rxtx.c @@ -354,12 +354,36 @@ idpf_qc_tx_queue_release(void *txq) static void idpf_dev_read_time_hw(void *cb_arg) { -#ifdef RTE_ARCH_X86_64 struct idpf_adapter *ad = (struct idpf_adapter *)cb_arg; uint32_t hi, lo, lo2; int rc = 0; +#ifndef IDPF_ACC_TIMESTAMP struct idpf_hw *hw = &ad->hw; +#endif /* !IDPF_ACC_TIMESTAMP */ +#ifdef IDPF_ACC_TIMESTAMP + + lo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L); + hi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H); + DRV_LOG(DEBUG, "lo : %X,", lo); + DRV_LOG(DEBUG, "hi : %X,", hi); + /* + * On typical system, the delta between lo and lo2 is ~1000ns, + * so 10000 seems a large-enough but not overly-big guard band. + */ + if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND)) + lo2 = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L); + else + lo2 = lo; + + if (lo2 < lo) { + lo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L); + hi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H); + } + + ad->time_hw = ((uint64_t)hi << 32) | lo; + +#else /* !IDPF_ACC_TIMESTAMP */ IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); @@ -380,9 +404,7 @@ idpf_dev_read_time_hw(void *cb_arg) } ad->time_hw = ((uint64_t)hi << 32) | lo; -#else /* !RTE_ARCH_X86_64 */ - ad->time_hw = 0; -#endif /* RTE_ARCH_X86_64 */ +#endif /* IDPF_ACC_TIMESTAMP */ /* re-alarm watchdog */ rc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg); diff --git a/drivers/common/idpf/meson.build b/drivers/common/idpf/meson.build index 80c8906f80..11682a27d5 100644 --- a/drivers/common/idpf/meson.build +++ b/drivers/common/idpf/meson.build @@ -45,3 +45,5 @@ if arch_subdir == 'x86' endif subdir('base') + + dpdk_conf.set('IDPF_ACC_TIMESTAMP', false) From patchwork Fri May 19 08:31:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 127107 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 93B1442B47; Fri, 19 May 2023 10:37:26 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8C6E342D42; Fri, 19 May 2023 10:37:08 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id AD19842D42; Fri, 19 May 2023 10:37:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684485427; x=1716021427; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gFvaESTTjiVW0tiWlhJwyzLxp5kB4NstfGGR+7MIiDY=; b=YMvZZTLeetBWgQuWvZ321wdfzMz15cxr9pcvtCY7IvPmpiIR00J0UaHc 7jLdiSmKC23bNfsaVz+lWAj0Dbll8E6a2O7IlZ7G4mPAQQ8ipq30uyZaX mjX/X1Rn0sDqP9hz6BkWAjeoMD21kBLMtUU+xpA8pFR4JMxjtzwBzkHxQ uVvJ940UrbCtVFeVpKKZj8OMWW6vVV5T2RmRmTkwsijs+tfE/Uh9YT6o4 S8gDHQoNoSQsb8RQ+/XscKoNdm1Gc64kcaNs1vGvJzOeCv6H00+l/X2wg pUo4hbaUp+jhpHfHoQaGx454HyJdpUNS0KzWsETU2nx39SrXyG+xfDiOm w==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="354670409" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="354670409" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 01:37:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="772216254" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="772216254" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.161]) by fmsmga004.fm.intel.com with ESMTP; 19 May 2023 01:37:03 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v4 5/7] common/idpf: add timestamp enable flag for rxq Date: Fri, 19 May 2023 04:31:08 -0400 Message-Id: <20230519083110.809913-6-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230519083110.809913-1-wenjing.qiao@intel.com> References: <20230424091707.488045-2-wenjing.qiao@intel.com> <20230519083110.809913-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org A rxq can be configured with timestamp offload. So, add timestamp enable flag for rxq. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao Suggested-by: Jingjing Wu --- drivers/common/idpf/idpf_common_rxtx.c | 11 ++++++++++- drivers/common/idpf/idpf_common_rxtx.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c index 13e94dda43..26aaddb106 100644 --- a/drivers/common/idpf/idpf_common_rxtx.c +++ b/drivers/common/idpf/idpf_common_rxtx.c @@ -416,7 +416,7 @@ int idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq) { int err; - if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) { + if (!rxq->ts_enable && (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) { /* Register mbuf field and flag for Rx timestamp */ err = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset, &idpf_timestamp_dynflag); @@ -425,6 +425,7 @@ idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq) "Cannot register mbuf field/flag for timestamp"); return -EINVAL; } + rxq->ts_enable = TRUE; } return 0; } @@ -433,9 +434,17 @@ idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq) int idpf_rx_timestamp_start(struct idpf_adapter *base) { + int ret; rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, (void *)base); + /* Register mbuf field and flag for Rx timestamp */ + ret = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset, + &idpf_timestamp_dynflag); + if (ret != 0) { + DRV_LOG(ERR, "Cannot register mbuf field/flag for timestamp"); + return -EINVAL; + } return 0; } diff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h index 53049b1a31..e902c4f275 100644 --- a/drivers/common/idpf/idpf_common_rxtx.h +++ b/drivers/common/idpf/idpf_common_rxtx.h @@ -145,6 +145,8 @@ struct idpf_rx_queue { struct idpf_rx_queue *bufq2; uint64_t offloads; + + bool ts_enable; /* if timestamp is enabled */ }; struct idpf_tx_entry { From patchwork Fri May 19 08:31:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 127108 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 34D3442B47; Fri, 19 May 2023 10:37:34 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D7A8A42D65; Fri, 19 May 2023 10:37:09 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id A884042D31; Fri, 19 May 2023 10:37:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684485428; x=1716021428; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=11In9lJFWJQsHMiBcR933U4CVzkIIQRr9DuKLpq9vYA=; b=iq9t0ORfoqVaJLvdUTffiznnbNTPaQzNoJ8WQmE9VTtvaEYkBM1+sCLc DbuodaU/tVjIpexg6aJ5ezpNPDVqIar5JNqUDVZk0FWor222efVyoVqua /Zxalh37eldIMUL1uV9JSwVvs1eNLwq1CTr53SrEJoZFBtQJaZ7cGGAxI 46RDgHBG04nHpMO2Od/BpGEe8w9lxtBzJZVb+KvQpyf+PtuEkRLPEytcQ atxv47xkNEvsJ+0ZMX0tLgEVZkkLHHKR8jAPqrtqsGyiuAiZOYxs6/XOi 3152iqdL1UAWx8odpZ8s6Hlk8p8PLOuyj1ix72BILglAah+2fESsHIbKX w==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="354670416" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="354670416" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 01:37:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="772216269" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="772216269" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.161]) by fmsmga004.fm.intel.com with ESMTP; 19 May 2023 01:37:04 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v4 6/7] net/cpfl: adjust timestamp mbuf register Date: Fri, 19 May 2023 04:31:09 -0400 Message-Id: <20230519083110.809913-7-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230519083110.809913-1-wenjing.qiao@intel.com> References: <20230424091707.488045-2-wenjing.qiao@intel.com> <20230519083110.809913-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Due to only support timestamp at port level, adjust timestamp mbuf register to dev config. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao Suggested-by: Jingjing Wu --- drivers/net/cpfl/cpfl_ethdev.c | 9 +++++++-- drivers/net/cpfl/cpfl_rxtx.c | 2 ++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 702fd6f4ec..a6a17d03f9 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -767,8 +767,13 @@ cpfl_dev_start(struct rte_eth_dev *dev) goto err_vec; } - if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) - idpf_rx_timestamp_start(base); + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) { + ret = idpf_rx_timestamp_start(base); + if (ret != 0) { + PMD_DRV_LOG(ERR, "Failed to register mbuf for timestamp"); + goto err_vec; + } + } ret = idpf_vc_vectors_alloc(vport, req_vecs_num); if (ret != 0) { diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index 75021c3c54..4781059f2c 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -530,6 +530,8 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) frame_size > rxq->rx_buf_len) dev->data->scattered_rx = 1; + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) + rxq->ts_enable = TRUE; err = idpf_qc_ts_mbuf_register(rxq); if (err != 0) { PMD_DRV_LOG(ERR, "fail to register timestamp mbuf %u", From patchwork Fri May 19 08:31:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 127109 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 561C742B47; Fri, 19 May 2023 10:37:42 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BDC2042D85; Fri, 19 May 2023 10:37:12 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 31BBD42D55; Fri, 19 May 2023 10:37:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684485429; x=1716021429; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fWt4FMjSCaxhJTnzJOhRbGUESSwEJ/jpJjCITHFvffY=; b=BLEe7LPGspbsHYwaKq+LKn9B7Vnt8QTbt29QvQwy/0EP1eRAhD9ofoGt 4ZCf8uvjXh7wjxLn35HfplEhTurefez/cAZfVGBLBLNo/iIx39AHoNwMg 78+yMdKVhq5lFugwt/vuj+cOzLwvquPavqmntypnrLwjb88D7DfWDozT5 5QcCekA9EDTp/kfYbWhEcp8PRedVHT2FR1OLniV9+WYJzwk6I4lYwuJa3 FqBHdUhJCw9OugZZBbaQPYZQvS4pr0CXlejmmRHIUyVqmf60lm5owzzCM nJnMuNdV/ZUy7yyptizDksjRF/yz3Om9BM5rBYlR/RvJKu9jXi+sr/KMw g==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="354670423" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="354670423" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 01:37:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="772216285" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="772216285" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.161]) by fmsmga004.fm.intel.com with ESMTP; 19 May 2023 01:37:06 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v4 7/7] net/idpf: adjust timestamp mbuf register Date: Fri, 19 May 2023 04:31:10 -0400 Message-Id: <20230519083110.809913-8-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230519083110.809913-1-wenjing.qiao@intel.com> References: <20230424091707.488045-2-wenjing.qiao@intel.com> <20230519083110.809913-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Due to only support timestamp at port level, adjust timestamp mbuf register to dev config. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao Suggested-by: Jingjing Wu --- drivers/net/idpf/idpf_ethdev.c | 9 +++++++-- drivers/net/idpf/idpf_rxtx.c | 3 +++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c index 21f3d0f76a..18c5844adb 100644 --- a/drivers/net/idpf/idpf_ethdev.c +++ b/drivers/net/idpf/idpf_ethdev.c @@ -761,8 +761,13 @@ idpf_dev_start(struct rte_eth_dev *dev) goto err_vec; } - if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) - idpf_rx_timestamp_start(base); + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) { + ret = idpf_rx_timestamp_start(base); + if (ret != 0) { + PMD_DRV_LOG(ERR, "Failed to register mbuf for timestamp"); + goto err_vec; + } + } ret = idpf_vc_vectors_alloc(vport, req_vecs_num); if (ret != 0) { diff --git a/drivers/net/idpf/idpf_rxtx.c b/drivers/net/idpf/idpf_rxtx.c index 3e3d81ca6d..6c893c64a8 100644 --- a/drivers/net/idpf/idpf_rxtx.c +++ b/drivers/net/idpf/idpf_rxtx.c @@ -531,6 +531,9 @@ idpf_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) frame_size > rxq->rx_buf_len) dev->data->scattered_rx = 1; + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) + rxq->ts_enable = TRUE; + err = idpf_qc_ts_mbuf_register(rxq); if (err != 0) { PMD_DRV_LOG(ERR, "fail to residter timestamp mbuf %u",