From patchwork Wed Jun 7 15:28:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128339 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A863042C4E; Wed, 7 Jun 2023 17:28:33 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 39E28410FD; Wed, 7 Jun 2023 17:28:33 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 35CA5410F9 for ; Wed, 7 Jun 2023 17:28:31 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 357Dvh3k028140; Wed, 7 Jun 2023 08:28:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=T9DEFMci5ixUOmIFDkC/CslVZz8sBxmzvjXU6uHynvQ=; b=J526C8BSAnaQgeHzPI5+hCSeknf9lt35l37WEI5yD2x7qcQJLGpKgD+eoVcCfEsZz9dM E3BPHqZcLFoB4u6EqAIm1f0JhYokc+T6+OlmwBXJx5EKG5+791tYcLKLllmE6DrXQBdU TXeUl8JzvWISojwKB1EzK1IlOX3eC7wXqSTLN40Cx3R4fq25NmRD74xJT1nKeeVrmZsQ MFPRYBnAFV/BXsrHaZCEwStPVzpXtfZ5EKLXGO5/rL6MT9o6pR91Qmx/d5qPWzhpVsCV LqvIU1++2nhn+/yYWiG7MaQ5ok3u81otsh1YpFgnRm6owEkvjHcUE82Fed3p7qyrSR5b 5g== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r2a7bv7sr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 07 Jun 2023 08:28:29 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 7 Jun 2023 08:28:27 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:28:27 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id EB72E3F7088; Wed, 7 Jun 2023 08:28:24 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 01/15] common/cnxk: add ROC MACsec initialization Date: Wed, 7 Jun 2023 20:58:05 +0530 Message-ID: <20230607152819.226838-2-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: zJ32CUDRp0ixv9_3ETGHTGInA4ZiaGQC X-Proofpoint-GUID: zJ32CUDRp0ixv9_3ETGHTGInA4ZiaGQC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added ROC init and fini APIs for supporting MACsec. Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_api.h | 3 + drivers/common/cnxk/roc_features.h | 12 ++ drivers/common/cnxk/roc_idev.c | 46 ++++++ drivers/common/cnxk/roc_idev.h | 3 + drivers/common/cnxk/roc_idev_priv.h | 1 + drivers/common/cnxk/roc_mbox.h | 65 +++++++- drivers/common/cnxk/roc_mcs.c | 220 ++++++++++++++++++++++++++++ drivers/common/cnxk/roc_mcs.h | 41 ++++++ drivers/common/cnxk/roc_mcs_priv.h | 65 ++++++++ drivers/common/cnxk/roc_priv.h | 3 + drivers/common/cnxk/roc_utils.c | 5 + drivers/common/cnxk/version.map | 7 + 13 files changed, 471 insertions(+), 1 deletion(-) create mode 100644 drivers/common/cnxk/roc_mcs.c create mode 100644 drivers/common/cnxk/roc_mcs.h create mode 100644 drivers/common/cnxk/roc_mcs_priv.h diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 631b594f32..e33c002676 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -26,6 +26,7 @@ sources = files( 'roc_irq.c', 'roc_ie_ot.c', 'roc_mbox.c', + 'roc_mcs.c', 'roc_ml.c', 'roc_model.c', 'roc_nix.c', diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h index bbc94ab48e..f630853088 100644 --- a/drivers/common/cnxk/roc_api.h +++ b/drivers/common/cnxk/roc_api.h @@ -114,4 +114,7 @@ /* ML */ #include "roc_ml.h" +/* MACsec */ +#include "roc_mcs.h" + #endif /* _ROC_API_H_ */ diff --git a/drivers/common/cnxk/roc_features.h b/drivers/common/cnxk/roc_features.h index 36ef315f5a..815f800e7a 100644 --- a/drivers/common/cnxk/roc_features.h +++ b/drivers/common/cnxk/roc_features.h @@ -59,4 +59,16 @@ roc_feature_nix_has_age_drop_stats(void) { return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0()); } + +static inline bool +roc_feature_nix_has_macsec(void) +{ + return roc_model_is_cn10kb(); +} + +static inline bool +roc_feature_bphy_has_macsec(void) +{ + return roc_model_is_cnf10kb(); +} #endif diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c index f420f0158d..e6c6b34d78 100644 --- a/drivers/common/cnxk/roc_idev.c +++ b/drivers/common/cnxk/roc_idev.c @@ -38,6 +38,7 @@ idev_set_defaults(struct idev_cfg *idev) idev->num_lmtlines = 0; idev->bphy = NULL; idev->cpt = NULL; + TAILQ_INIT(&idev->mcs_list); idev->nix_inl_dev = NULL; TAILQ_INIT(&idev->roc_nix_list); plt_spinlock_init(&idev->nix_inl_dev_lock); @@ -187,6 +188,51 @@ roc_idev_cpt_get(void) return NULL; } +struct roc_mcs * +roc_idev_mcs_get(uint8_t mcs_idx) +{ + struct idev_cfg *idev = idev_get_cfg(); + struct roc_mcs *mcs = NULL; + + if (idev != NULL) { + TAILQ_FOREACH(mcs, &idev->mcs_list, next) { + if (mcs->idx == mcs_idx) + return mcs; + } + } + + return NULL; +} + +void +roc_idev_mcs_set(struct roc_mcs *mcs) +{ + struct idev_cfg *idev = idev_get_cfg(); + struct roc_mcs *mcs_iter = NULL; + + if (idev != NULL) { + TAILQ_FOREACH(mcs_iter, &idev->mcs_list, next) { + if (mcs_iter->idx == mcs->idx) + return; + } + TAILQ_INSERT_TAIL(&idev->mcs_list, mcs, next); + } +} + +void +roc_idev_mcs_free(struct roc_mcs *mcs) +{ + struct idev_cfg *idev = idev_get_cfg(); + struct roc_mcs *mcs_iter = NULL; + + if (idev != NULL) { + TAILQ_FOREACH(mcs_iter, &idev->mcs_list, next) { + if (mcs_iter->idx == mcs->idx) + TAILQ_REMOVE(&idev->mcs_list, mcs, next); + } + } +} + uint64_t * roc_nix_inl_outb_ring_base_get(struct roc_nix *roc_nix) { diff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h index 640ca97708..aea7f5279d 100644 --- a/drivers/common/cnxk/roc_idev.h +++ b/drivers/common/cnxk/roc_idev.h @@ -19,4 +19,7 @@ struct roc_nix *__roc_api roc_idev_npa_nix_get(void); uint64_t __roc_api roc_idev_nix_inl_meta_aura_get(void); struct roc_nix_list *__roc_api roc_idev_nix_list_get(void); +struct roc_mcs *__roc_api roc_idev_mcs_get(uint8_t mcs_idx); +void __roc_api roc_idev_mcs_set(struct roc_mcs *mcs); +void __roc_api roc_idev_mcs_free(struct roc_mcs *mcs); #endif /* _ROC_IDEV_H_ */ diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h index 4983578fc6..80f8465e1c 100644 --- a/drivers/common/cnxk/roc_idev_priv.h +++ b/drivers/common/cnxk/roc_idev_priv.h @@ -31,6 +31,7 @@ struct idev_cfg { struct roc_bphy *bphy; struct roc_cpt *cpt; struct roc_sso *sso; + struct roc_mcs_head mcs_list; struct nix_inl_dev *nix_inl_dev; struct idev_nix_inl_cfg inl_cfg; struct roc_nix_list roc_nix_list; diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 93c5451c0f..ef7a7d6513 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -295,7 +295,12 @@ struct mbox_msghdr { nix_bpids) \ M(NIX_FREE_BPIDS, 0x8029, nix_free_bpids, nix_bpids, msg_rsp) \ M(NIX_RX_CHAN_CFG, 0x802a, nix_rx_chan_cfg, nix_rx_chan_cfg, \ - nix_rx_chan_cfg) + nix_rx_chan_cfg) \ + /* MCS mbox IDs (range 0xa000 - 0xbFFF) */ \ + M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ + mcs_alloc_rsrc_rsp) \ + M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ + M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ /* Messages initiated by AF (range 0xC00 - 0xDFF) */ #define MBOX_UP_CGX_MESSAGES \ @@ -673,6 +678,64 @@ struct cgx_set_link_mode_rsp { int __io status; }; +/* MCS mbox structures */ +enum mcs_direction { + MCS_RX, + MCS_TX, +}; + +enum mcs_rsrc_type { + MCS_RSRC_TYPE_FLOWID, + MCS_RSRC_TYPE_SECY, + MCS_RSRC_TYPE_SC, + MCS_RSRC_TYPE_SA, +}; + +struct mcs_alloc_rsrc_req { + struct mbox_msghdr hdr; + uint8_t __io rsrc_type; + uint8_t __io rsrc_cnt; /* Resources count */ + uint8_t __io mcs_id; /* MCS block ID */ + uint8_t __io dir; /* Macsec ingress or egress side */ + uint8_t __io all; /* Allocate all resource type one each */ + uint64_t __io rsvd; +}; + +struct mcs_alloc_rsrc_rsp { + struct mbox_msghdr hdr; + uint8_t __io flow_ids[128]; /* Index of reserved entries */ + uint8_t __io secy_ids[128]; + uint8_t __io sc_ids[128]; + uint8_t __io sa_ids[256]; + uint8_t __io rsrc_type; + uint8_t __io rsrc_cnt; /* No of entries reserved */ + uint8_t __io mcs_id; + uint8_t __io dir; + uint8_t __io all; + uint8_t __io rsvd[256]; +}; + +struct mcs_free_rsrc_req { + struct mbox_msghdr hdr; + uint8_t __io rsrc_id; /* Index of the entry to be freed */ + uint8_t __io rsrc_type; + uint8_t __io mcs_id; + uint8_t __io dir; + uint8_t __io all; /* Free all the cam resources */ + uint64_t __io rsvd; +}; + +struct mcs_hw_info { + struct mbox_msghdr hdr; + uint8_t __io num_mcs_blks; /* Number of MCS blocks */ + uint8_t __io tcam_entries; /* RX/TX Tcam entries per mcs block */ + uint8_t __io secy_entries; /* RX/TX SECY entries per mcs block */ + uint8_t __io sc_entries; /* RX/TX SC CAM entries per mcs block */ + uint16_t __io sa_entries; /* PN table entries = SA entries */ + uint64_t __io rsvd[16]; +}; + + /* NPA mbox message formats */ /* NPA mailbox error codes diff --git a/drivers/common/cnxk/roc_mcs.c b/drivers/common/cnxk/roc_mcs.c new file mode 100644 index 0000000000..20433eae83 --- /dev/null +++ b/drivers/common/cnxk/roc_mcs.c @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2022 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" + +int +roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info) +{ + struct mcs_hw_info *hw; + struct npa_lf *npa; + int rc; + + MCS_SUPPORT_CHECK; + + if (hw_info == NULL) + return -EINVAL; + + /* Use mbox handler of first probed pci_func for + * initial mcs mbox communication. + */ + npa = idev_npa_obj_get(); + if (!npa) + return MCS_ERR_DEVICE_NOT_FOUND; + + mbox_alloc_msg_mcs_get_hw_info(npa->mbox); + rc = mbox_process_msg(npa->mbox, (void *)&hw); + if (rc) + return rc; + + hw_info->num_mcs_blks = hw->num_mcs_blks; + hw_info->tcam_entries = hw->tcam_entries; + hw_info->secy_entries = hw->secy_entries; + hw_info->sc_entries = hw->sc_entries; + hw_info->sa_entries = hw->sa_entries; + + return rc; +} + +static int +mcs_alloc_bmap(uint16_t entries, void **mem, struct plt_bitmap **bmap) +{ + size_t bmap_sz; + int rc = 0; + + bmap_sz = plt_bitmap_get_memory_footprint(entries); + *mem = plt_zmalloc(bmap_sz, PLT_CACHE_LINE_SIZE); + if (*mem == NULL) + rc = -ENOMEM; + + *bmap = plt_bitmap_init(entries, *mem, bmap_sz); + if (!*bmap) { + plt_free(*mem); + *mem = NULL; + rc = -ENOMEM; + } + + return rc; +} + +static void +rsrc_bmap_free(struct mcs_rsrc *rsrc) +{ + plt_bitmap_free(rsrc->tcam_bmap); + plt_free(rsrc->tcam_bmap_mem); + plt_bitmap_free(rsrc->secy_bmap); + plt_free(rsrc->secy_bmap_mem); + plt_bitmap_free(rsrc->sc_bmap); + plt_free(rsrc->sc_bmap_mem); + plt_bitmap_free(rsrc->sa_bmap); + plt_free(rsrc->sa_bmap_mem); +} + +static int +rsrc_bmap_alloc(struct mcs_priv *priv, struct mcs_rsrc *rsrc) +{ + int rc; + + rc = mcs_alloc_bmap(priv->tcam_entries << 1, &rsrc->tcam_bmap_mem, &rsrc->tcam_bmap); + if (rc) + goto exit; + + rc = mcs_alloc_bmap(priv->secy_entries << 1, &rsrc->secy_bmap_mem, &rsrc->secy_bmap); + if (rc) + goto exit; + + rc = mcs_alloc_bmap(priv->sc_entries << 1, &rsrc->sc_bmap_mem, &rsrc->sc_bmap); + if (rc) + goto exit; + + rc = mcs_alloc_bmap(priv->sa_entries << 1, &rsrc->sa_bmap_mem, &rsrc->sa_bmap); + if (rc) + goto exit; + + return rc; +exit: + rsrc_bmap_free(rsrc); + + return rc; +} + +static int +mcs_alloc_rsrc_bmap(struct roc_mcs *mcs) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct mcs_hw_info *hw; + int i, rc; + + mbox_alloc_msg_mcs_get_hw_info(mcs->mbox); + rc = mbox_process_msg(mcs->mbox, (void *)&hw); + if (rc) + return rc; + + priv->num_mcs_blks = hw->num_mcs_blks; + priv->tcam_entries = hw->tcam_entries; + priv->secy_entries = hw->secy_entries; + priv->sc_entries = hw->sc_entries; + priv->sa_entries = hw->sa_entries; + + rc = rsrc_bmap_alloc(priv, &priv->dev_rsrc); + if (rc) + return rc; + + priv->port_rsrc = plt_zmalloc(sizeof(struct mcs_rsrc) * 4, 0); + if (priv->port_rsrc == NULL) { + rsrc_bmap_free(&priv->dev_rsrc); + return -ENOMEM; + } + + for (i = 0; i < MAX_PORTS_PER_MCS; i++) { + rc = rsrc_bmap_alloc(priv, &priv->port_rsrc[i]); + if (rc) + goto exit; + + priv->port_rsrc[i].sc_conf = + plt_zmalloc(priv->sc_entries * sizeof(struct mcs_sc_conf), 0); + if (priv->port_rsrc[i].sc_conf == NULL) { + rsrc_bmap_free(&priv->port_rsrc[i]); + goto exit; + } + } + + return rc; + +exit: + while (i--) { + rsrc_bmap_free(&priv->port_rsrc[i]); + plt_free(priv->port_rsrc[i].sc_conf); + } + plt_free(priv->port_rsrc); + + return -ENOMEM; +} + +struct roc_mcs * +roc_mcs_dev_init(uint8_t mcs_idx) +{ + struct roc_mcs *mcs; + struct npa_lf *npa; + + if (!(roc_feature_bphy_has_macsec() || roc_feature_nix_has_macsec())) + return NULL; + + mcs = roc_idev_mcs_get(mcs_idx); + if (mcs) { + plt_info("Skipping device, mcs device already probed"); + mcs->refcount++; + return mcs; + } + + mcs = plt_zmalloc(sizeof(struct roc_mcs), PLT_CACHE_LINE_SIZE); + if (!mcs) + return NULL; + + npa = idev_npa_obj_get(); + if (!npa) + goto exit; + + mcs->mbox = npa->mbox; + mcs->idx = mcs_idx; + + /* Add any per mcsv initialization */ + if (mcs_alloc_rsrc_bmap(mcs)) + goto exit; + + roc_idev_mcs_set(mcs); + mcs->refcount++; + + return mcs; +exit: + plt_free(mcs); + return NULL; +} + +void +roc_mcs_dev_fini(struct roc_mcs *mcs) +{ + struct mcs_priv *priv; + int i; + + mcs->refcount--; + if (mcs->refcount > 0) + return; + + priv = roc_mcs_to_mcs_priv(mcs); + + rsrc_bmap_free(&priv->dev_rsrc); + + for (i = 0; i < MAX_PORTS_PER_MCS; i++) { + rsrc_bmap_free(&priv->port_rsrc[i]); + plt_free(priv->port_rsrc[i].sc_conf); + } + + plt_free(priv->port_rsrc); + + roc_idev_mcs_free(mcs); + + plt_free(mcs); +} diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h new file mode 100644 index 0000000000..2f06ce2659 --- /dev/null +++ b/drivers/common/cnxk/roc_mcs.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2022 Marvell. + */ + +#ifndef _ROC_MCS_H_ +#define _ROC_MCS_H_ + +#define MCS_AES_GCM_256_KEYLEN 32 + +struct roc_mcs_hw_info { + uint8_t num_mcs_blks; /* Number of MCS blocks */ + uint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */ + uint8_t secy_entries; /* RX/TX SECY entries per mcs block */ + uint8_t sc_entries; /* RX/TX SC CAM entries per mcs block */ + uint16_t sa_entries; /* PN table entries = SA entries */ + uint64_t rsvd[16]; +}; + + +struct roc_mcs { + TAILQ_ENTRY(roc_mcs) next; + struct plt_pci_device *pci_dev; + struct mbox *mbox; + void *userdata; + uint8_t idx; + uint8_t refcount; + +#define ROC_MCS_MEM_SZ (1 * 1024) + uint8_t reserved[ROC_MCS_MEM_SZ] __plt_cache_aligned; +} __plt_cache_aligned; + +TAILQ_HEAD(roc_mcs_head, roc_mcs); + +/* Initialization */ +__roc_api struct roc_mcs *roc_mcs_dev_init(uint8_t mcs_idx); +__roc_api void roc_mcs_dev_fini(struct roc_mcs *mcs); +/* Get roc mcs dev structure */ +__roc_api struct roc_mcs *roc_mcs_dev_get(uint8_t mcs_idx); +/* HW info get */ +__roc_api int roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info); +#endif /* _ROC_MCS_H_ */ diff --git a/drivers/common/cnxk/roc_mcs_priv.h b/drivers/common/cnxk/roc_mcs_priv.h new file mode 100644 index 0000000000..9e0bbe4392 --- /dev/null +++ b/drivers/common/cnxk/roc_mcs_priv.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2022 Marvell. + */ + +#ifndef _ROC_MCS_PRIV_H_ +#define _ROC_MCS_PRIV_H_ + +#define MAX_PORTS_PER_MCS 4 + +enum mcs_error_status { + MCS_ERR_PARAM = -900, + MCS_ERR_HW_NOTSUP = -901, + MCS_ERR_DEVICE_NOT_FOUND = -902, +}; + +#define MCS_SUPPORT_CHECK \ + do { \ + if (!(roc_feature_bphy_has_macsec() || roc_feature_nix_has_macsec())) \ + return MCS_ERR_HW_NOTSUP; \ + } while (0) + +struct mcs_sc_conf { + struct { + uint64_t sci; + uint16_t sa_idx0; + uint16_t sa_idx1; + uint8_t rekey_enb; + } tx; + struct { + uint16_t sa_idx; + uint8_t an; + } rx; +}; + +struct mcs_rsrc { + struct plt_bitmap *tcam_bmap; + void *tcam_bmap_mem; + struct plt_bitmap *secy_bmap; + void *secy_bmap_mem; + struct plt_bitmap *sc_bmap; + void *sc_bmap_mem; + struct plt_bitmap *sa_bmap; + void *sa_bmap_mem; + struct mcs_sc_conf *sc_conf; +}; + +struct mcs_priv { + struct mcs_rsrc *port_rsrc; + struct mcs_rsrc dev_rsrc; + uint64_t default_sci; + uint32_t lmac_bmap; + uint8_t num_mcs_blks; + uint8_t tcam_entries; + uint8_t secy_entries; + uint8_t sc_entries; + uint16_t sa_entries; +}; + +static inline struct mcs_priv * +roc_mcs_to_mcs_priv(struct roc_mcs *roc_mcs) +{ + return (struct mcs_priv *)&roc_mcs->reserved[0]; +} + +#endif /* _ROC_MCS_PRIV_H_ */ diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h index 14fe2e452a..254a2d3310 100644 --- a/drivers/common/cnxk/roc_priv.h +++ b/drivers/common/cnxk/roc_priv.h @@ -44,6 +44,9 @@ /* DPI */ #include "roc_dpi_priv.h" +/* MCS */ +#include "roc_mcs_priv.h" + /* REE */ #include "roc_ree_priv.h" diff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c index fe291fce96..9af2ae9b69 100644 --- a/drivers/common/cnxk/roc_utils.c +++ b/drivers/common/cnxk/roc_utils.c @@ -16,6 +16,7 @@ roc_error_msg_get(int errorcode) case NPA_ERR_PARAM: case NPC_ERR_PARAM: case SSO_ERR_PARAM: + case MCS_ERR_PARAM: case UTIL_ERR_PARAM: err_msg = "Invalid parameter"; break; @@ -35,6 +36,7 @@ roc_error_msg_get(int errorcode) err_msg = "Operation not supported"; break; case NIX_ERR_HW_NOTSUP: + case MCS_ERR_HW_NOTSUP: err_msg = "Hardware does not support"; break; case NIX_ERR_QUEUE_INVALID_RANGE: @@ -223,6 +225,9 @@ roc_error_msg_get(int errorcode) case SSO_ERR_DEVICE_NOT_BOUNDED: err_msg = "SSO pf/vf not found"; break; + case MCS_ERR_DEVICE_NOT_FOUND: + err_msg = "MCS device not found"; + break; case UTIL_ERR_FS: err_msg = "file operation failed"; break; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index e1335e9068..900290b866 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -94,6 +94,9 @@ INTERNAL { roc_idev_cpt_get; roc_idev_cpt_set; roc_idev_lmt_base_addr_get; + roc_idev_mcs_free; + roc_idev_mcs_get; + roc_idev_mcs_set; roc_idev_npa_maxpools_get; roc_idev_npa_maxpools_set; roc_idev_npa_nix_get; @@ -132,6 +135,10 @@ INTERNAL { roc_se_auth_key_set; roc_se_ciph_key_set; roc_se_ctx_init; + roc_mcs_dev_init; + roc_mcs_dev_fini; + roc_mcs_dev_get; + roc_mcs_hw_info_get; roc_nix_bpf_alloc; roc_nix_bpf_config; roc_nix_bpf_connect; From patchwork Wed Jun 7 15:28:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128340 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53CAF42C4E; Wed, 7 Jun 2023 17:28:39 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 76D2742C4D; Wed, 7 Jun 2023 17:28:35 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4E1A941149 for ; Wed, 7 Jun 2023 17:28:33 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 357Dvh1n028122; Wed, 7 Jun 2023 08:28:32 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=gHP4iRk11xbbzV0BPqN2egs1bV2C9463G8IoxkRIZpI=; b=WGyhlzZOoaK6HGUBserfgdbwRmw8N5/Fn2jdjFZq9lt5d1Foiv//dGrYeIjV/wOuehQN ncc/zqCTNwtFncEH0fPNbTb3nkHL80rENTF7vymbJBuhSdGUvspmZDrSVOUP+/0+7aA5 NZyTm9fJRKVW4gfm1AAtFhEn1lEqXVAZHyDKtAIqf+yjCV001p+NAq6EBTE4lTYyzMUk DcC6cNXcmhe2RDUEpLrUxf/ZieSHMktg9cZ7cHVhQivL4qLtJW/M7cjU8cOy5sKS+xUY x72qnLSl+DHCWaSa3XuWU3jsO+nVxZCx3+GtAwsPA5GewVaN3b6N1Cuu9G0Wzm2p6ifG xQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r2a7bv7t4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 07 Jun 2023 08:28:32 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 7 Jun 2023 08:28:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:28:30 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id DF1703F7084; Wed, 7 Jun 2023 08:28:27 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 02/15] common/cnxk: add MACsec SA configuration Date: Wed, 7 Jun 2023 20:58:06 +0530 Message-ID: <20230607152819.226838-3-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: teQnRqAxXcLFSevWcK-7m_od9mcbMsF8 X-Proofpoint-GUID: teQnRqAxXcLFSevWcK-7m_od9mcbMsF8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added ROC APIs to allocate/free MACsec resources and APIs to write SA policy. Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_mbox.h | 12 ++ drivers/common/cnxk/roc_mcs.h | 43 ++++++ drivers/common/cnxk/roc_mcs_sec_cfg.c | 211 ++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 4 + 5 files changed, 271 insertions(+) create mode 100644 drivers/common/cnxk/roc_mcs_sec_cfg.c diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index e33c002676..589baf74fe 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -27,6 +27,7 @@ sources = files( 'roc_ie_ot.c', 'roc_mbox.c', 'roc_mcs.c', + 'roc_mcs_sec_cfg.c', 'roc_ml.c', 'roc_model.c', 'roc_nix.c', diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index ef7a7d6513..ab1173e805 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -300,6 +300,7 @@ struct mbox_msghdr { M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ mcs_alloc_rsrc_rsp) \ M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ + M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, msg_rsp) \ M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ /* Messages initiated by AF (range 0xC00 - 0xDFF) */ @@ -725,6 +726,17 @@ struct mcs_free_rsrc_req { uint64_t __io rsvd; }; +struct mcs_sa_plcy_write_req { + struct mbox_msghdr hdr; + uint64_t __io plcy[2][9]; /* Support 2 SA policy */ + uint8_t __io sa_index[2]; + uint8_t __io sa_cnt; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + + struct mcs_hw_info { struct mbox_msghdr hdr; uint8_t __io num_mcs_blks; /* Number of MCS blocks */ diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h index 2f06ce2659..ea4c6ddc05 100644 --- a/drivers/common/cnxk/roc_mcs.h +++ b/drivers/common/cnxk/roc_mcs.h @@ -7,6 +7,39 @@ #define MCS_AES_GCM_256_KEYLEN 32 +struct roc_mcs_alloc_rsrc_req { + uint8_t rsrc_type; + uint8_t rsrc_cnt; /* Resources count */ + uint8_t dir; /* Macsec ingress or egress side */ + uint8_t all; /* Allocate all resource type one each */ +}; + +struct roc_mcs_alloc_rsrc_rsp { + uint8_t flow_ids[128]; /* Index of reserved entries */ + uint8_t secy_ids[128]; + uint8_t sc_ids[128]; + uint8_t sa_ids[256]; + uint8_t rsrc_type; + uint8_t rsrc_cnt; /* No of entries reserved */ + uint8_t dir; + uint8_t all; +}; + +struct roc_mcs_free_rsrc_req { + uint8_t rsrc_id; /* Index of the entry to be freed */ + uint8_t rsrc_type; + uint8_t dir; + uint8_t all; /* Free all the cam resources */ +}; + + +struct roc_mcs_sa_plcy_write_req { + uint64_t plcy[2][9]; + uint8_t sa_index[2]; + uint8_t sa_cnt; + uint8_t dir; +}; + struct roc_mcs_hw_info { uint8_t num_mcs_blks; /* Number of MCS blocks */ uint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */ @@ -38,4 +71,14 @@ __roc_api void roc_mcs_dev_fini(struct roc_mcs *mcs); __roc_api struct roc_mcs *roc_mcs_dev_get(uint8_t mcs_idx); /* HW info get */ __roc_api int roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info); + +/* Resource allocation and free */ +__roc_api int roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req, + struct roc_mcs_alloc_rsrc_rsp *rsp); +__roc_api int roc_mcs_rsrc_free(struct roc_mcs *mcs, struct roc_mcs_free_rsrc_req *req); +/* SA policy read and write */ +__roc_api int roc_mcs_sa_policy_write(struct roc_mcs *mcs, + struct roc_mcs_sa_plcy_write_req *sa_plcy); +__roc_api int roc_mcs_sa_policy_read(struct roc_mcs *mcs, + struct roc_mcs_sa_plcy_write_req *sa_plcy); #endif /* _ROC_MCS_H_ */ diff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c new file mode 100644 index 0000000000..041be51b4b --- /dev/null +++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2023 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" + +int +roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req, + struct roc_mcs_alloc_rsrc_rsp *rsp) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct mcs_alloc_rsrc_req *rsrc_req; + struct mcs_alloc_rsrc_rsp *rsrc_rsp; + int rc, i; + + MCS_SUPPORT_CHECK; + + if (req == NULL || rsp == NULL) + return -EINVAL; + + rsrc_req = mbox_alloc_msg_mcs_alloc_resources(mcs->mbox); + if (rsrc_req == NULL) + return -ENOMEM; + + rsrc_req->rsrc_type = req->rsrc_type; + rsrc_req->rsrc_cnt = req->rsrc_cnt; + rsrc_req->mcs_id = mcs->idx; + rsrc_req->dir = req->dir; + rsrc_req->all = req->all; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsrc_rsp); + if (rc) + return rc; + + if (rsrc_rsp->all) { + rsrc_rsp->rsrc_cnt = 1; + rsrc_rsp->rsrc_type = 0xFF; + } + + for (i = 0; i < rsrc_rsp->rsrc_cnt; i++) { + switch (rsrc_rsp->rsrc_type) { + case MCS_RSRC_TYPE_FLOWID: + rsp->flow_ids[i] = rsrc_rsp->flow_ids[i]; + plt_bitmap_set(priv->dev_rsrc.tcam_bmap, + rsp->flow_ids[i] + + ((req->dir == MCS_TX) ? priv->tcam_entries : 0)); + break; + case MCS_RSRC_TYPE_SECY: + rsp->secy_ids[i] = rsrc_rsp->secy_ids[i]; + plt_bitmap_set(priv->dev_rsrc.secy_bmap, + rsp->secy_ids[i] + + ((req->dir == MCS_TX) ? priv->secy_entries : 0)); + break; + case MCS_RSRC_TYPE_SC: + rsp->sc_ids[i] = rsrc_rsp->sc_ids[i]; + plt_bitmap_set(priv->dev_rsrc.sc_bmap, + rsp->sc_ids[i] + + ((req->dir == MCS_TX) ? priv->sc_entries : 0)); + break; + case MCS_RSRC_TYPE_SA: + rsp->sa_ids[i] = rsrc_rsp->sa_ids[i]; + plt_bitmap_set(priv->dev_rsrc.sa_bmap, + rsp->sa_ids[i] + + ((req->dir == MCS_TX) ? priv->sa_entries : 0)); + break; + default: + rsp->flow_ids[i] = rsrc_rsp->flow_ids[i]; + rsp->secy_ids[i] = rsrc_rsp->secy_ids[i]; + rsp->sc_ids[i] = rsrc_rsp->sc_ids[i]; + rsp->sa_ids[i] = rsrc_rsp->sa_ids[i]; + plt_bitmap_set(priv->dev_rsrc.tcam_bmap, + rsp->flow_ids[i] + + ((req->dir == MCS_TX) ? priv->tcam_entries : 0)); + plt_bitmap_set(priv->dev_rsrc.secy_bmap, + rsp->secy_ids[i] + + ((req->dir == MCS_TX) ? priv->secy_entries : 0)); + plt_bitmap_set(priv->dev_rsrc.sc_bmap, + rsp->sc_ids[i] + + ((req->dir == MCS_TX) ? priv->sc_entries : 0)); + plt_bitmap_set(priv->dev_rsrc.sa_bmap, + rsp->sa_ids[i] + + ((req->dir == MCS_TX) ? priv->sa_entries : 0)); + break; + } + } + rsp->rsrc_type = rsrc_rsp->rsrc_type; + rsp->rsrc_cnt = rsrc_rsp->rsrc_cnt; + rsp->dir = rsrc_rsp->dir; + rsp->all = rsrc_rsp->all; + + return 0; +} + +int +roc_mcs_rsrc_free(struct roc_mcs *mcs, struct roc_mcs_free_rsrc_req *free_req) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct mcs_free_rsrc_req *req; + struct msg_rsp *rsp; + uint32_t pos; + int i, rc; + + MCS_SUPPORT_CHECK; + + if (free_req == NULL) + return -EINVAL; + + req = mbox_alloc_msg_mcs_free_resources(mcs->mbox); + if (req == NULL) + return -ENOMEM; + + req->rsrc_id = free_req->rsrc_id; + req->rsrc_type = free_req->rsrc_type; + req->mcs_id = mcs->idx; + req->dir = free_req->dir; + req->all = free_req->all; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + switch (free_req->rsrc_type) { + case MCS_RSRC_TYPE_FLOWID: + pos = free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->tcam_entries : 0); + plt_bitmap_clear(priv->dev_rsrc.tcam_bmap, pos); + for (i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].tcam_bmap, pos); + + if (set) { + plt_bitmap_clear(priv->port_rsrc[i].tcam_bmap, pos); + break; + } + } + break; + case MCS_RSRC_TYPE_SECY: + pos = free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->secy_entries : 0); + plt_bitmap_clear(priv->dev_rsrc.secy_bmap, pos); + for (i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].secy_bmap, pos); + + if (set) { + plt_bitmap_clear(priv->port_rsrc[i].secy_bmap, pos); + break; + } + } + break; + case MCS_RSRC_TYPE_SC: + pos = free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->sc_entries : 0); + plt_bitmap_clear(priv->dev_rsrc.sc_bmap, pos); + for (i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].sc_bmap, pos); + + if (set) { + plt_bitmap_clear(priv->port_rsrc[i].sc_bmap, pos); + break; + } + } + break; + case MCS_RSRC_TYPE_SA: + pos = free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->sa_entries : 0); + plt_bitmap_clear(priv->dev_rsrc.sa_bmap, pos); + for (i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].sa_bmap, pos); + + if (set) { + plt_bitmap_clear(priv->port_rsrc[i].sa_bmap, pos); + break; + } + } + break; + default: + break; + } + + return rc; +} + +int +roc_mcs_sa_policy_write(struct roc_mcs *mcs, struct roc_mcs_sa_plcy_write_req *sa_plcy) +{ + struct mcs_sa_plcy_write_req *sa; + struct msg_rsp *rsp; + + MCS_SUPPORT_CHECK; + + if (sa_plcy == NULL) + return -EINVAL; + + sa = mbox_alloc_msg_mcs_sa_plcy_write(mcs->mbox); + if (sa == NULL) + return -ENOMEM; + + mbox_memcpy(sa->plcy, sa_plcy->plcy, sizeof(uint64_t) * 2 * 9); + sa->sa_index[0] = sa_plcy->sa_index[0]; + sa->sa_index[1] = sa_plcy->sa_index[1]; + sa->sa_cnt = sa_plcy->sa_cnt; + sa->mcs_id = mcs->idx; + sa->dir = sa_plcy->dir; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + +int +roc_mcs_sa_policy_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_sa_plcy_write_req *sa __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 900290b866..bd8a3095f9 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -139,6 +139,10 @@ INTERNAL { roc_mcs_dev_fini; roc_mcs_dev_get; roc_mcs_hw_info_get; + roc_mcs_rsrc_alloc; + roc_mcs_rsrc_free; + roc_mcs_sa_policy_read; + roc_mcs_sa_policy_write; roc_nix_bpf_alloc; roc_nix_bpf_config; roc_nix_bpf_connect; From patchwork Wed Jun 7 15:28:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128341 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4AC0342C4E; Wed, 7 Jun 2023 17:28:47 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2EA8742D2C; Wed, 7 Jun 2023 17:28:38 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id ADDC242D0C for ; Wed, 7 Jun 2023 17:28:36 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 357Dvh1t028122; Wed, 7 Jun 2023 08:28:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=kU3ZoIn+6XV/1AawsAyCDePJhUSAxakpofwquziF0u8=; b=du2mRM8tBg0YisriZm3Fr47HQ67k3Mzdudi1JP6fmZNsILN4enzd81+G+cI/c3pDYuOR xYptB6RTMKc9yGAL+gIrUV7A5F/4tuvfXwjFS6GM+OatVhSzvsgV2FElvLI2GSKoD5QI M4RbMc7B6oCnv3tX4KBRVaU7dxSKzJKFJsPUclIdF8NqBN7NAUE+WHTmBnJZrXewGBQM Cm7ApcCJcgho9uAVrjqKRIkp2kZER8zSs5FkxEqV9QIp8+y/vJfsTHvMG7Tsqam+8Dt+ QkrUxBqYPd1roEE9LN21htd2Z9ZmgjP1vNA9bQUIFEgp0g6bNJb8CVnnz1ZuqlgJZUIt XQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r2a7bv7ut-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 07 Jun 2023 08:28:35 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 7 Jun 2023 08:28:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:28:32 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id CC9E63F708C; Wed, 7 Jun 2023 08:28:30 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 03/15] common/cnxk: add MACsec SC configuration APIs Date: Wed, 7 Jun 2023 20:58:07 +0530 Message-ID: <20230607152819.226838-4-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: zxcHvUxtuPoLjWxxKkz3Zi3KjJGsF42f X-Proofpoint-GUID: zxcHvUxtuPoLjWxxKkz3Zi3KjJGsF42f X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added ROC APIs to configure MACsec secure channel(SC) and its mapping with SAs for both Rx and Tx. Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_mbox.h | 37 ++++++ drivers/common/cnxk/roc_mcs.h | 41 ++++++ drivers/common/cnxk/roc_mcs_sec_cfg.c | 171 ++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 7 ++ 4 files changed, 256 insertions(+) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index ab1173e805..40b761ee99 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -300,7 +300,10 @@ struct mbox_msghdr { M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ mcs_alloc_rsrc_rsp) \ M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ + M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, msg_rsp) \ M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, msg_rsp) \ + M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, msg_rsp) \ + M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, msg_rsp) \ M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ /* Messages initiated by AF (range 0xC00 - 0xDFF) */ @@ -726,6 +729,16 @@ struct mcs_free_rsrc_req { uint64_t __io rsvd; }; +/* RX SC_CAM mapping */ +struct mcs_rx_sc_cam_write_req { + struct mbox_msghdr hdr; + uint64_t __io sci; /* SCI */ + uint64_t __io secy_id; /* secy index mapped to SC */ + uint8_t __io sc_id; /* SC CAM entry index */ + uint8_t __io mcs_id; + uint64_t __io rsvd; +}; + struct mcs_sa_plcy_write_req { struct mbox_msghdr hdr; uint64_t __io plcy[2][9]; /* Support 2 SA policy */ @@ -736,6 +749,30 @@ struct mcs_sa_plcy_write_req { uint64_t __io rsvd; }; +struct mcs_tx_sc_sa_map { + struct mbox_msghdr hdr; + uint8_t __io sa_index0; + uint8_t __io sa_index1; + uint8_t __io rekey_ena; + uint8_t __io sa_index0_vld; + uint8_t __io sa_index1_vld; + uint8_t __io tx_sa_active; + uint64_t __io sectag_sci; + uint8_t __io sc_id; /* used as index for SA_MEM_MAP */ + uint8_t __io mcs_id; + uint64_t __io rsvd; +}; + +struct mcs_rx_sc_sa_map { + struct mbox_msghdr hdr; + uint8_t __io sa_index; + uint8_t __io sa_in_use; + uint8_t __io sc_id; + /* an range is 0-3, sc_id + an used as index SA_MEM_MAP */ + uint8_t __io an; + uint8_t __io mcs_id; + uint64_t __io rsvd; +}; struct mcs_hw_info { struct mbox_msghdr hdr; diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h index ea4c6ddc05..e947f93460 100644 --- a/drivers/common/cnxk/roc_mcs.h +++ b/drivers/common/cnxk/roc_mcs.h @@ -32,6 +32,12 @@ struct roc_mcs_free_rsrc_req { uint8_t all; /* Free all the cam resources */ }; +/* RX SC_CAM mapping */ +struct roc_mcs_rx_sc_cam_write_req { + uint64_t sci; /* SCI */ + uint64_t secy_id; /* secy index mapped to SC */ + uint8_t sc_id; /* SC CAM entry index */ +}; struct roc_mcs_sa_plcy_write_req { uint64_t plcy[2][9]; @@ -40,6 +46,24 @@ struct roc_mcs_sa_plcy_write_req { uint8_t dir; }; +struct roc_mcs_tx_sc_sa_map { + uint8_t sa_index0; + uint8_t sa_index1; + uint8_t rekey_ena; + uint8_t sa_index0_vld; + uint8_t sa_index1_vld; + uint8_t tx_sa_active; + uint64_t sectag_sci; + uint8_t sc_id; /* used as index for SA_MEM_MAP */ +}; + +struct roc_mcs_rx_sc_sa_map { + uint8_t sa_index; + uint8_t sa_in_use; + uint8_t sc_id; + uint8_t an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ +}; + struct roc_mcs_hw_info { uint8_t num_mcs_blks; /* Number of MCS blocks */ uint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */ @@ -81,4 +105,21 @@ __roc_api int roc_mcs_sa_policy_write(struct roc_mcs *mcs, struct roc_mcs_sa_plcy_write_req *sa_plcy); __roc_api int roc_mcs_sa_policy_read(struct roc_mcs *mcs, struct roc_mcs_sa_plcy_write_req *sa_plcy); +/* RX SC read, write and enable */ +__roc_api int roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); +__roc_api int roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); +__roc_api int roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); +/* RX SC-SA MAP read and write */ +__roc_api int roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs, + struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map); +__roc_api int roc_mcs_rx_sc_sa_map_read(struct roc_mcs *mcs, + struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map); +/* TX SC-SA MAP read and write */ +__roc_api int roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs, + struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map); +__roc_api int roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs, + struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map); #endif /* _ROC_MCS_H_ */ diff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c index 041be51b4b..9b87952112 100644 --- a/drivers/common/cnxk/roc_mcs_sec_cfg.c +++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c @@ -209,3 +209,174 @@ roc_mcs_sa_policy_read(struct roc_mcs *mcs __plt_unused, return -ENOTSUP; } + + +int +roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct mcs_rx_sc_cam_write_req *rx_sc; + struct msg_rsp *rsp; + int i, rc; + + MCS_SUPPORT_CHECK; + + if (rx_sc_cam == NULL) + return -EINVAL; + + rx_sc = mbox_alloc_msg_mcs_rx_sc_cam_write(mcs->mbox); + if (rx_sc == NULL) + return -ENOMEM; + + rx_sc->sci = rx_sc_cam->sci; + rx_sc->secy_id = rx_sc_cam->secy_id; + rx_sc->sc_id = rx_sc_cam->sc_id; + rx_sc->mcs_id = mcs->idx; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + for (i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].secy_bmap, rx_sc_cam->secy_id); + + if (set) { + plt_bitmap_set(priv->port_rsrc[i].sc_bmap, rx_sc_cam->sc_id); + break; + } + } + + return 0; +} + +int +roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} + +int +roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} + +int +roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct mcs_rx_sc_sa_map *sa_map; + struct msg_rsp *rsp; + uint16_t sc_id; + int i, rc; + + MCS_SUPPORT_CHECK; + + if (rx_sc_sa_map == NULL) + return -EINVAL; + + sc_id = rx_sc_sa_map->sc_id; + sa_map = mbox_alloc_msg_mcs_rx_sc_sa_map_write(mcs->mbox); + if (sa_map == NULL) + return -ENOMEM; + + sa_map->sa_index = rx_sc_sa_map->sa_index; + sa_map->sa_in_use = rx_sc_sa_map->sa_in_use; + sa_map->sc_id = rx_sc_sa_map->sc_id; + sa_map->an = rx_sc_sa_map->an; + sa_map->mcs_id = mcs->idx; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + for (i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].sc_bmap, sc_id); + + if (set) { + plt_bitmap_set(priv->port_rsrc[i].sa_bmap, rx_sc_sa_map->sa_index); + priv->port_rsrc[i].sc_conf[sc_id].rx.sa_idx = rx_sc_sa_map->sa_index; + priv->port_rsrc[i].sc_conf[sc_id].rx.an = rx_sc_sa_map->an; + break; + } + } + + return 0; +} + +int +roc_mcs_rx_sc_sa_map_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} + +int +roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct mcs_tx_sc_sa_map *sa_map; + struct msg_rsp *rsp; + uint16_t sc_id; + int i, rc; + + MCS_SUPPORT_CHECK; + + if (tx_sc_sa_map == NULL) + return -EINVAL; + + sa_map = mbox_alloc_msg_mcs_tx_sc_sa_map_write(mcs->mbox); + if (sa_map == NULL) + return -ENOMEM; + + sa_map->sa_index0 = tx_sc_sa_map->sa_index0; + sa_map->sa_index1 = tx_sc_sa_map->sa_index1; + sa_map->rekey_ena = tx_sc_sa_map->rekey_ena; + sa_map->sa_index0_vld = tx_sc_sa_map->sa_index0_vld; + sa_map->sa_index1_vld = tx_sc_sa_map->sa_index1_vld; + sa_map->tx_sa_active = tx_sc_sa_map->tx_sa_active; + sa_map->sectag_sci = tx_sc_sa_map->sectag_sci; + sa_map->sc_id = tx_sc_sa_map->sc_id; + sa_map->mcs_id = mcs->idx; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + sc_id = tx_sc_sa_map->sc_id; + for (i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].sc_bmap, sc_id + priv->sc_entries); + + if (set) { + uint32_t pos = priv->sa_entries + tx_sc_sa_map->sa_index0; + + plt_bitmap_set(priv->port_rsrc[i].sa_bmap, pos); + priv->port_rsrc[i].sc_conf[sc_id].tx.sa_idx0 = tx_sc_sa_map->sa_index0; + pos = priv->sa_entries + tx_sc_sa_map->sa_index1; + plt_bitmap_set(priv->port_rsrc[i].sa_bmap, pos); + priv->port_rsrc[i].sc_conf[sc_id].tx.sa_idx1 = tx_sc_sa_map->sa_index1; + priv->port_rsrc[i].sc_conf[sc_id].tx.sci = tx_sc_sa_map->sectag_sci; + priv->port_rsrc[i].sc_conf[sc_id].tx.rekey_enb = tx_sc_sa_map->rekey_ena; + break; + } + } + + return 0; +} + +int +roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index bd8a3095f9..dbfda62ad1 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -141,8 +141,15 @@ INTERNAL { roc_mcs_hw_info_get; roc_mcs_rsrc_alloc; roc_mcs_rsrc_free; + roc_mcs_rx_sc_cam_enable; + roc_mcs_rx_sc_cam_read; + roc_mcs_rx_sc_cam_write; + roc_mcs_rx_sc_sa_map_read; + roc_mcs_rx_sc_sa_map_write; roc_mcs_sa_policy_read; roc_mcs_sa_policy_write; + roc_mcs_tx_sc_sa_map_read; + roc_mcs_tx_sc_sa_map_write; roc_nix_bpf_alloc; roc_nix_bpf_config; roc_nix_bpf_connect; From patchwork Wed Jun 7 15:28:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128342 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 62AA142C4E; Wed, 7 Jun 2023 17:28:53 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6068742D10; Wed, 7 Jun 2023 17:28:41 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 46F9042D35 for ; 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Wed, 07 Jun 2023 08:28:38 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 7 Jun 2023 08:28:36 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:28:35 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id BCF2E3F7088; Wed, 7 Jun 2023 08:28:33 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 04/15] common/cnxk: add MACsec secy and flow configuration Date: Wed, 7 Jun 2023 20:58:08 +0530 Message-ID: <20230607152819.226838-5-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: OdVtKioy4gvMP3pKGPL-Q6pj4g-j4Yeh X-Proofpoint-GUID: OdVtKioy4gvMP3pKGPL-Q6pj4g-j4Yeh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added ROC APIs to configure MACsec secy policy and flow entries. Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_mbox.h | 38 +++++++++ drivers/common/cnxk/roc_mcs.h | 37 +++++++++ drivers/common/cnxk/roc_mcs_sec_cfg.c | 115 ++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 5 ++ 4 files changed, 195 insertions(+) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 40b761ee99..fcfcc90f6c 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -300,10 +300,14 @@ struct mbox_msghdr { M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ mcs_alloc_rsrc_rsp) \ M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ + M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ + msg_rsp) \ + M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, msg_rsp) \ M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, msg_rsp) \ M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, msg_rsp) \ M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, msg_rsp) \ M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, msg_rsp) \ + M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, msg_rsp) \ M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ /* Messages initiated by AF (range 0xC00 - 0xDFF) */ @@ -729,6 +733,31 @@ struct mcs_free_rsrc_req { uint64_t __io rsvd; }; +struct mcs_flowid_entry_write_req { + struct mbox_msghdr hdr; + uint64_t __io data[4]; + uint64_t __io mask[4]; + uint64_t __io sci; /* CNF10K-B for tx_secy_mem_map */ + uint8_t __io flow_id; + uint8_t __io secy_id; /* secyid for which flowid is mapped */ + /* sc_id is Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ + uint8_t __io sc_id; + uint8_t __io ena; /* Enable tcam entry */ + uint8_t __io ctr_pkt; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + +struct mcs_secy_plcy_write_req { + struct mbox_msghdr hdr; + uint64_t __io plcy; + uint8_t __io secy_id; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + /* RX SC_CAM mapping */ struct mcs_rx_sc_cam_write_req { struct mbox_msghdr hdr; @@ -774,6 +803,15 @@ struct mcs_rx_sc_sa_map { uint64_t __io rsvd; }; +struct mcs_flowid_ena_dis_entry { + struct mbox_msghdr hdr; + uint8_t __io flow_id; + uint8_t __io ena; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + struct mcs_hw_info { struct mbox_msghdr hdr; uint8_t __io num_mcs_blks; /* Number of MCS blocks */ diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h index e947f93460..38c2d5626a 100644 --- a/drivers/common/cnxk/roc_mcs.h +++ b/drivers/common/cnxk/roc_mcs.h @@ -32,6 +32,24 @@ struct roc_mcs_free_rsrc_req { uint8_t all; /* Free all the cam resources */ }; +struct roc_mcs_flowid_entry_write_req { + uint64_t data[4]; + uint64_t mask[4]; + uint64_t sci; /* 105N for tx_secy_mem_map */ + uint8_t flow_id; + uint8_t secy_id; /* secyid for which flowid is mapped */ + uint8_t sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ + uint8_t ena; /* Enable tcam entry */ + uint8_t ctr_pkt; + uint8_t dir; +}; + +struct roc_mcs_secy_plcy_write_req { + uint64_t plcy; + uint8_t secy_id; + uint8_t dir; +}; + /* RX SC_CAM mapping */ struct roc_mcs_rx_sc_cam_write_req { uint64_t sci; /* SCI */ @@ -64,6 +82,12 @@ struct roc_mcs_rx_sc_sa_map { uint8_t an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ }; +struct roc_mcs_flowid_ena_dis_entry { + uint8_t flow_id; + uint8_t ena; + uint8_t dir; +}; + struct roc_mcs_hw_info { uint8_t num_mcs_blks; /* Number of MCS blocks */ uint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */ @@ -112,6 +136,11 @@ __roc_api int roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); __roc_api int roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); +/* SECY policy read and write */ +__roc_api int roc_mcs_secy_policy_write(struct roc_mcs *mcs, + struct roc_mcs_secy_plcy_write_req *secy_plcy); +__roc_api int roc_mcs_secy_policy_read(struct roc_mcs *mcs, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); /* RX SC-SA MAP read and write */ __roc_api int roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map); @@ -122,4 +151,12 @@ __roc_api int roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map); __roc_api int roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs, struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map); +/* Flow entry read, write and enable */ +__roc_api int roc_mcs_flowid_entry_write(struct roc_mcs *mcs, + struct roc_mcs_flowid_entry_write_req *flowid_req); +__roc_api int roc_mcs_flowid_entry_read(struct roc_mcs *mcs, + struct roc_mcs_flowid_entry_write_req *flowid_rsp); +__roc_api int roc_mcs_flowid_entry_enable(struct roc_mcs *mcs, + struct roc_mcs_flowid_ena_dis_entry *entry); + #endif /* _ROC_MCS_H_ */ diff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c index 9b87952112..44b4919bbc 100644 --- a/drivers/common/cnxk/roc_mcs_sec_cfg.c +++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c @@ -267,6 +267,38 @@ roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs __plt_unused, return -ENOTSUP; } +int +roc_mcs_secy_policy_write(struct roc_mcs *mcs, struct roc_mcs_secy_plcy_write_req *secy_plcy) +{ + struct mcs_secy_plcy_write_req *secy; + struct msg_rsp *rsp; + + MCS_SUPPORT_CHECK; + + if (secy_plcy == NULL) + return -EINVAL; + + secy = mbox_alloc_msg_mcs_secy_plcy_write(mcs->mbox); + if (secy == NULL) + return -ENOMEM; + + secy->plcy = secy_plcy->plcy; + secy->secy_id = secy_plcy->secy_id; + secy->mcs_id = mcs->idx; + secy->dir = secy_plcy->dir; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + +int +roc_mcs_secy_policy_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} + int roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map) { @@ -380,3 +412,86 @@ roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs __plt_unused, return -ENOTSUP; } + +int +roc_mcs_flowid_entry_write(struct roc_mcs *mcs, struct roc_mcs_flowid_entry_write_req *flowid_req) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct mcs_flowid_entry_write_req *flow_req; + struct msg_rsp *rsp; + uint8_t port; + int rc; + + MCS_SUPPORT_CHECK; + + if (flowid_req == NULL) + return -EINVAL; + + flow_req = mbox_alloc_msg_mcs_flowid_entry_write(mcs->mbox); + if (flow_req == NULL) + return -ENOMEM; + + mbox_memcpy(flow_req->data, flowid_req->data, sizeof(uint64_t) * 4); + mbox_memcpy(flow_req->mask, flowid_req->mask, sizeof(uint64_t) * 4); + flow_req->sci = flowid_req->sci; + flow_req->flow_id = flowid_req->flow_id; + flow_req->secy_id = flowid_req->secy_id; + flow_req->sc_id = flowid_req->sc_id; + flow_req->ena = flowid_req->ena; + flow_req->ctr_pkt = flowid_req->ctr_pkt; + flow_req->mcs_id = mcs->idx; + flow_req->dir = flowid_req->dir; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + if (flow_req->mask[3] & (BIT_ULL(10) | BIT_ULL(11))) + return rc; + + port = (flow_req->data[3] >> 10) & 0x3; + + plt_bitmap_set(priv->port_rsrc[port].tcam_bmap, + flowid_req->flow_id + + ((flowid_req->dir == MCS_TX) ? priv->tcam_entries : 0)); + plt_bitmap_set(priv->port_rsrc[port].secy_bmap, + flowid_req->secy_id + + ((flowid_req->dir == MCS_TX) ? priv->secy_entries : 0)); + + if (flowid_req->dir == MCS_TX) + plt_bitmap_set(priv->port_rsrc[port].sc_bmap, priv->sc_entries + flowid_req->sc_id); + + return 0; +} + +int +roc_mcs_flowid_entry_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_flowid_entry_write_req *flowid_rsp __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} + +int +roc_mcs_flowid_entry_enable(struct roc_mcs *mcs, struct roc_mcs_flowid_ena_dis_entry *entry) +{ + struct mcs_flowid_ena_dis_entry *flow_entry; + struct msg_rsp *rsp; + + MCS_SUPPORT_CHECK; + + if (entry == NULL) + return -EINVAL; + + flow_entry = mbox_alloc_msg_mcs_flowid_ena_entry(mcs->mbox); + if (flow_entry == NULL) + return -ENOMEM; + + flow_entry->flow_id = entry->flow_id; + flow_entry->ena = entry->ena; + flow_entry->mcs_id = mcs->idx; + flow_entry->dir = entry->dir; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index dbfda62ad1..3d9da3b187 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -138,6 +138,9 @@ INTERNAL { roc_mcs_dev_init; roc_mcs_dev_fini; roc_mcs_dev_get; + roc_mcs_flowid_entry_enable; + roc_mcs_flowid_entry_read; + roc_mcs_flowid_entry_write; roc_mcs_hw_info_get; roc_mcs_rsrc_alloc; roc_mcs_rsrc_free; @@ -148,6 +151,8 @@ INTERNAL { roc_mcs_rx_sc_sa_map_write; roc_mcs_sa_policy_read; roc_mcs_sa_policy_write; + roc_mcs_secy_policy_read; + roc_mcs_secy_policy_write; roc_mcs_tx_sc_sa_map_read; roc_mcs_tx_sc_sa_map_write; roc_nix_bpf_alloc; From patchwork Wed Jun 7 15:28:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128343 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7AE9F42C4E; Wed, 7 Jun 2023 17:29:01 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DDC2E42D52; Wed, 7 Jun 2023 17:28:42 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0347542D3A for ; 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Wed, 07 Jun 2023 08:28:40 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 7 Jun 2023 08:28:39 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:28:38 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id AB18F3F708C; Wed, 7 Jun 2023 08:28:36 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 05/15] common/cnxk: add MACsec PN and LMAC mode configuration Date: Wed, 7 Jun 2023 20:58:09 +0530 Message-ID: <20230607152819.226838-6-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: sMV4SWHPC_cFwXnzu9ilOQK_lqe2l7zi X-Proofpoint-GUID: sMV4SWHPC_cFwXnzu9ilOQK_lqe2l7zi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added ROC APIs for setting packet number and LMAC related configurations. Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_mbox.h | 56 +++++++++++++++++++++ drivers/common/cnxk/roc_mcs.c | 71 +++++++++++++++++++++++++++ drivers/common/cnxk/roc_mcs.h | 48 ++++++++++++++++++ drivers/common/cnxk/roc_mcs_sec_cfg.c | 31 ++++++++++++ drivers/common/cnxk/version.map | 5 ++ 5 files changed, 211 insertions(+) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index fcfcc90f6c..62c5c3a3ce 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -308,7 +308,11 @@ struct mbox_msghdr { M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, msg_rsp) \ M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, msg_rsp) \ M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, msg_rsp) \ + M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, msg_rsp) \ + M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, msg_rsp) \ M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ + M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ + M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, msg_rsp) \ /* Messages initiated by AF (range 0xC00 - 0xDFF) */ #define MBOX_UP_CGX_MESSAGES \ @@ -812,6 +816,34 @@ struct mcs_flowid_ena_dis_entry { uint64_t __io rsvd; }; +struct mcs_pn_table_write_req { + struct mbox_msghdr hdr; + uint64_t __io next_pn; + uint8_t __io pn_id; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + +struct mcs_cam_entry_read_req { + struct mbox_msghdr hdr; + uint8_t __io rsrc_type; /* TCAM/SECY/SC/SA/PN */ + uint8_t __io rsrc_id; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + +struct mcs_cam_entry_read_rsp { + struct mbox_msghdr hdr; + uint64_t __io reg_val[10]; + uint8_t __io rsrc_type; + uint8_t __io rsrc_id; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + struct mcs_hw_info { struct mbox_msghdr hdr; uint8_t __io num_mcs_blks; /* Number of MCS blocks */ @@ -822,6 +854,30 @@ struct mcs_hw_info { uint64_t __io rsvd[16]; }; +struct mcs_set_active_lmac { + struct mbox_msghdr hdr; + uint32_t __io lmac_bmap; /* bitmap of active lmac per mcs block */ + uint8_t __io mcs_id; + uint16_t __io channel_base; /* MCS channel base */ + uint64_t __io rsvd; +}; + +struct mcs_set_lmac_mode { + struct mbox_msghdr hdr; + uint8_t __io mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */ + uint8_t __io lmac_id; + uint8_t __io mcs_id; + uint64_t __io rsvd; +}; + +struct mcs_set_pn_threshold { + struct mbox_msghdr hdr; + uint64_t __io threshold; + uint8_t __io xpn; /* '1' for setting xpn threshold */ + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; /* NPA mbox message formats */ diff --git a/drivers/common/cnxk/roc_mcs.c b/drivers/common/cnxk/roc_mcs.c index 20433eae83..38f1e9b2f7 100644 --- a/drivers/common/cnxk/roc_mcs.c +++ b/drivers/common/cnxk/roc_mcs.c @@ -38,6 +38,77 @@ roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info) return rc; } +int +roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_active_lmac *lmac) +{ + struct mcs_set_active_lmac *req; + struct msg_rsp *rsp; + + /* Only needed for 105N */ + if (!roc_model_is_cnf10kb()) + return 0; + + if (lmac == NULL) + return -EINVAL; + + MCS_SUPPORT_CHECK; + + req = mbox_alloc_msg_mcs_set_active_lmac(mcs->mbox); + if (req == NULL) + return -ENOMEM; + + req->lmac_bmap = lmac->lmac_bmap; + req->channel_base = lmac->channel_base; + req->mcs_id = mcs->idx; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + +int +roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port) +{ + struct mcs_set_lmac_mode *req; + struct msg_rsp *rsp; + + if (port == NULL) + return -EINVAL; + + MCS_SUPPORT_CHECK; + + req = mbox_alloc_msg_mcs_set_lmac_mode(mcs->mbox); + if (req == NULL) + return -ENOMEM; + + req->lmac_id = port->lmac_id; + req->mcs_id = mcs->idx; + req->mode = port->mode; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + +int +roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *pn) +{ + struct mcs_set_pn_threshold *req; + struct msg_rsp *rsp; + + if (pn == NULL) + return -EINVAL; + + MCS_SUPPORT_CHECK; + + req = mbox_alloc_msg_mcs_set_pn_threshold(mcs->mbox); + if (req == NULL) + return -ENOMEM; + + req->threshold = pn->threshold; + req->mcs_id = mcs->idx; + req->dir = pn->dir; + req->xpn = pn->xpn; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + static int mcs_alloc_bmap(uint16_t entries, void **mem, struct plt_bitmap **bmap) { diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h index 38c2d5626a..bedae3bf42 100644 --- a/drivers/common/cnxk/roc_mcs.h +++ b/drivers/common/cnxk/roc_mcs.h @@ -88,6 +88,25 @@ struct roc_mcs_flowid_ena_dis_entry { uint8_t dir; }; +struct roc_mcs_pn_table_write_req { + uint64_t next_pn; + uint8_t pn_id; + uint8_t dir; +}; + +struct roc_mcs_cam_entry_read_req { + uint8_t rsrc_type; /* TCAM/SECY/SC/SA/PN */ + uint8_t rsrc_id; + uint8_t dir; +}; + +struct roc_mcs_cam_entry_read_rsp { + uint64_t reg_val[10]; + uint8_t rsrc_type; + uint8_t rsrc_id; + uint8_t dir; +}; + struct roc_mcs_hw_info { uint8_t num_mcs_blks; /* Number of MCS blocks */ uint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */ @@ -97,6 +116,24 @@ struct roc_mcs_hw_info { uint64_t rsvd[16]; }; +struct roc_mcs_set_lmac_mode { + uint8_t mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */ + uint8_t lmac_id; + uint64_t rsvd; +}; + +struct roc_mcs_set_active_lmac { + uint32_t lmac_bmap; /* bitmap of active lmac per mcs block */ + uint16_t channel_base; /* MCS channel base */ + uint64_t rsvd; +}; + +struct roc_mcs_set_pn_threshold { + uint64_t threshold; + uint8_t xpn; /* '1' for setting xpn threshold */ + uint8_t dir; + uint64_t rsvd; +}; struct roc_mcs { TAILQ_ENTRY(roc_mcs) next; @@ -119,6 +156,12 @@ __roc_api void roc_mcs_dev_fini(struct roc_mcs *mcs); __roc_api struct roc_mcs *roc_mcs_dev_get(uint8_t mcs_idx); /* HW info get */ __roc_api int roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info); +/* Active lmac bmap set */ +__roc_api int roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_active_lmac *lmac); +/* Port bypass mode set */ +__roc_api int roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port); +/* (X)PN threshold set */ +__roc_api int roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *pn); /* Resource allocation and free */ __roc_api int roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req, @@ -129,6 +172,11 @@ __roc_api int roc_mcs_sa_policy_write(struct roc_mcs *mcs, struct roc_mcs_sa_plcy_write_req *sa_plcy); __roc_api int roc_mcs_sa_policy_read(struct roc_mcs *mcs, struct roc_mcs_sa_plcy_write_req *sa_plcy); +/* PN Table read and write */ +__roc_api int roc_mcs_pn_table_write(struct roc_mcs *mcs, + struct roc_mcs_pn_table_write_req *pn_table); +__roc_api int roc_mcs_pn_table_read(struct roc_mcs *mcs, + struct roc_mcs_pn_table_write_req *pn_table); /* RX SC read, write and enable */ __roc_api int roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); diff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c index 44b4919bbc..7b3a4c91e8 100644 --- a/drivers/common/cnxk/roc_mcs_sec_cfg.c +++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c @@ -210,6 +210,37 @@ roc_mcs_sa_policy_read(struct roc_mcs *mcs __plt_unused, return -ENOTSUP; } +int +roc_mcs_pn_table_write(struct roc_mcs *mcs, struct roc_mcs_pn_table_write_req *pn_table) +{ + struct mcs_pn_table_write_req *pn; + struct msg_rsp *rsp; + + MCS_SUPPORT_CHECK; + + if (pn_table == NULL) + return -EINVAL; + + pn = mbox_alloc_msg_mcs_pn_table_write(mcs->mbox); + if (pn == NULL) + return -ENOMEM; + + pn->next_pn = pn_table->next_pn; + pn->pn_id = pn_table->pn_id; + pn->mcs_id = mcs->idx; + pn->dir = pn_table->dir; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + +int +roc_mcs_pn_table_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_pn_table_write_req *sa __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} int roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam) diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 3d9da3b187..0591747961 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -135,6 +135,7 @@ INTERNAL { roc_se_auth_key_set; roc_se_ciph_key_set; roc_se_ctx_init; + roc_mcs_active_lmac_set; roc_mcs_dev_init; roc_mcs_dev_fini; roc_mcs_dev_get; @@ -142,6 +143,10 @@ INTERNAL { roc_mcs_flowid_entry_read; roc_mcs_flowid_entry_write; roc_mcs_hw_info_get; + roc_mcs_lmac_mode_set; + roc_mcs_pn_table_write; + roc_mcs_pn_table_read; + roc_mcs_pn_threshold_set; roc_mcs_rsrc_alloc; roc_mcs_rsrc_free; roc_mcs_rx_sc_cam_enable; From patchwork Wed Jun 7 15:28:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128344 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4266442C4E; Wed, 7 Jun 2023 17:29:08 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0779742D3D; Wed, 7 Jun 2023 17:28:46 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A577F42BFE for ; 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Wed, 07 Jun 2023 08:28:43 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 7 Jun 2023 08:28:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:28:42 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 9C4EF3F7084; Wed, 7 Jun 2023 08:28:39 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 06/15] common/cnxk: add MACsec stats Date: Wed, 7 Jun 2023 20:58:10 +0530 Message-ID: <20230607152819.226838-7-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 7Rp92NziSkFDckBqkY5TCxgROUoVGqKD X-Proofpoint-GUID: 7Rp92NziSkFDckBqkY5TCxgROUoVGqKD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added ROC APIs for MACsec stats for SC/SECY/FLOW/PORT Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_mbox.h | 93 ++++++++++++++ drivers/common/cnxk/roc_mcs.h | 85 ++++++++++++ drivers/common/cnxk/roc_mcs_stats.c | 193 ++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 5 + 5 files changed, 377 insertions(+) create mode 100644 drivers/common/cnxk/roc_mcs_stats.c diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 589baf74fe..79e10bac74 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -28,6 +28,7 @@ sources = files( 'roc_mbox.c', 'roc_mcs.c', 'roc_mcs_sec_cfg.c', + 'roc_mcs_stats.c', 'roc_ml.c', 'roc_model.c', 'roc_nix.c', diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 62c5c3a3ce..3f3a6aadc8 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -311,6 +311,11 @@ struct mbox_msghdr { M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, msg_rsp) \ M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, msg_rsp) \ M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ + M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, mcs_flowid_stats) \ + M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, mcs_secy_stats) \ + M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ + M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, mcs_port_stats) \ + M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, msg_rsp) \ @@ -879,6 +884,94 @@ struct mcs_set_pn_threshold { uint64_t __io rsvd; }; +struct mcs_stats_req { + struct mbox_msghdr hdr; + uint8_t __io id; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + +struct mcs_flowid_stats { + struct mbox_msghdr hdr; + uint64_t __io tcam_hit_cnt; + uint64_t __io rsvd; +}; + +struct mcs_secy_stats { + struct mbox_msghdr hdr; + uint64_t __io ctl_pkt_bcast_cnt; + uint64_t __io ctl_pkt_mcast_cnt; + uint64_t __io ctl_pkt_ucast_cnt; + uint64_t __io ctl_octet_cnt; + uint64_t __io unctl_pkt_bcast_cnt; + uint64_t __io unctl_pkt_mcast_cnt; + uint64_t __io unctl_pkt_ucast_cnt; + uint64_t __io unctl_octet_cnt; + /* Valid only for RX */ + uint64_t __io octet_decrypted_cnt; + uint64_t __io octet_validated_cnt; + uint64_t __io pkt_port_disabled_cnt; + uint64_t __io pkt_badtag_cnt; + uint64_t __io pkt_nosa_cnt; + uint64_t __io pkt_nosaerror_cnt; + uint64_t __io pkt_tagged_ctl_cnt; + uint64_t __io pkt_untaged_cnt; + uint64_t __io pkt_ctl_cnt; /* CN10K-B */ + uint64_t __io pkt_notag_cnt; /* CNF10K-B */ + /* Valid only for TX */ + uint64_t __io octet_encrypted_cnt; + uint64_t __io octet_protected_cnt; + uint64_t __io pkt_noactivesa_cnt; + uint64_t __io pkt_toolong_cnt; + uint64_t __io pkt_untagged_cnt; + uint64_t __io rsvd[4]; +}; + +struct mcs_port_stats { + struct mbox_msghdr hdr; + uint64_t __io tcam_miss_cnt; + uint64_t __io parser_err_cnt; + uint64_t __io preempt_err_cnt; /* CNF10K-B */ + uint64_t __io sectag_insert_err_cnt; + uint64_t __io rsvd[4]; +}; + +struct mcs_sc_stats { + struct mbox_msghdr hdr; + /* RX */ + uint64_t __io hit_cnt; + uint64_t __io pkt_invalid_cnt; + uint64_t __io pkt_late_cnt; + uint64_t __io pkt_notvalid_cnt; + uint64_t __io pkt_unchecked_cnt; + uint64_t __io pkt_delay_cnt; /* CNF10K-B */ + uint64_t __io pkt_ok_cnt; /* CNF10K-B */ + uint64_t __io octet_decrypt_cnt; /* CN10K-B */ + uint64_t __io octet_validate_cnt; /* CN10K-B */ + /* TX */ + uint64_t __io pkt_encrypt_cnt; + uint64_t __io pkt_protected_cnt; + uint64_t __io octet_encrypt_cnt; /* CN10K-B */ + uint64_t __io octet_protected_cnt; /* CN10K-B */ + uint64_t __io rsvd[4]; +}; + +struct mcs_clear_stats { + struct mbox_msghdr hdr; +#define MCS_FLOWID_STATS 0 +#define MCS_SECY_STATS 1 +#define MCS_SC_STATS 2 +#define MCS_SA_STATS 3 +#define MCS_PORT_STATS 4 + uint8_t __io type; /* FLOWID, SECY, SC, SA, PORT */ + /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ + uint8_t __io id; + uint8_t __io mcs_id; + uint8_t __io dir; + uint8_t __io all; /* All resources stats mapped to PF are cleared */ +}; + /* NPA mbox message formats */ /* NPA mailbox error codes diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h index bedae3bf42..3fbeee13fa 100644 --- a/drivers/common/cnxk/roc_mcs.h +++ b/drivers/common/cnxk/roc_mcs.h @@ -135,6 +135,76 @@ struct roc_mcs_set_pn_threshold { uint64_t rsvd; }; +struct roc_mcs_stats_req { + uint8_t id; + uint8_t dir; +}; + +struct roc_mcs_flowid_stats { + uint64_t tcam_hit_cnt; +}; + +struct roc_mcs_secy_stats { + uint64_t ctl_pkt_bcast_cnt; + uint64_t ctl_pkt_mcast_cnt; + uint64_t ctl_pkt_ucast_cnt; + uint64_t ctl_octet_cnt; + uint64_t unctl_pkt_bcast_cnt; + uint64_t unctl_pkt_mcast_cnt; + uint64_t unctl_pkt_ucast_cnt; + uint64_t unctl_octet_cnt; + /* Valid only for RX */ + uint64_t octet_decrypted_cnt; + uint64_t octet_validated_cnt; + uint64_t pkt_port_disabled_cnt; + uint64_t pkt_badtag_cnt; + uint64_t pkt_nosa_cnt; + uint64_t pkt_nosaerror_cnt; + uint64_t pkt_tagged_ctl_cnt; + uint64_t pkt_untaged_cnt; + uint64_t pkt_ctl_cnt; /* CN10K-B */ + uint64_t pkt_notag_cnt; /* CNF10K-B */ + /* Valid only for TX */ + uint64_t octet_encrypted_cnt; + uint64_t octet_protected_cnt; + uint64_t pkt_noactivesa_cnt; + uint64_t pkt_toolong_cnt; + uint64_t pkt_untagged_cnt; +}; + +struct roc_mcs_sc_stats { + /* RX */ + uint64_t hit_cnt; + uint64_t pkt_invalid_cnt; + uint64_t pkt_late_cnt; + uint64_t pkt_notvalid_cnt; + uint64_t pkt_unchecked_cnt; + uint64_t pkt_delay_cnt; /* CNF10K-B */ + uint64_t pkt_ok_cnt; /* CNF10K-B */ + uint64_t octet_decrypt_cnt; /* CN10K-B */ + uint64_t octet_validate_cnt; /* CN10K-B */ + /* TX */ + uint64_t pkt_encrypt_cnt; + uint64_t pkt_protected_cnt; + uint64_t octet_encrypt_cnt; /* CN10K-B */ + uint64_t octet_protected_cnt; /* CN10K-B */ +}; + +struct roc_mcs_port_stats { + uint64_t tcam_miss_cnt; + uint64_t parser_err_cnt; + uint64_t preempt_err_cnt; /* CNF10K-B */ + uint64_t sectag_insert_err_cnt; +}; + +struct roc_mcs_clear_stats { + uint8_t type; /* FLOWID, SECY, SC, SA, PORT */ + /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ + uint8_t id; + uint8_t dir; + uint8_t all; /* All resources stats mapped to PF are cleared */ +}; + struct roc_mcs { TAILQ_ENTRY(roc_mcs) next; struct plt_pci_device *pci_dev; @@ -207,4 +277,19 @@ __roc_api int roc_mcs_flowid_entry_read(struct roc_mcs *mcs, __roc_api int roc_mcs_flowid_entry_enable(struct roc_mcs *mcs, struct roc_mcs_flowid_ena_dis_entry *entry); +/* Flow id stats get */ +__roc_api int roc_mcs_flowid_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req, + struct roc_mcs_flowid_stats *stats); +/* Secy stats get */ +__roc_api int roc_mcs_secy_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req, + struct roc_mcs_secy_stats *stats); +/* SC stats get */ +__roc_api int roc_mcs_sc_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req, + struct roc_mcs_sc_stats *stats); +/* Port stats get */ +__roc_api int roc_mcs_port_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req, + struct roc_mcs_port_stats *stats); +/* Clear stats */ +__roc_api int roc_mcs_stats_clear(struct roc_mcs *mcs, struct roc_mcs_clear_stats *mcs_req); + #endif /* _ROC_MCS_H_ */ diff --git a/drivers/common/cnxk/roc_mcs_stats.c b/drivers/common/cnxk/roc_mcs_stats.c new file mode 100644 index 0000000000..24ac8a31cd --- /dev/null +++ b/drivers/common/cnxk/roc_mcs_stats.c @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2022 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" + +int +roc_mcs_flowid_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req, + struct roc_mcs_flowid_stats *stats) +{ + struct mcs_flowid_stats *rsp; + struct mcs_stats_req *req; + int rc; + + MCS_SUPPORT_CHECK; + + req = mbox_alloc_msg_mcs_get_flowid_stats(mcs->mbox); + if (req == NULL) + return -ENOSPC; + + req->id = mcs_req->id; + req->mcs_id = mcs->idx; + req->dir = mcs_req->dir; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + stats->tcam_hit_cnt = rsp->tcam_hit_cnt; + + return rc; +} + +int +roc_mcs_secy_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req, + struct roc_mcs_secy_stats *stats) +{ + struct mcs_secy_stats *rsp; + struct mcs_stats_req *req; + int rc; + + MCS_SUPPORT_CHECK; + + req = mbox_alloc_msg_mcs_get_secy_stats(mcs->mbox); + if (req == NULL) + return -ENOSPC; + + req->id = mcs_req->id; + req->mcs_id = mcs->idx; + req->dir = mcs_req->dir; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + stats->ctl_pkt_bcast_cnt = rsp->ctl_pkt_bcast_cnt; + stats->ctl_pkt_mcast_cnt = rsp->ctl_pkt_mcast_cnt; + stats->ctl_pkt_ucast_cnt = rsp->ctl_pkt_ucast_cnt; + stats->ctl_octet_cnt = rsp->ctl_octet_cnt; + stats->unctl_pkt_bcast_cnt = rsp->unctl_pkt_bcast_cnt; + stats->unctl_pkt_mcast_cnt = rsp->unctl_pkt_mcast_cnt; + stats->unctl_pkt_ucast_cnt = rsp->unctl_pkt_ucast_cnt; + stats->unctl_octet_cnt = rsp->unctl_octet_cnt; + + if (mcs_req->dir == MCS_RX) { + stats->octet_decrypted_cnt = rsp->octet_decrypted_cnt; + stats->octet_validated_cnt = rsp->octet_validated_cnt; + stats->pkt_port_disabled_cnt = rsp->pkt_port_disabled_cnt; + stats->pkt_badtag_cnt = rsp->pkt_badtag_cnt; + stats->pkt_nosa_cnt = rsp->pkt_nosa_cnt; + stats->pkt_nosaerror_cnt = rsp->pkt_nosaerror_cnt; + stats->pkt_tagged_ctl_cnt = rsp->pkt_tagged_ctl_cnt; + stats->pkt_untaged_cnt = rsp->pkt_untaged_cnt; + if (roc_model_is_cn10kb_a0()) + /* CN10K-B */ + stats->pkt_ctl_cnt = rsp->pkt_ctl_cnt; + else + /* CNF10K-B */ + stats->pkt_notag_cnt = rsp->pkt_notag_cnt; + } else { + stats->octet_encrypted_cnt = rsp->octet_encrypted_cnt; + stats->octet_protected_cnt = rsp->octet_protected_cnt; + stats->pkt_noactivesa_cnt = rsp->pkt_noactivesa_cnt; + stats->pkt_toolong_cnt = rsp->pkt_toolong_cnt; + stats->pkt_untagged_cnt = rsp->pkt_untagged_cnt; + } + + return rc; +} + +int +roc_mcs_sc_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req, + struct roc_mcs_sc_stats *stats) +{ + struct mcs_stats_req *req; + struct mcs_sc_stats *rsp; + int rc; + + MCS_SUPPORT_CHECK; + + req = mbox_alloc_msg_mcs_get_sc_stats(mcs->mbox); + if (req == NULL) + return -ENOSPC; + + req->id = mcs_req->id; + req->mcs_id = mcs->idx; + req->dir = mcs_req->dir; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + if (mcs_req->dir == MCS_RX) { + stats->hit_cnt = rsp->hit_cnt; + stats->pkt_invalid_cnt = rsp->pkt_invalid_cnt; + stats->pkt_late_cnt = rsp->pkt_late_cnt; + stats->pkt_notvalid_cnt = rsp->pkt_notvalid_cnt; + stats->pkt_unchecked_cnt = rsp->pkt_unchecked_cnt; + if (roc_model_is_cn10kb_a0()) { + stats->octet_decrypt_cnt = rsp->octet_decrypt_cnt; + stats->octet_validate_cnt = rsp->octet_validate_cnt; + } else { + stats->pkt_delay_cnt = rsp->pkt_delay_cnt; + stats->pkt_ok_cnt = rsp->pkt_ok_cnt; + } + } else { + stats->pkt_encrypt_cnt = rsp->pkt_encrypt_cnt; + stats->pkt_protected_cnt = rsp->pkt_protected_cnt; + if (roc_model_is_cn10kb_a0()) { + stats->octet_encrypt_cnt = rsp->octet_encrypt_cnt; + stats->octet_protected_cnt = rsp->octet_protected_cnt; + } + } + + return rc; +} + +int +roc_mcs_port_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req, + struct roc_mcs_port_stats *stats) +{ + struct mcs_port_stats *rsp; + struct mcs_stats_req *req; + int rc; + + MCS_SUPPORT_CHECK; + + req = mbox_alloc_msg_mcs_get_port_stats(mcs->mbox); + if (req == NULL) + return -ENOSPC; + + req->id = mcs_req->id; + req->mcs_id = mcs->idx; + req->dir = mcs_req->dir; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + stats->tcam_miss_cnt = rsp->tcam_miss_cnt; + stats->parser_err_cnt = rsp->parser_err_cnt; + if (roc_model_is_cnf10kb()) + stats->preempt_err_cnt = rsp->preempt_err_cnt; + + stats->sectag_insert_err_cnt = rsp->sectag_insert_err_cnt; + + return rc; +} + +int +roc_mcs_stats_clear(struct roc_mcs *mcs, struct roc_mcs_clear_stats *mcs_req) +{ + struct mcs_clear_stats *req; + struct msg_rsp *rsp; + + MCS_SUPPORT_CHECK; + + if (!roc_model_is_cn10kb_a0() && mcs_req->type == MCS_SA_STATS) + return MCS_ERR_HW_NOTSUP; + + req = mbox_alloc_msg_mcs_clear_stats(mcs->mbox); + if (req == NULL) + return -ENOSPC; + + req->type = mcs_req->type; + req->id = mcs_req->id; + req->mcs_id = mcs->idx; + req->dir = mcs_req->dir; + req->all = mcs_req->all; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 0591747961..d8890e3538 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -142,11 +142,13 @@ INTERNAL { roc_mcs_flowid_entry_enable; roc_mcs_flowid_entry_read; roc_mcs_flowid_entry_write; + roc_mcs_flowid_stats_get; roc_mcs_hw_info_get; roc_mcs_lmac_mode_set; roc_mcs_pn_table_write; roc_mcs_pn_table_read; roc_mcs_pn_threshold_set; + roc_mcs_port_stats_get; roc_mcs_rsrc_alloc; roc_mcs_rsrc_free; roc_mcs_rx_sc_cam_enable; @@ -156,8 +158,11 @@ INTERNAL { roc_mcs_rx_sc_sa_map_write; roc_mcs_sa_policy_read; roc_mcs_sa_policy_write; + roc_mcs_sc_stats_get; roc_mcs_secy_policy_read; roc_mcs_secy_policy_write; + roc_mcs_secy_stats_get; + roc_mcs_stats_clear; roc_mcs_tx_sc_sa_map_read; roc_mcs_tx_sc_sa_map_write; roc_nix_bpf_alloc; From patchwork Wed Jun 7 15:28:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128345 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9030342C4E; Wed, 7 Jun 2023 17:29:14 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 320E742D29; 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Wed, 07 Jun 2023 08:28:46 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 7 Jun 2023 08:28:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:28:44 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 8A4F03F7088; Wed, 7 Jun 2023 08:28:42 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 07/15] common/cnxk: add MACsec interrupt APIs Date: Wed, 7 Jun 2023 20:58:11 +0530 Message-ID: <20230607152819.226838-8-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: WTb5LxZkvlDn1Zl5wxjPVAfeEgrwC1ID X-Proofpoint-GUID: WTb5LxZkvlDn1Zl5wxjPVAfeEgrwC1ID X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added ROC APIs to support various MACsec interrupts. Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_dev.c | 86 +++++++++++++++++ drivers/common/cnxk/roc_mbox.h | 37 +++++++- drivers/common/cnxk/roc_mcs.c | 117 +++++++++++++++++++++++ drivers/common/cnxk/roc_mcs.h | 144 +++++++++++++++++++++++++++++ drivers/common/cnxk/roc_mcs_priv.h | 8 ++ drivers/common/cnxk/version.map | 3 + 6 files changed, 394 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c index d87b00e7e8..875bfc59e4 100644 --- a/drivers/common/cnxk/roc_dev.c +++ b/drivers/common/cnxk/roc_dev.c @@ -514,6 +514,91 @@ pf_vf_mbox_send_up_msg(struct dev *dev, void *rec_msg) } } +static int +mbox_up_handler_mcs_intr_notify(struct dev *dev, struct mcs_intr_info *info, struct msg_rsp *rsp) +{ + struct roc_mcs_event_desc desc = {0}; + struct roc_mcs *mcs; + + plt_base_dbg("pf:%d/vf:%d msg id 0x%x (%s) from: pf:%d/vf:%d", dev_get_pf(dev->pf_func), + dev_get_vf(dev->pf_func), info->hdr.id, mbox_id2name(info->hdr.id), + dev_get_pf(info->hdr.pcifunc), dev_get_vf(info->hdr.pcifunc)); + + mcs = roc_idev_mcs_get(info->mcs_id); + if (!mcs) + goto exit; + + if (info->intr_mask) { + switch (info->intr_mask) { + case MCS_CPM_RX_SECTAG_V_EQ1_INT: + desc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR; + desc.subtype = ROC_MCS_EVENT_RX_SECTAG_V_EQ1; + break; + case MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT: + desc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR; + desc.subtype = ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1; + break; + case MCS_CPM_RX_SECTAG_SL_GTE48_INT: + desc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR; + desc.subtype = ROC_MCS_EVENT_RX_SECTAG_SL_GTE48; + break; + case MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT: + desc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR; + desc.subtype = ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1; + break; + case MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT: + desc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR; + desc.subtype = ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1; + break; + case MCS_CPM_RX_PACKET_XPN_EQ0_INT: + desc.type = ROC_MCS_EVENT_RX_SA_PN_HARD_EXP; + desc.metadata.sa_idx = info->sa_id; + break; + case MCS_CPM_RX_PN_THRESH_REACHED_INT: + desc.type = ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP; + desc.metadata.sa_idx = info->sa_id; + break; + case MCS_CPM_TX_PACKET_XPN_EQ0_INT: + desc.type = ROC_MCS_EVENT_TX_SA_PN_HARD_EXP; + desc.metadata.sa_idx = info->sa_id; + break; + case MCS_CPM_TX_PN_THRESH_REACHED_INT: + desc.type = ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP; + desc.metadata.sa_idx = info->sa_id; + break; + case MCS_CPM_TX_SA_NOT_VALID_INT: + desc.type = ROC_MCS_EVENT_SA_NOT_VALID; + break; + case MCS_BBE_RX_DFIFO_OVERFLOW_INT: + case MCS_BBE_TX_DFIFO_OVERFLOW_INT: + desc.type = ROC_MCS_EVENT_FIFO_OVERFLOW; + desc.subtype = ROC_MCS_EVENT_DATA_FIFO_OVERFLOW; + desc.metadata.lmac_id = info->lmac_id; + break; + case MCS_BBE_RX_PLFIFO_OVERFLOW_INT: + case MCS_BBE_TX_PLFIFO_OVERFLOW_INT: + desc.type = ROC_MCS_EVENT_FIFO_OVERFLOW; + desc.subtype = ROC_MCS_EVENT_POLICY_FIFO_OVERFLOW; + desc.metadata.lmac_id = info->lmac_id; + break; + case MCS_PAB_RX_CHAN_OVERFLOW_INT: + case MCS_PAB_TX_CHAN_OVERFLOW_INT: + desc.type = ROC_MCS_EVENT_FIFO_OVERFLOW; + desc.subtype = ROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW; + desc.metadata.lmac_id = info->lmac_id; + break; + default: + goto exit; + } + + mcs_event_cb_process(mcs, &desc); + } + +exit: + rsp->hdr.rc = 0; + return 0; +} + static int mbox_up_handler_cgx_link_event(struct dev *dev, struct cgx_link_info_msg *msg, struct msg_rsp *rsp) @@ -602,6 +687,7 @@ mbox_process_msgs_up(struct dev *dev, struct mbox_msghdr *req) return err; \ } MBOX_UP_CGX_MESSAGES + MBOX_UP_MCS_MESSAGES #undef M } diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 3f3a6aadc8..d964ba9f9d 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -316,6 +316,7 @@ struct mbox_msghdr { M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, mcs_port_stats) \ M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ + M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, msg_rsp) \ @@ -324,9 +325,11 @@ struct mbox_msghdr { M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) \ M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, msg_rsp) +#define MBOX_UP_MCS_MESSAGES M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) + enum { #define M(_name, _id, _1, _2, _3) MBOX_MSG_##_name = _id, - MBOX_MESSAGES MBOX_UP_CGX_MESSAGES + MBOX_MESSAGES MBOX_UP_CGX_MESSAGES MBOX_UP_MCS_MESSAGES #undef M }; @@ -867,6 +870,38 @@ struct mcs_set_active_lmac { uint64_t __io rsvd; }; +#define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) +#define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) +#define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) +#define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) +#define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) +#define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) +#define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) +#define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) +#define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) +#define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) +#define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) +#define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) +#define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) +#define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) +#define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) +#define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) + +struct mcs_intr_cfg { + struct mbox_msghdr hdr; + uint64_t __io intr_mask; /* Interrupt enable mask */ + uint8_t __io mcs_id; +}; + +struct mcs_intr_info { + struct mbox_msghdr hdr; + uint64_t __io intr_mask; + int __io sa_id; + uint8_t __io mcs_id; + uint8_t __io lmac_id; + uint64_t __io rsvd; +}; + struct mcs_set_lmac_mode { struct mbox_msghdr hdr; uint8_t __io mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */ diff --git a/drivers/common/cnxk/roc_mcs.c b/drivers/common/cnxk/roc_mcs.c index 38f1e9b2f7..e9090da575 100644 --- a/drivers/common/cnxk/roc_mcs.c +++ b/drivers/common/cnxk/roc_mcs.c @@ -5,6 +5,18 @@ #include "roc_api.h" #include "roc_priv.h" +struct mcs_event_cb { + TAILQ_ENTRY(mcs_event_cb) next; + enum roc_mcs_event_type event; + roc_mcs_dev_cb_fn cb_fn; + void *cb_arg; + void *ret_param; + uint32_t active; +}; +TAILQ_HEAD(mcs_event_cb_list, mcs_event_cb); + +PLT_STATIC_ASSERT(ROC_MCS_MEM_SZ >= (sizeof(struct mcs_priv) + sizeof(struct mcs_event_cb_list))); + int roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info) { @@ -109,6 +121,107 @@ roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *p return mbox_process_msg(mcs->mbox, (void *)&rsp); } +int +roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config) +{ + struct mcs_intr_cfg *req; + struct msg_rsp *rsp; + + if (config == NULL) + return -EINVAL; + + MCS_SUPPORT_CHECK; + + req = mbox_alloc_msg_mcs_intr_cfg(mcs->mbox); + if (req == NULL) + return -ENOMEM; + + req->intr_mask = config->intr_mask; + req->mcs_id = mcs->idx; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + +int +roc_mcs_event_cb_register(struct roc_mcs *mcs, enum roc_mcs_event_type event, + roc_mcs_dev_cb_fn cb_fn, void *cb_arg, void *userdata) +{ + struct mcs_event_cb_list *cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs); + struct mcs_event_cb *cb; + + if (cb_fn == NULL || cb_arg == NULL || userdata == NULL) + return -EINVAL; + + MCS_SUPPORT_CHECK; + + TAILQ_FOREACH (cb, cb_list, next) { + if (cb->cb_fn == cb_fn && cb->cb_arg == cb_arg && cb->event == event) + break; + } + + if (cb == NULL) { + cb = plt_zmalloc(sizeof(struct mcs_event_cb), 0); + if (!cb) + return -ENOMEM; + + cb->cb_fn = cb_fn; + cb->cb_arg = cb_arg; + cb->event = event; + mcs->userdata = userdata; + TAILQ_INSERT_TAIL(cb_list, cb, next); + } + + return 0; +} + +int +roc_mcs_event_cb_unregister(struct roc_mcs *mcs, enum roc_mcs_event_type event) +{ + struct mcs_event_cb_list *cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs); + struct mcs_event_cb *cb, *next; + + MCS_SUPPORT_CHECK; + + for (cb = TAILQ_FIRST(cb_list); cb != NULL; cb = next) { + next = TAILQ_NEXT(cb, next); + + if (cb->event != event) + continue; + + if (cb->active == 0) { + TAILQ_REMOVE(cb_list, cb, next); + plt_free(cb); + } else { + return -EAGAIN; + } + } + + return 0; +} + +int +mcs_event_cb_process(struct roc_mcs *mcs, struct roc_mcs_event_desc *desc) +{ + struct mcs_event_cb_list *cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs); + struct mcs_event_cb mcs_cb; + struct mcs_event_cb *cb; + int rc = 0; + + TAILQ_FOREACH (cb, cb_list, next) { + if (cb->cb_fn == NULL || cb->event != desc->type) + continue; + + mcs_cb = *cb; + cb->active = 1; + mcs_cb.ret_param = desc; + + rc = mcs_cb.cb_fn(mcs->userdata, mcs_cb.ret_param, mcs_cb.cb_arg); + cb->active = 0; + } + + return rc; +} + static int mcs_alloc_bmap(uint16_t entries, void **mem, struct plt_bitmap **bmap) { @@ -227,6 +340,7 @@ mcs_alloc_rsrc_bmap(struct roc_mcs *mcs) struct roc_mcs * roc_mcs_dev_init(uint8_t mcs_idx) { + struct mcs_event_cb_list *cb_list; struct roc_mcs *mcs; struct npa_lf *npa; @@ -255,6 +369,9 @@ roc_mcs_dev_init(uint8_t mcs_idx) if (mcs_alloc_rsrc_bmap(mcs)) goto exit; + cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs); + TAILQ_INIT(cb_list); + roc_idev_mcs_set(mcs); mcs->refcount++; diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h index 3fbeee13fa..b2ca6ee51b 100644 --- a/drivers/common/cnxk/roc_mcs.h +++ b/drivers/common/cnxk/roc_mcs.h @@ -116,6 +116,34 @@ struct roc_mcs_hw_info { uint64_t rsvd[16]; }; +#define ROC_MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) +#define ROC_MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) +#define ROC_MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) +#define ROC_MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) +#define ROC_MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) +#define ROC_MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) +#define ROC_MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) +#define ROC_MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) +#define ROC_MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) +#define ROC_MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) +#define ROC_MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) +#define ROC_MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) +#define ROC_MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) +#define ROC_MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) +#define ROC_MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) +#define ROC_MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) + +struct roc_mcs_intr_cfg { + uint64_t intr_mask; /* Interrupt enable mask */ +}; + +struct roc_mcs_intr_info { + uint64_t intr_mask; + int sa_id; + uint8_t lmac_id; + uint64_t rsvd; +}; + struct roc_mcs_set_lmac_mode { uint8_t mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */ uint8_t lmac_id; @@ -205,6 +233,113 @@ struct roc_mcs_clear_stats { uint8_t all; /* All resources stats mapped to PF are cleared */ }; +enum roc_mcs_event_subtype { + ROC_MCS_SUBEVENT_UNKNOWN, + + /* subevents of ROC_MCS_EVENT_SECTAG_VAL_ERR sectag validation events + * ROC_MCS_EVENT_RX_SECTAG_V_EQ1 + * Validation check: SecTag.TCI.V = 1 + * ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1 + * Validation check: SecTag.TCI.E = 0 && SecTag.TCI.C = 1 + * ROC_MCS_EVENT_RX_SECTAG_SL_GTE48 + * Validation check: SecTag.SL >= 'd48 + * ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1 + * Validation check: SecTag.TCI.ES = 1 && SecTag.TCI.SC = 1 + * ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1 + * Validation check: SecTag.TCI.SC = 1 && SecTag.TCI.SCB = 1 + */ + ROC_MCS_EVENT_RX_SECTAG_V_EQ1, + ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1, + ROC_MCS_EVENT_RX_SECTAG_SL_GTE48, + ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1, + ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1, + + /* subevents of ROC_MCS_EVENT_FIFO_OVERFLOW error event + * ROC_MCS_EVENT_DATA_FIFO_OVERFLOW: + * Notifies data FIFO overflow fatal error in BBE unit. + * ROC_MCS_EVENT_POLICY_FIFO_OVERFLOW + * Notifies policy FIFO overflow fatal error in BBE unit. + * ROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW, + * Notifies output FIFO overflow fatal error in PAB unit. + */ + ROC_MCS_EVENT_DATA_FIFO_OVERFLOW, + ROC_MCS_EVENT_POLICY_FIFO_OVERFLOW, + ROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW, +}; + +enum roc_mcs_event_type { + ROC_MCS_EVENT_UNKNOWN, + + /* Notifies BBE_INT_DFIFO/PLFIFO_OVERFLOW or PAB_INT_OVERFLOW + * interrupts, it's a fatal error that causes packet corruption. + */ + ROC_MCS_EVENT_FIFO_OVERFLOW, + + /* Notifies CPM_RX_SECTAG_X validation error interrupt */ + ROC_MCS_EVENT_SECTAG_VAL_ERR, + /* Notifies CPM_RX_PACKET_XPN_EQ0 (SecTag.PN == 0 in ingress) interrupt */ + ROC_MCS_EVENT_RX_SA_PN_HARD_EXP, + /* Notifies CPM_RX_PN_THRESH_REACHED interrupt */ + ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP, + /* Notifies CPM_TX_PACKET_XPN_EQ0 (PN wrapped in egress) interrupt */ + ROC_MCS_EVENT_TX_SA_PN_HARD_EXP, + /* Notifies CPM_TX_PN_THRESH_REACHED interrupt */ + ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP, + /* Notifies CPM_TX_SA_NOT_VALID interrupt */ + ROC_MCS_EVENT_SA_NOT_VALID, + /* Notifies recovery of software driven port reset */ + ROC_MCS_EVENT_PORT_RESET_RECOVERY, +}; + +union roc_mcs_event_data { + /* Valid for below events + * - ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP + * - ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP + */ + struct { + uint8_t secy_idx; + uint8_t sc_idx; + uint8_t sa_idx; + }; + /* Valid for below event + * - ROC_MCS_EVENT_FIFO_OVERFLOW + * + * Upon fatal error notification on a MCS port, ROC driver resets below attributes of active + * flow entities(sc & sa) and than resets the port. + * - Reset NEXT_PN of active SAs to 1. + * - Reset TX active SA for each SC, TX_SA_ACTIVE = 0, SA_INDEX0_VLD = 1. + * - Clear SA_IN_USE for active ANs in RX_SA_MAP_MEM. + * - Clear all stats mapping to this port. + * - Reactivate SA_IN_USE for active ANs in RX_SA_MAP_MEM. + * + * ROC driver notifies the following flow entity(sc & sa) details in application callback, + * application is expected to exchange the Tx/Rx NEXT_PN, TX_SA_ACTIVE, active RX SC AN + * details with peer device so that peer device can resets it's MACsec flow states and than + * resume packet transfers. + */ + struct { + uint16_t *tx_sa_array; /* Tx SAs whose PN memories were reset (NEXT_PN=1) */ + uint16_t *rx_sa_array; /* Rx SAs whose PN memories were reset (NEXT_PN=1) */ + uint16_t *tx_sc_array; /* Tx SCs whose active SAs were reset (TX_SA_ACTIVE=0) */ + uint16_t *rx_sc_array; /* Rx SCs whose state was reset */ + uint8_t *sc_an_array; /* AN of Rx SCs(in rx_sc_array) which were reactivated */ + uint8_t num_tx_sa; /* num entries in tx_sa_array */ + uint8_t num_rx_sa; /* num entries in rx_sa_array */ + uint8_t num_tx_sc; /* num entries in tx_sc_array */ + uint8_t num_rx_sc; /* num entries in rx_sc_array */ + uint8_t lmac_id; /* lmac_id/port which was recovered from fatal error */ + }; +}; + +struct roc_mcs_event_desc { + enum roc_mcs_event_type type; + enum roc_mcs_event_subtype subtype; + union roc_mcs_event_data metadata; +}; + +/** User application callback to be registered for any notifications from driver. */ +typedef int (*roc_mcs_dev_cb_fn)(void *userdata, struct roc_mcs_event_desc *desc, void *cb_arg); + struct roc_mcs { TAILQ_ENTRY(roc_mcs) next; struct plt_pci_device *pci_dev; @@ -292,4 +427,13 @@ __roc_api int roc_mcs_port_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_r /* Clear stats */ __roc_api int roc_mcs_stats_clear(struct roc_mcs *mcs, struct roc_mcs_clear_stats *mcs_req); +/* Register user callback routines */ +__roc_api int roc_mcs_event_cb_register(struct roc_mcs *mcs, enum roc_mcs_event_type event, + roc_mcs_dev_cb_fn cb_fn, void *cb_arg, void *userdata); +/* Unregister user callback routines */ +__roc_api int roc_mcs_event_cb_unregister(struct roc_mcs *mcs, enum roc_mcs_event_type event); + +/* Configure interrupts */ +__roc_api int roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config); + #endif /* _ROC_MCS_H_ */ diff --git a/drivers/common/cnxk/roc_mcs_priv.h b/drivers/common/cnxk/roc_mcs_priv.h index 9e0bbe4392..8da03f4295 100644 --- a/drivers/common/cnxk/roc_mcs_priv.h +++ b/drivers/common/cnxk/roc_mcs_priv.h @@ -62,4 +62,12 @@ roc_mcs_to_mcs_priv(struct roc_mcs *roc_mcs) return (struct mcs_priv *)&roc_mcs->reserved[0]; } +static inline void * +roc_mcs_to_mcs_cb_list(struct roc_mcs *roc_mcs) +{ + return (void *)((uintptr_t)roc_mcs->reserved + sizeof(struct mcs_priv)); +} + +int mcs_event_cb_process(struct roc_mcs *mcs, struct roc_mcs_event_desc *desc); + #endif /* _ROC_MCS_PRIV_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index d8890e3538..d10dfcd84e 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -139,11 +139,14 @@ INTERNAL { roc_mcs_dev_init; roc_mcs_dev_fini; roc_mcs_dev_get; + roc_mcs_event_cb_register; + roc_mcs_event_cb_unregister; roc_mcs_flowid_entry_enable; roc_mcs_flowid_entry_read; roc_mcs_flowid_entry_write; roc_mcs_flowid_stats_get; roc_mcs_hw_info_get; + roc_mcs_intr_configure; roc_mcs_lmac_mode_set; roc_mcs_pn_table_write; roc_mcs_pn_table_read; From patchwork Wed Jun 7 15:28:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128346 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5B2D942C4E; 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Wed, 07 Jun 2023 08:28:49 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 7 Jun 2023 08:28:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:28:47 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 78AF23F7084; Wed, 7 Jun 2023 08:28:45 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 08/15] common/cnxk: add MACsec port configuration Date: Wed, 7 Jun 2023 20:58:12 +0530 Message-ID: <20230607152819.226838-9-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: c-PwhhePFvxxEGXUCZZz4wxQCRAtFmiJ X-Proofpoint-GUID: c-PwhhePFvxxEGXUCZZz4wxQCRAtFmiJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added ROC APIs for MACsec port configurations Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_mbox.h | 40 ++++ drivers/common/cnxk/roc_mcs.c | 346 ++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_mcs.h | 48 +++++ drivers/common/cnxk/version.map | 4 + 4 files changed, 438 insertions(+) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index d964ba9f9d..d7c0385a8b 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -319,6 +319,9 @@ struct mbox_msghdr { M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, msg_rsp) \ + M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ + M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp) \ + M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, mcs_port_cfg_get_rsp) \ /* Messages initiated by AF (range 0xC00 - 0xDFF) */ #define MBOX_UP_CGX_MESSAGES \ @@ -919,6 +922,43 @@ struct mcs_set_pn_threshold { uint64_t __io rsvd; }; +struct mcs_port_cfg_set_req { + struct mbox_msghdr hdr; + uint8_t __io cstm_tag_rel_mode_sel; + uint8_t __io custom_hdr_enb; + uint8_t __io fifo_skid; + uint8_t __io lmac_mode; + uint8_t __io lmac_id; + uint8_t __io mcs_id; + uint64_t __io rsvd; +}; + +struct mcs_port_cfg_get_req { + struct mbox_msghdr hdr; + uint8_t __io lmac_id; + uint8_t __io mcs_id; + uint64_t __io rsvd; +}; + +struct mcs_port_cfg_get_rsp { + struct mbox_msghdr hdr; + uint8_t __io cstm_tag_rel_mode_sel; + uint8_t __io custom_hdr_enb; + uint8_t __io fifo_skid; + uint8_t __io lmac_mode; + uint8_t __io lmac_id; + uint8_t __io mcs_id; + uint64_t __io rsvd; +}; + +struct mcs_port_reset_req { + struct mbox_msghdr hdr; + uint8_t __io reset; + uint8_t __io mcs_id; + uint8_t __io lmac_id; + uint64_t __io rsvd; +}; + struct mcs_stats_req { struct mbox_msghdr hdr; uint8_t __io id; diff --git a/drivers/common/cnxk/roc_mcs.c b/drivers/common/cnxk/roc_mcs.c index e9090da575..e6e6197a49 100644 --- a/drivers/common/cnxk/roc_mcs.c +++ b/drivers/common/cnxk/roc_mcs.c @@ -76,6 +76,25 @@ roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_active_lmac *lma return mbox_process_msg(mcs->mbox, (void *)&rsp); } +static int +mcs_port_reset_set(struct roc_mcs *mcs, struct roc_mcs_port_reset_req *port, uint8_t reset) +{ + struct mcs_port_reset_req *req; + struct msg_rsp *rsp; + + MCS_SUPPORT_CHECK; + + req = mbox_alloc_msg_mcs_port_reset(mcs->mbox); + if (req == NULL) + return -ENOMEM; + + req->reset = reset; + req->lmac_id = port->port_id; + req->mcs_id = mcs->idx; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + int roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port) { @@ -121,6 +140,64 @@ roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *p return mbox_process_msg(mcs->mbox, (void *)&rsp); } +int +roc_mcs_port_cfg_set(struct roc_mcs *mcs, struct roc_mcs_port_cfg_set_req *req) +{ + struct mcs_port_cfg_set_req *set_req; + struct msg_rsp *rsp; + + MCS_SUPPORT_CHECK; + + if (req == NULL) + return -EINVAL; + + set_req = mbox_alloc_msg_mcs_port_cfg_set(mcs->mbox); + if (set_req == NULL) + return -ENOMEM; + + set_req->cstm_tag_rel_mode_sel = req->cstm_tag_rel_mode_sel; + set_req->custom_hdr_enb = req->custom_hdr_enb; + set_req->fifo_skid = req->fifo_skid; + set_req->lmac_mode = req->port_mode; + set_req->lmac_id = req->port_id; + set_req->mcs_id = mcs->idx; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + +int +roc_mcs_port_cfg_get(struct roc_mcs *mcs, struct roc_mcs_port_cfg_get_req *req, + struct roc_mcs_port_cfg_get_rsp *rsp) +{ + struct mcs_port_cfg_get_req *get_req; + struct mcs_port_cfg_get_rsp *get_rsp; + int rc; + + MCS_SUPPORT_CHECK; + + if (req == NULL) + return -EINVAL; + + get_req = mbox_alloc_msg_mcs_port_cfg_get(mcs->mbox); + if (get_req == NULL) + return -ENOMEM; + + get_req->lmac_id = req->port_id; + get_req->mcs_id = mcs->idx; + + rc = mbox_process_msg(mcs->mbox, (void *)&get_rsp); + if (rc) + return rc; + + rsp->cstm_tag_rel_mode_sel = get_rsp->cstm_tag_rel_mode_sel; + rsp->custom_hdr_enb = get_rsp->custom_hdr_enb; + rsp->fifo_skid = get_rsp->fifo_skid; + rsp->port_mode = get_rsp->lmac_mode; + rsp->port_id = get_rsp->lmac_id; + + return 0; +} + int roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config) { @@ -142,6 +219,275 @@ roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config) return mbox_process_msg(mcs->mbox, (void *)&rsp); } +int +roc_mcs_port_recovery(struct roc_mcs *mcs, union roc_mcs_event_data *mdata, uint8_t port_id) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct roc_mcs_pn_table_write_req pn_table = {0}; + struct roc_mcs_rx_sc_sa_map rx_map = {0}; + struct roc_mcs_tx_sc_sa_map tx_map = {0}; + struct roc_mcs_port_reset_req port = {0}; + struct roc_mcs_clear_stats stats = {0}; + int tx_cnt = 0, rx_cnt = 0, rc = 0; + uint64_t set; + int i; + + port.port_id = port_id; + rc = mcs_port_reset_set(mcs, &port, 1); + + /* Reset TX/RX PN tables */ + for (i = 0; i < (priv->sa_entries << 1); i++) { + set = plt_bitmap_get(priv->port_rsrc[port_id].sa_bmap, i); + if (set) { + pn_table.pn_id = i; + pn_table.next_pn = 1; + pn_table.dir = MCS_RX; + if (i >= priv->sa_entries) { + pn_table.dir = MCS_TX; + pn_table.pn_id -= priv->sa_entries; + } + rc = roc_mcs_pn_table_write(mcs, &pn_table); + if (rc) + return rc; + + if (i >= priv->sa_entries) + tx_cnt++; + else + rx_cnt++; + } + } + + if (tx_cnt || rx_cnt) { + mdata->tx_sa_array = plt_zmalloc(tx_cnt * sizeof(uint16_t), 0); + if (tx_cnt && (mdata->tx_sa_array == NULL)) { + rc = -ENOMEM; + goto exit; + } + mdata->rx_sa_array = plt_zmalloc(rx_cnt * sizeof(uint16_t), 0); + if (rx_cnt && (mdata->rx_sa_array == NULL)) { + rc = -ENOMEM; + goto exit; + } + + mdata->num_tx_sa = tx_cnt; + mdata->num_rx_sa = rx_cnt; + for (i = 0; i < (priv->sa_entries << 1); i++) { + set = plt_bitmap_get(priv->port_rsrc[port_id].sa_bmap, i); + if (set) { + if (i >= priv->sa_entries) + mdata->tx_sa_array[--tx_cnt] = i - priv->sa_entries; + else + mdata->rx_sa_array[--rx_cnt] = i; + } + } + } + tx_cnt = 0; + rx_cnt = 0; + + /* Reset Tx active SA to index:0 */ + for (i = priv->sc_entries; i < (priv->sc_entries << 1); i++) { + set = plt_bitmap_get(priv->port_rsrc[port_id].sc_bmap, i); + if (set) { + uint16_t sc_id = i - priv->sc_entries; + + tx_map.sa_index0 = priv->port_rsrc[port_id].sc_conf[sc_id].tx.sa_idx0; + tx_map.sa_index1 = priv->port_rsrc[port_id].sc_conf[sc_id].tx.sa_idx1; + tx_map.rekey_ena = priv->port_rsrc[port_id].sc_conf[sc_id].tx.rekey_enb; + tx_map.sectag_sci = priv->port_rsrc[port_id].sc_conf[sc_id].tx.sci; + tx_map.sa_index0_vld = 1; + tx_map.sa_index1_vld = 0; + tx_map.tx_sa_active = 0; + tx_map.sc_id = sc_id; + rc = roc_mcs_tx_sc_sa_map_write(mcs, &tx_map); + if (rc) + return rc; + + tx_cnt++; + } + } + + if (tx_cnt) { + mdata->tx_sc_array = plt_zmalloc(tx_cnt * sizeof(uint16_t), 0); + if (tx_cnt && (mdata->tx_sc_array == NULL)) { + rc = -ENOMEM; + goto exit; + } + + mdata->num_tx_sc = tx_cnt; + for (i = priv->sc_entries; i < (priv->sc_entries << 1); i++) { + set = plt_bitmap_get(priv->port_rsrc[port_id].sc_bmap, i); + if (set) + mdata->tx_sc_array[--tx_cnt] = i - priv->sc_entries; + } + } + + /* Clear SA_IN_USE for active ANs in RX CPM */ + for (i = 0; i < priv->sc_entries; i++) { + set = plt_bitmap_get(priv->port_rsrc[port_id].sc_bmap, i); + if (set) { + rx_map.sa_index = priv->port_rsrc[port_id].sc_conf[i].rx.sa_idx; + rx_map.an = priv->port_rsrc[port_id].sc_conf[i].rx.an; + rx_map.sa_in_use = 0; + rx_map.sc_id = i; + rc = roc_mcs_rx_sc_sa_map_write(mcs, &rx_map); + if (rc) + return rc; + + rx_cnt++; + } + } + + /* Reset flow(flow/secy/sc/sa) stats mapped to this PORT */ + for (i = 0; i < (priv->tcam_entries << 1); i++) { + set = plt_bitmap_get(priv->port_rsrc[port_id].tcam_bmap, i); + if (set) { + stats.type = MCS_FLOWID_STATS; + stats.id = i; + stats.dir = MCS_RX; + if (i >= priv->sa_entries) { + stats.dir = MCS_TX; + stats.id -= priv->tcam_entries; + } + rc = roc_mcs_stats_clear(mcs, &stats); + if (rc) + return rc; + } + } + for (i = 0; i < (priv->secy_entries << 1); i++) { + set = plt_bitmap_get(priv->port_rsrc[port_id].secy_bmap, i); + if (set) { + stats.type = MCS_SECY_STATS; + stats.id = i; + stats.dir = MCS_RX; + if (i >= priv->sa_entries) { + stats.dir = MCS_TX; + stats.id -= priv->secy_entries; + } + rc = roc_mcs_stats_clear(mcs, &stats); + if (rc) + return rc; + } + } + for (i = 0; i < (priv->sc_entries << 1); i++) { + set = plt_bitmap_get(priv->port_rsrc[port_id].sc_bmap, i); + if (set) { + stats.type = MCS_SC_STATS; + stats.id = i; + stats.dir = MCS_RX; + if (i >= priv->sa_entries) { + stats.dir = MCS_TX; + stats.id -= priv->sc_entries; + } + rc = roc_mcs_stats_clear(mcs, &stats); + if (rc) + return rc; + } + } + if (roc_model_is_cn10kb_a0()) { + for (i = 0; i < (priv->sa_entries << 1); i++) { + set = plt_bitmap_get(priv->port_rsrc[port_id].sa_bmap, i); + if (set) { + stats.type = MCS_SA_STATS; + stats.id = i; + stats.dir = MCS_RX; + if (i >= priv->sa_entries) { + stats.dir = MCS_TX; + stats.id -= priv->sa_entries; + } + rc = roc_mcs_stats_clear(mcs, &stats); + if (rc) + return rc; + } + } + } + { + stats.type = MCS_PORT_STATS; + stats.id = port_id; + rc = roc_mcs_stats_clear(mcs, &stats); + if (rc) + return rc; + } + + if (rx_cnt) { + mdata->rx_sc_array = plt_zmalloc(rx_cnt * sizeof(uint16_t), 0); + if (mdata->rx_sc_array == NULL) { + rc = -ENOMEM; + goto exit; + } + mdata->sc_an_array = plt_zmalloc(rx_cnt * sizeof(uint8_t), 0); + if (mdata->sc_an_array == NULL) { + rc = -ENOMEM; + goto exit; + } + + mdata->num_rx_sc = rx_cnt; + } + + /* Reactivate in-use ANs for active SCs in RX CPM */ + for (i = 0; i < priv->sc_entries; i++) { + set = plt_bitmap_get(priv->port_rsrc[port_id].sc_bmap, i); + if (set) { + rx_map.sa_index = priv->port_rsrc[port_id].sc_conf[i].rx.sa_idx; + rx_map.an = priv->port_rsrc[port_id].sc_conf[i].rx.an; + rx_map.sa_in_use = 1; + rx_map.sc_id = i; + rc = roc_mcs_rx_sc_sa_map_write(mcs, &rx_map); + if (rc) + return rc; + + mdata->rx_sc_array[--rx_cnt] = i; + mdata->sc_an_array[rx_cnt] = priv->port_rsrc[port_id].sc_conf[i].rx.an; + } + } + + port.port_id = port_id; + rc = mcs_port_reset_set(mcs, &port, 0); + + return rc; +exit: + if (mdata->num_tx_sa) + plt_free(mdata->tx_sa_array); + if (mdata->num_rx_sa) + plt_free(mdata->rx_sa_array); + if (mdata->num_tx_sc) + plt_free(mdata->tx_sc_array); + if (mdata->num_rx_sc) { + plt_free(mdata->rx_sc_array); + plt_free(mdata->sc_an_array); + } + return rc; +} + +int +roc_mcs_port_reset(struct roc_mcs *mcs, struct roc_mcs_port_reset_req *port) +{ + struct roc_mcs_event_desc desc = {0}; + int rc; + + /* Initiate port reset and software recovery */ + rc = roc_mcs_port_recovery(mcs, &desc.metadata, port->port_id); + if (rc) + goto exit; + + desc.type = ROC_MCS_EVENT_PORT_RESET_RECOVERY; + /* Notify the entity details to the application which are recovered */ + mcs_event_cb_process(mcs, &desc); + +exit: + if (desc.metadata.num_tx_sa) + plt_free(desc.metadata.tx_sa_array); + if (desc.metadata.num_rx_sa) + plt_free(desc.metadata.rx_sa_array); + if (desc.metadata.num_tx_sc) + plt_free(desc.metadata.tx_sc_array); + if (desc.metadata.num_rx_sc) { + plt_free(desc.metadata.rx_sc_array); + plt_free(desc.metadata.sc_an_array); + } + + return rc; +} + int roc_mcs_event_cb_register(struct roc_mcs *mcs, enum roc_mcs_event_type event, roc_mcs_dev_cb_fn cb_fn, void *cb_arg, void *userdata) diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h index b2ca6ee51b..d06057726f 100644 --- a/drivers/common/cnxk/roc_mcs.h +++ b/drivers/common/cnxk/roc_mcs.h @@ -163,6 +163,43 @@ struct roc_mcs_set_pn_threshold { uint64_t rsvd; }; +struct roc_mcs_port_cfg_set_req { + /* Index of custom tag (= cstm_indx[x] in roc_mcs_custom_tag_cfg_get_rsp struct) to use + * when TX SECY_PLCY_MEMX[SECTAG_INSERT_MODE] = 0 (relative offset mode) + */ + uint8_t cstm_tag_rel_mode_sel; + /* In ingress path, custom_hdr_enb = 1 when the port is expected to receive pkts + * that have 8B custom header before DMAC + */ + uint8_t custom_hdr_enb; + /* Valid fifo skid values are 14,28,56 for 25G,50G,100G respectively + * FIFOs need to be configured based on the port_mode, valid only for 105N + */ + uint8_t fifo_skid; + uint8_t port_mode; /* 2'b00 - 25G or less, 2'b01 - 50G, 2'b10 - 100G */ + uint8_t port_id; + uint64_t rsvd; +}; + +struct roc_mcs_port_cfg_get_req { + uint8_t port_id; + uint64_t rsvd; +}; + +struct roc_mcs_port_cfg_get_rsp { + uint8_t cstm_tag_rel_mode_sel; + uint8_t custom_hdr_enb; + uint8_t fifo_skid; + uint8_t port_mode; + uint8_t port_id; + uint64_t rsvd; +}; + +struct roc_mcs_port_reset_req { + uint8_t port_id; + uint64_t rsvd; +}; + struct roc_mcs_stats_req { uint8_t id; uint8_t dir; @@ -367,6 +404,13 @@ __roc_api int roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_ac __roc_api int roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port); /* (X)PN threshold set */ __roc_api int roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *pn); +/* Reset port */ +__roc_api int roc_mcs_port_reset(struct roc_mcs *mcs, struct roc_mcs_port_reset_req *port); +/* Get port config */ +__roc_api int roc_mcs_port_cfg_set(struct roc_mcs *mcs, struct roc_mcs_port_cfg_set_req *req); +/* Set port config */ +__roc_api int roc_mcs_port_cfg_get(struct roc_mcs *mcs, struct roc_mcs_port_cfg_get_req *req, + struct roc_mcs_port_cfg_get_rsp *rsp); /* Resource allocation and free */ __roc_api int roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req, @@ -436,4 +480,8 @@ __roc_api int roc_mcs_event_cb_unregister(struct roc_mcs *mcs, enum roc_mcs_even /* Configure interrupts */ __roc_api int roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config); +/* Port recovery from fatal errors */ +__roc_api int roc_mcs_port_recovery(struct roc_mcs *mcs, union roc_mcs_event_data *mdata, + uint8_t port_id); + #endif /* _ROC_MCS_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index d10dfcd84e..6c0defa27e 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -151,6 +151,10 @@ INTERNAL { roc_mcs_pn_table_write; roc_mcs_pn_table_read; roc_mcs_pn_threshold_set; + roc_mcs_port_cfg_get; + roc_mcs_port_cfg_set; + roc_mcs_port_recovery; + roc_mcs_port_reset; roc_mcs_port_stats_get; roc_mcs_rsrc_alloc; roc_mcs_rsrc_free; From patchwork Wed Jun 7 15:28:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128347 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 58CBF42C4E; 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Wed, 07 Jun 2023 08:28:52 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 7 Jun 2023 08:28:50 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:28:50 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 670183F708C; Wed, 7 Jun 2023 08:28:48 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 09/15] common/cnxk: add MACsec control port configuration Date: Wed, 7 Jun 2023 20:58:13 +0530 Message-ID: <20230607152819.226838-10-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ESSjMO3wzcG3bnHjKA44mvUnErh-Y19e X-Proofpoint-GUID: ESSjMO3wzcG3bnHjKA44mvUnErh-Y19e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added ROC APIs to configure MACsec control port. Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_mbox.h | 72 ++++++++++++++++++++ drivers/common/cnxk/roc_mcs.c | 117 ++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_mcs.h | 65 ++++++++++++++++++ drivers/common/cnxk/version.map | 4 ++ 4 files changed, 258 insertions(+) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index d7c0385a8b..446f49aeaf 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -319,9 +319,17 @@ struct mbox_msghdr { M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, msg_rsp) \ + M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, mcs_alloc_ctrl_pkt_rule_req, \ + mcs_alloc_ctrl_pkt_rule_rsp) \ + M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, mcs_free_ctrl_pkt_rule_req, \ + msg_rsp) \ + M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, mcs_ctrl_pkt_rule_write_req, \ + msg_rsp) \ M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp) \ M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, mcs_port_cfg_get_rsp) \ + M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, mcs_custom_tag_cfg_get_req, \ + mcs_custom_tag_cfg_get_rsp) \ /* Messages initiated by AF (range 0xC00 - 0xDFF) */ #define MBOX_UP_CGX_MESSAGES \ @@ -922,6 +930,53 @@ struct mcs_set_pn_threshold { uint64_t __io rsvd; }; +enum mcs_ctrl_pkt_rule_type { + MCS_CTRL_PKT_RULE_TYPE_ETH, + MCS_CTRL_PKT_RULE_TYPE_DA, + MCS_CTRL_PKT_RULE_TYPE_RANGE, + MCS_CTRL_PKT_RULE_TYPE_COMBO, + MCS_CTRL_PKT_RULE_TYPE_MAC, +}; + +struct mcs_alloc_ctrl_pkt_rule_req { + struct mbox_msghdr hdr; + uint8_t __io rule_type; + uint8_t __io mcs_id; /* MCS block ID */ + uint8_t __io dir; /* Macsec ingress or egress side */ + uint64_t __io rsvd; +}; + +struct mcs_alloc_ctrl_pkt_rule_rsp { + struct mbox_msghdr hdr; + uint8_t __io rule_idx; + uint8_t __io rule_type; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + +struct mcs_free_ctrl_pkt_rule_req { + struct mbox_msghdr hdr; + uint8_t __io rule_idx; + uint8_t __io rule_type; + uint8_t __io mcs_id; + uint8_t __io dir; + uint8_t __io all; /* Free all the rule resources */ + uint64_t __io rsvd; +}; + +struct mcs_ctrl_pkt_rule_write_req { + struct mbox_msghdr hdr; + uint64_t __io data0; + uint64_t __io data1; + uint64_t __io data2; + uint8_t __io rule_idx; + uint8_t __io rule_type; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + struct mcs_port_cfg_set_req { struct mbox_msghdr hdr; uint8_t __io cstm_tag_rel_mode_sel; @@ -951,6 +1006,23 @@ struct mcs_port_cfg_get_rsp { uint64_t __io rsvd; }; +struct mcs_custom_tag_cfg_get_req { + struct mbox_msghdr hdr; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + +struct mcs_custom_tag_cfg_get_rsp { + struct mbox_msghdr hdr; + uint16_t __io cstm_etype[8]; + uint8_t __io cstm_indx[8]; + uint8_t __io cstm_etype_en; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + struct mcs_port_reset_req { struct mbox_msghdr hdr; uint8_t __io reset; diff --git a/drivers/common/cnxk/roc_mcs.c b/drivers/common/cnxk/roc_mcs.c index e6e6197a49..1e3235ad73 100644 --- a/drivers/common/cnxk/roc_mcs.c +++ b/drivers/common/cnxk/roc_mcs.c @@ -140,6 +140,88 @@ roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *p return mbox_process_msg(mcs->mbox, (void *)&rsp); } +int +roc_mcs_ctrl_pkt_rule_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_ctrl_pkt_rule_req *req, + struct roc_mcs_alloc_ctrl_pkt_rule_rsp *rsp) +{ + struct mcs_alloc_ctrl_pkt_rule_req *rule_req; + struct mcs_alloc_ctrl_pkt_rule_rsp *rule_rsp; + int rc; + + MCS_SUPPORT_CHECK; + + if (req == NULL || rsp == NULL) + return -EINVAL; + + rule_req = mbox_alloc_msg_mcs_alloc_ctrl_pkt_rule(mcs->mbox); + if (rule_req == NULL) + return -ENOMEM; + + rule_req->rule_type = req->rule_type; + rule_req->mcs_id = mcs->idx; + rule_req->dir = req->dir; + + rc = mbox_process_msg(mcs->mbox, (void *)&rule_rsp); + if (rc) + return rc; + + rsp->rule_type = rule_rsp->rule_type; + rsp->rule_idx = rule_rsp->rule_idx; + rsp->dir = rule_rsp->dir; + + return 0; +} + +int +roc_mcs_ctrl_pkt_rule_free(struct roc_mcs *mcs, struct roc_mcs_free_ctrl_pkt_rule_req *req) +{ + struct mcs_free_ctrl_pkt_rule_req *rule_req; + struct msg_rsp *rsp; + + MCS_SUPPORT_CHECK; + + if (req == NULL) + return -EINVAL; + + rule_req = mbox_alloc_msg_mcs_free_ctrl_pkt_rule(mcs->mbox); + if (rule_req == NULL) + return -ENOMEM; + + rule_req->rule_type = req->rule_type; + rule_req->rule_idx = req->rule_idx; + rule_req->mcs_id = mcs->idx; + rule_req->dir = req->dir; + rule_req->all = req->all; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + +int +roc_mcs_ctrl_pkt_rule_write(struct roc_mcs *mcs, struct roc_mcs_ctrl_pkt_rule_write_req *req) +{ + struct mcs_ctrl_pkt_rule_write_req *rule_req; + struct msg_rsp *rsp; + + MCS_SUPPORT_CHECK; + + if (req == NULL) + return -EINVAL; + + rule_req = mbox_alloc_msg_mcs_ctrl_pkt_rule_write(mcs->mbox); + if (rule_req == NULL) + return -ENOMEM; + + rule_req->rule_type = req->rule_type; + rule_req->rule_idx = req->rule_idx; + rule_req->mcs_id = mcs->idx; + rule_req->dir = req->dir; + rule_req->data0 = req->data0; + rule_req->data1 = req->data1; + rule_req->data2 = req->data2; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + int roc_mcs_port_cfg_set(struct roc_mcs *mcs, struct roc_mcs_port_cfg_set_req *req) { @@ -198,6 +280,41 @@ roc_mcs_port_cfg_get(struct roc_mcs *mcs, struct roc_mcs_port_cfg_get_req *req, return 0; } +int +roc_mcs_custom_tag_cfg_get(struct roc_mcs *mcs, struct roc_mcs_custom_tag_cfg_get_req *req, + struct roc_mcs_custom_tag_cfg_get_rsp *rsp) +{ + struct mcs_custom_tag_cfg_get_req *get_req; + struct mcs_custom_tag_cfg_get_rsp *get_rsp; + int i, rc; + + MCS_SUPPORT_CHECK; + + if (req == NULL) + return -EINVAL; + + get_req = mbox_alloc_msg_mcs_custom_tag_cfg_get(mcs->mbox); + if (get_req == NULL) + return -ENOMEM; + + get_req->dir = req->dir; + get_req->mcs_id = mcs->idx; + + rc = mbox_process_msg(mcs->mbox, (void *)&get_rsp); + if (rc) + return rc; + + for (i = 0; i < 8; i++) { + rsp->cstm_etype[i] = get_rsp->cstm_etype[i]; + rsp->cstm_indx[i] = get_rsp->cstm_indx[i]; + } + + rsp->cstm_etype_en = get_rsp->cstm_etype_en; + rsp->dir = get_rsp->dir; + + return 0; +} + int roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config) { diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h index d06057726f..e8d6b070db 100644 --- a/drivers/common/cnxk/roc_mcs.h +++ b/drivers/common/cnxk/roc_mcs.h @@ -163,6 +163,45 @@ struct roc_mcs_set_pn_threshold { uint64_t rsvd; }; +enum roc_mcs_ctrl_pkt_rule_type { + ROC_MCS_CTRL_PKT_RULE_TYPE_ETH, + ROC_MCS_CTRL_PKT_RULE_TYPE_DA, + ROC_MCS_CTRL_PKT_RULE_TYPE_RANGE, + ROC_MCS_CTRL_PKT_RULE_TYPE_COMBO, + ROC_MCS_CTRL_PKT_RULE_TYPE_MAC, +}; + +struct roc_mcs_alloc_ctrl_pkt_rule_req { + uint8_t rule_type; + uint8_t dir; /* Macsec ingress or egress side */ + uint64_t rsvd; +}; + +struct roc_mcs_alloc_ctrl_pkt_rule_rsp { + uint8_t rule_idx; + uint8_t rule_type; + uint8_t dir; + uint64_t rsvd; +}; + +struct roc_mcs_free_ctrl_pkt_rule_req { + uint8_t rule_idx; + uint8_t rule_type; + uint8_t dir; + uint8_t all; /* Free all the rule resources */ + uint64_t rsvd; +}; + +struct roc_mcs_ctrl_pkt_rule_write_req { + uint64_t data0; + uint64_t data1; + uint64_t data2; + uint8_t rule_idx; + uint8_t rule_type; + uint8_t dir; + uint64_t rsvd; +}; + struct roc_mcs_port_cfg_set_req { /* Index of custom tag (= cstm_indx[x] in roc_mcs_custom_tag_cfg_get_rsp struct) to use * when TX SECY_PLCY_MEMX[SECTAG_INSERT_MODE] = 0 (relative offset mode) @@ -195,6 +234,19 @@ struct roc_mcs_port_cfg_get_rsp { uint64_t rsvd; }; +struct roc_mcs_custom_tag_cfg_get_req { + uint8_t dir; + uint64_t rsvd; +}; + +struct roc_mcs_custom_tag_cfg_get_rsp { + uint16_t cstm_etype[8]; /* EthType/TPID */ + uint8_t cstm_indx[8]; /* Custom tag index used to identify the VLAN etype */ + uint8_t cstm_etype_en; /* bitmap of enabled custom tags */ + uint8_t dir; + uint64_t rsvd; +}; + struct roc_mcs_port_reset_req { uint8_t port_id; uint64_t rsvd; @@ -411,6 +463,10 @@ __roc_api int roc_mcs_port_cfg_set(struct roc_mcs *mcs, struct roc_mcs_port_cfg_ /* Set port config */ __roc_api int roc_mcs_port_cfg_get(struct roc_mcs *mcs, struct roc_mcs_port_cfg_get_req *req, struct roc_mcs_port_cfg_get_rsp *rsp); +/* Get custom tag config */ +__roc_api int roc_mcs_custom_tag_cfg_get(struct roc_mcs *mcs, + struct roc_mcs_custom_tag_cfg_get_req *req, + struct roc_mcs_custom_tag_cfg_get_rsp *rsp); /* Resource allocation and free */ __roc_api int roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req, @@ -456,6 +512,15 @@ __roc_api int roc_mcs_flowid_entry_read(struct roc_mcs *mcs, __roc_api int roc_mcs_flowid_entry_enable(struct roc_mcs *mcs, struct roc_mcs_flowid_ena_dis_entry *entry); +/* Control packet rule alloc, free and write */ +__roc_api int roc_mcs_ctrl_pkt_rule_alloc(struct roc_mcs *mcs, + struct roc_mcs_alloc_ctrl_pkt_rule_req *req, + struct roc_mcs_alloc_ctrl_pkt_rule_rsp *rsp); +__roc_api int roc_mcs_ctrl_pkt_rule_free(struct roc_mcs *mcs, + struct roc_mcs_free_ctrl_pkt_rule_req *req); +__roc_api int roc_mcs_ctrl_pkt_rule_write(struct roc_mcs *mcs, + struct roc_mcs_ctrl_pkt_rule_write_req *req); + /* Flow id stats get */ __roc_api int roc_mcs_flowid_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req, struct roc_mcs_flowid_stats *stats); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 6c0defa27e..914d0d2caa 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -136,6 +136,10 @@ INTERNAL { roc_se_ciph_key_set; roc_se_ctx_init; roc_mcs_active_lmac_set; + roc_mcs_ctrl_pkt_rule_alloc; + roc_mcs_ctrl_pkt_rule_free; + roc_mcs_ctrl_pkt_rule_write; + roc_mcs_custom_tag_cfg_get; roc_mcs_dev_init; roc_mcs_dev_fini; roc_mcs_dev_get; From patchwork Wed Jun 7 15:28:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128348 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5EFC942C4E; Wed, 7 Jun 2023 17:29:37 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 70A6442DAA; Wed, 7 Jun 2023 17:28:58 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id DCD2D42D9C for ; Wed, 7 Jun 2023 17:28:56 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 357Dvl00028208; Wed, 7 Jun 2023 08:28:56 -0700 DKIM-Signature: v=1; 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Wed, 7 Jun 2023 08:28:53 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 55A513F7084; Wed, 7 Jun 2023 08:28:51 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 10/15] common/cnxk: add MACsec FIPS mbox Date: Wed, 7 Jun 2023 20:58:14 +0530 Message-ID: <20230607152819.226838-11-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 7fNF3yZBZoaAGiGvZSbKGZoU5aHcL-qT X-Proofpoint-GUID: 7fNF3yZBZoaAGiGvZSbKGZoU5aHcL-qT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added MACsec FIPS configuration mbox Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_mbox.h | 74 ++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_mcs.h | 69 +++++++++++++++++++++++++++++++ 2 files changed, 143 insertions(+) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 446f49aeaf..2f85b2f755 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -330,6 +330,15 @@ struct mbox_msghdr { M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, mcs_port_cfg_get_rsp) \ M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, mcs_custom_tag_cfg_get_req, \ mcs_custom_tag_cfg_get_rsp) \ + M(MCS_FIPS_RESET, 0xa040, mcs_fips_reset, mcs_fips_req, msg_rsp) \ + M(MCS_FIPS_MODE_SET, 0xa041, mcs_fips_mode_set, mcs_fips_mode_req, msg_rsp) \ + M(MCS_FIPS_CTL_SET, 0xa042, mcs_fips_ctl_set, mcs_fips_ctl_req, msg_rsp) \ + M(MCS_FIPS_IV_SET, 0xa043, mcs_fips_iv_set, mcs_fips_iv_req, msg_rsp) \ + M(MCS_FIPS_CTR_SET, 0xa044, mcs_fips_ctr_set, mcs_fips_ctr_req, msg_rsp) \ + M(MCS_FIPS_KEY_SET, 0xa045, mcs_fips_key_set, mcs_fips_key_req, msg_rsp) \ + M(MCS_FIPS_BLOCK_SET, 0xa046, mcs_fips_block_set, mcs_fips_block_req, msg_rsp) \ + M(MCS_FIPS_START, 0xa047, mcs_fips_start, mcs_fips_req, msg_rsp) \ + M(MCS_FIPS_RESULT_GET, 0xa048, mcs_fips_result_get, mcs_fips_req, mcs_fips_result_rsp) /* Messages initiated by AF (range 0xC00 - 0xDFF) */ #define MBOX_UP_CGX_MESSAGES \ @@ -1119,6 +1128,71 @@ struct mcs_clear_stats { uint8_t __io all; /* All resources stats mapped to PF are cleared */ }; +struct mcs_fips_req { + struct mbox_msghdr hdr; + uint8_t __io mcs_id; + uint8_t __io dir; +}; + +struct mcs_fips_mode_req { + struct mbox_msghdr hdr; + uint64_t __io mode; + uint8_t __io mcs_id; + uint8_t __io dir; +}; + +struct mcs_fips_ctl_req { + struct mbox_msghdr hdr; + uint64_t __io ctl; + uint8_t __io mcs_id; + uint8_t __io dir; +}; + +struct mcs_fips_iv_req { + struct mbox_msghdr hdr; + uint32_t __io iv_bits95_64; + uint64_t __io iv_bits63_0; + uint8_t __io mcs_id; + uint8_t __io dir; +}; + +struct mcs_fips_ctr_req { + struct mbox_msghdr hdr; + uint32_t __io fips_ctr; + uint8_t __io mcs_id; + uint8_t __io dir; +}; + +struct mcs_fips_key_req { + struct mbox_msghdr hdr; + uint64_t __io sak_bits255_192; + uint64_t __io sak_bits191_128; + uint64_t __io sak_bits127_64; + uint64_t __io sak_bits63_0; + uint64_t __io hashkey_bits127_64; + uint64_t __io hashkey_bits63_0; + uint8_t __io sak_len; + uint8_t __io mcs_id; + uint8_t __io dir; +}; + +struct mcs_fips_block_req { + struct mbox_msghdr hdr; + uint64_t __io blk_bits127_64; + uint64_t __io blk_bits63_0; + uint8_t __io mcs_id; + uint8_t __io dir; +}; + +struct mcs_fips_result_rsp { + struct mbox_msghdr hdr; + uint64_t __io blk_bits127_64; + uint64_t __io blk_bits63_0; + uint64_t __io icv_bits127_64; + uint64_t __io icv_bits63_0; + uint8_t __io result_pass; +}; + /* NPA mbox message formats */ /* NPA mailbox error codes diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h index e8d6b070db..5b1423ac8f 100644 --- a/drivers/common/cnxk/roc_mcs.h +++ b/drivers/common/cnxk/roc_mcs.h @@ -426,6 +426,56 @@ struct roc_mcs_event_desc { union roc_mcs_event_data metadata; }; +struct roc_mcs_fips_req { + uint8_t dir; +}; + +struct roc_mcs_fips_mode { + uint64_t mode; + uint8_t dir; +}; + +struct roc_mcs_fips_ctl { + uint64_t ctl; + uint8_t dir; +}; + +struct roc_mcs_fips_iv { + uint32_t iv_bits95_64; + uint64_t iv_bits63_0; + uint8_t dir; +}; + +struct roc_mcs_fips_ctr { + uint32_t fips_ctr; + uint8_t dir; +}; + +struct roc_mcs_fips_key { + uint64_t sak_bits255_192; + uint64_t sak_bits191_128; + uint64_t sak_bits127_64; + uint64_t sak_bits63_0; + uint64_t hashkey_bits127_64; + uint64_t hashkey_bits63_0; + uint8_t sak_len; + uint8_t dir; +}; + +struct roc_mcs_fips_block { + uint64_t blk_bits127_64; + uint64_t blk_bits63_0; + uint8_t dir; +}; + +struct roc_mcs_fips_result_rsp { + uint64_t blk_bits127_64; + uint64_t blk_bits63_0; + uint64_t icv_bits127_64; + uint64_t icv_bits63_0; + uint8_t result_pass; +}; + /** User application callback to be registered for any notifications from driver. */ typedef int (*roc_mcs_dev_cb_fn)(void *userdata, struct roc_mcs_event_desc *desc, void *cb_arg); @@ -549,4 +599,23 @@ __roc_api int roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cf __roc_api int roc_mcs_port_recovery(struct roc_mcs *mcs, union roc_mcs_event_data *mdata, uint8_t port_id); +/* FIPS reset */ +__roc_api int roc_mcs_fips_reset(struct roc_mcs *mcs, struct roc_mcs_fips_req *req); +/* FIPS mode set */ +__roc_api int roc_mcs_fips_mode_set(struct roc_mcs *mcs, struct roc_mcs_fips_mode *req); +/* FIPS ctl set */ +__roc_api int roc_mcs_fips_ctl_set(struct roc_mcs *mcs, struct roc_mcs_fips_ctl *req); +/* FIPS iv set */ +__roc_api int roc_mcs_fips_iv_set(struct roc_mcs *mcs, struct roc_mcs_fips_iv *req); +/* FIPS ctr set */ +__roc_api int roc_mcs_fips_ctr_set(struct roc_mcs *mcs, struct roc_mcs_fips_ctr *req); +/* FIPS key set */ +__roc_api int roc_mcs_fips_key_set(struct roc_mcs *mcs, struct roc_mcs_fips_key *req); +/* FIPS block set */ +__roc_api int roc_mcs_fips_block_set(struct roc_mcs *mcs, struct roc_mcs_fips_block *req); +/* FIPS start */ +__roc_api int roc_mcs_fips_start(struct roc_mcs *mcs, struct roc_mcs_fips_req *req); +/* FIPS result */ +__roc_api int roc_mcs_fips_result_get(struct roc_mcs *mcs, struct roc_mcs_fips_req *req, + struct roc_mcs_fips_result_rsp *rsp); #endif /* _ROC_MCS_H_ */ From patchwork Wed Jun 7 15:28:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128349 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9551E42C4E; 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Wed, 07 Jun 2023 08:28:58 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 7 Jun 2023 08:28:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:28:56 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 43C3A3F708C; Wed, 7 Jun 2023 08:28:54 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 11/15] common/cnxk: derive hash key for MACsec Date: Wed, 7 Jun 2023 20:58:15 +0530 Message-ID: <20230607152819.226838-12-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: a5MU9FJoIC5QAwZwiyKEB_672Dqf3jZZ X-Proofpoint-GUID: a5MU9FJoIC5QAwZwiyKEB_672Dqf3jZZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MACsec hardware configuration need hash key to be generated from the cipher key of AES-GCM-128/256. Added an ROC API to derive the hash key and extend the case for AES-256 as well. Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_aes.c | 86 ++++++++++++++++++++++----------- drivers/common/cnxk/roc_aes.h | 4 +- drivers/common/cnxk/version.map | 1 + 3 files changed, 60 insertions(+), 31 deletions(-) diff --git a/drivers/common/cnxk/roc_aes.c b/drivers/common/cnxk/roc_aes.c index f821c8b710..d84feb546a 100644 --- a/drivers/common/cnxk/roc_aes.c +++ b/drivers/common/cnxk/roc_aes.c @@ -4,9 +4,10 @@ #include "roc_api.h" -#define KEY_WORD_LEN (ROC_CPT_AES_XCBC_KEY_LENGTH / sizeof(uint32_t)) -#define KEY_ROUNDS 10 /* (Nr+1)*Nb */ -#define KEY_SCHEDULE_LEN ((KEY_ROUNDS + 1) * 4) /* (Nr+1)*Nb words */ +#define KEY128_ROUNDS 10 /* (Nr+1)*Nb */ +#define KEY256_ROUNDS 14 /* (Nr+1)*Nb */ +#define KEY_SCHEDULE_LEN(nr) ((nr + 1) * 4) /* (Nr+1)*Nb words */ +#define AES_HASH_KEY_LEN 16 /* * AES 128 implementation based on NIST FIPS 197 suitable for LittleEndian @@ -93,22 +94,30 @@ GF8mul(uint8_t byte, uint32_t mp) } static void -aes_key_expand(const uint8_t *key, uint32_t *ks) +aes_key_expand(const uint8_t *key, uint32_t len, uint32_t *ks) { - unsigned int i = 4; + uint32_t len_words = len / sizeof(uint32_t); + unsigned int schedule_len; + unsigned int i = len_words; uint32_t temp; + schedule_len = (len == ROC_CPT_AES128_KEY_LEN) ? KEY_SCHEDULE_LEN(KEY128_ROUNDS) : + KEY_SCHEDULE_LEN(KEY256_ROUNDS); /* Skip key in ks */ - memcpy(ks, key, KEY_WORD_LEN * sizeof(uint32_t)); + memcpy(ks, key, len); - while (i < KEY_SCHEDULE_LEN) { + while (i < schedule_len) { temp = ks[i - 1]; - if ((i & 0x3) == 0) { + if ((i & (len_words - 1)) == 0) { temp = rot_word(temp); temp = sub_word(temp); - temp ^= (uint32_t)GF8mul(1, 1 << ((i >> 2) - 1)); + temp ^= (uint32_t)GF8mul(1, 1 << ((i / len_words) - 1)); } - ks[i] = ks[i - 4] ^ temp; + if (len == ROC_CPT_AES256_KEY_LEN) { + if ((i % len_words) == 4) + temp = sub_word(temp); + } + ks[i] = ks[i - len_words] ^ temp; i++; } } @@ -145,64 +154,83 @@ mix_columns(uint8_t *sRc) } static void -cipher(uint8_t *in, uint8_t *out, uint32_t *ks) +cipher(uint8_t *in, uint8_t *out, uint32_t *ks, uint32_t key_rounds, uint8_t in_len) { - uint32_t state[KEY_WORD_LEN]; + uint8_t data_word_len = in_len / sizeof(uint32_t); + uint32_t state[data_word_len]; unsigned int i, round; memcpy(state, in, sizeof(state)); /* AddRoundKey(state, w[0, Nb-1]) // See Sec. 5.1.4 */ - for (i = 0; i < KEY_WORD_LEN; i++) + for (i = 0; i < data_word_len; i++) state[i] ^= ks[i]; - for (round = 1; round < KEY_ROUNDS; round++) { + for (round = 1; round < key_rounds; round++) { /* SubBytes(state) // See Sec. 5.1.1 */ - for (i = 0; i < KEY_WORD_LEN; i++) + for (i = 0; i < data_word_len; i++) state[i] = sub_word(state[i]); /* ShiftRows(state) // See Sec. 5.1.2 */ - for (i = 0; i < KEY_WORD_LEN; i++) + for (i = 0; i < data_word_len; i++) shift_word((uint8_t *)state, i, i); /* MixColumns(state) // See Sec. 5.1.3 */ - for (i = 0; i < KEY_WORD_LEN; i++) + for (i = 0; i < data_word_len; i++) mix_columns((uint8_t *)&state[i]); /* AddRoundKey(state, w[round*Nb, (round+1)*Nb-1]) */ - for (i = 0; i < KEY_WORD_LEN; i++) - state[i] ^= ks[round * 4 + i]; + for (i = 0; i < data_word_len; i++) + state[i] ^= ks[round * data_word_len + i]; } /* SubBytes(state) */ - for (i = 0; i < KEY_WORD_LEN; i++) + for (i = 0; i < data_word_len; i++) state[i] = sub_word(state[i]); /* ShiftRows(state) */ - for (i = 0; i < KEY_WORD_LEN; i++) + for (i = 0; i < data_word_len; i++) shift_word((uint8_t *)state, i, i); /* AddRoundKey(state, w[Nr*Nb, (Nr+1)*Nb-1]) */ - for (i = 0; i < KEY_WORD_LEN; i++) - state[i] ^= ks[KEY_ROUNDS * 4 + i]; - memcpy(out, state, KEY_WORD_LEN * sizeof(uint32_t)); + for (i = 0; i < data_word_len; i++) + state[i] ^= ks[key_rounds * data_word_len + i]; + memcpy(out, state, data_word_len * sizeof(uint32_t)); } void roc_aes_xcbc_key_derive(const uint8_t *auth_key, uint8_t *derived_key) { - uint32_t aes_ks[KEY_SCHEDULE_LEN] = {0}; + uint32_t aes_ks[KEY_SCHEDULE_LEN(KEY128_ROUNDS)] = {0}; uint8_t k1[16] = {[0 ... 15] = 0x01}; uint8_t k2[16] = {[0 ... 15] = 0x02}; uint8_t k3[16] = {[0 ... 15] = 0x03}; - aes_key_expand(auth_key, aes_ks); + aes_key_expand(auth_key, ROC_CPT_AES_XCBC_KEY_LENGTH, aes_ks); - cipher(k1, derived_key, aes_ks); + cipher(k1, derived_key, aes_ks, KEY128_ROUNDS, sizeof(k1)); derived_key += sizeof(k1); - cipher(k2, derived_key, aes_ks); + cipher(k2, derived_key, aes_ks, KEY128_ROUNDS, sizeof(k2)); derived_key += sizeof(k2); - cipher(k3, derived_key, aes_ks); + cipher(k3, derived_key, aes_ks, KEY128_ROUNDS, sizeof(k3)); +} + +void +roc_aes_hash_key_derive(const uint8_t *key, uint16_t len, uint8_t hash_key[]) +{ + uint8_t data[AES_HASH_KEY_LEN] = {0x0}; + + if (len == ROC_CPT_AES128_KEY_LEN) { + uint32_t aes_ks[KEY_SCHEDULE_LEN(KEY128_ROUNDS)] = {0}; + + aes_key_expand(key, ROC_CPT_AES128_KEY_LEN, aes_ks); + cipher(data, hash_key, aes_ks, KEY128_ROUNDS, sizeof(data)); + } else { + uint32_t aes_ks[KEY_SCHEDULE_LEN(KEY256_ROUNDS)] = {0}; + + aes_key_expand(key, ROC_CPT_AES256_KEY_LEN, aes_ks); + cipher(data, hash_key, aes_ks, KEY256_ROUNDS, sizeof(data)); + } } diff --git a/drivers/common/cnxk/roc_aes.h b/drivers/common/cnxk/roc_aes.h index 954039139f..3b4b921bcd 100644 --- a/drivers/common/cnxk/roc_aes.h +++ b/drivers/common/cnxk/roc_aes.h @@ -8,7 +8,7 @@ /* * Derive k1, k2, k3 from 128 bit AES key */ -void __roc_api roc_aes_xcbc_key_derive(const uint8_t *auth_key, - uint8_t *derived_key); +void __roc_api roc_aes_xcbc_key_derive(const uint8_t *auth_key, uint8_t *derived_key); +void __roc_api roc_aes_hash_key_derive(const uint8_t *key, uint16_t len, uint8_t *hash_key); #endif /* _ROC_AES_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 914d0d2caa..8c71497df8 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -30,6 +30,7 @@ INTERNAL { roc_ae_ec_grp_put; roc_ae_fpm_get; roc_ae_fpm_put; + roc_aes_hash_key_derive; roc_aes_xcbc_key_derive; roc_bphy_cgx_cpri_mode_change; roc_bphy_cgx_cpri_mode_misc; From patchwork Wed Jun 7 15:28:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128350 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9E58542C4E; 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Wed, 07 Jun 2023 08:29:01 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 7 Jun 2023 08:28:59 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:28:59 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 315933F708E; Wed, 7 Jun 2023 08:28:56 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 12/15] net/cnxk: add MACsec initialization Date: Wed, 7 Jun 2023 20:58:16 +0530 Message-ID: <20230607152819.226838-13-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: fSjzZxJw5bmKckm29kfgtBJni_JvaPZG X-Proofpoint-GUID: fSjzZxJw5bmKckm29kfgtBJni_JvaPZG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added initialization routines for MACsec for cn10kb platform. Signed-off-by: Akhil Goyal --- drivers/net/cnxk/cn10k_ethdev_sec.c | 6 ++ drivers/net/cnxk/cnxk_ethdev.c | 13 +++ drivers/net/cnxk/cnxk_ethdev.h | 14 +++ drivers/net/cnxk/cnxk_ethdev_mcs.c | 151 ++++++++++++++++++++++++++++ drivers/net/cnxk/cnxk_ethdev_mcs.h | 61 +++++++++++ drivers/net/cnxk/meson.build | 1 + 6 files changed, 246 insertions(+) create mode 100644 drivers/net/cnxk/cnxk_ethdev_mcs.c create mode 100644 drivers/net/cnxk/cnxk_ethdev_mcs.h diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 5bc547051d..8dd2c8b7a5 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -1090,9 +1090,15 @@ cn10k_eth_sec_ops_override(void) init_once = 1; /* Update platform specific ops */ + cnxk_eth_sec_ops.macsec_sa_create = NULL; + cnxk_eth_sec_ops.macsec_sc_create = NULL; + cnxk_eth_sec_ops.macsec_sa_destroy = NULL; + cnxk_eth_sec_ops.macsec_sc_destroy = NULL; cnxk_eth_sec_ops.session_create = cn10k_eth_sec_session_create; cnxk_eth_sec_ops.session_destroy = cn10k_eth_sec_session_destroy; cnxk_eth_sec_ops.capabilities_get = cn10k_eth_sec_capabilities_get; cnxk_eth_sec_ops.session_update = cn10k_eth_sec_session_update; cnxk_eth_sec_ops.session_stats_get = cn10k_eth_sec_session_stats_get; + cnxk_eth_sec_ops.macsec_sc_stats_get = NULL; + cnxk_eth_sec_ops.macsec_sa_stats_get = NULL; } diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 916198d802..5368f0777d 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1961,6 +1961,16 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev) if (rc) goto free_mac_addrs; + if (roc_feature_nix_has_macsec()) { + rc = cnxk_mcs_dev_init(dev, 0); + if (rc) { + plt_err("Failed to init MCS"); + goto free_mac_addrs; + } + dev->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_MACSEC_STRIP; + dev->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_MACSEC_INSERT; + } + plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64, eth_dev->data->port_id, roc_nix_get_pf(nix), @@ -2058,6 +2068,9 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset) } eth_dev->data->nb_rx_queues = 0; + if (roc_feature_nix_has_macsec()) + cnxk_mcs_dev_fini(dev); + /* Free security resources */ nix_security_release(dev); diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index e280d6c05e..d5bb06b823 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -395,6 +395,9 @@ struct cnxk_eth_dev { /* Reassembly dynfield/flag offsets */ int reass_dynfield_off; int reass_dynflag_bit; + + /* MCS device */ + struct cnxk_mcs_dev *mcs_dev; }; struct cnxk_eth_rxq_sp { @@ -623,6 +626,17 @@ int cnxk_nix_cman_config_set(struct rte_eth_dev *dev, const struct rte_eth_cman_ int cnxk_nix_cman_config_get(struct rte_eth_dev *dev, struct rte_eth_cman_config *config); +int cnxk_mcs_dev_init(struct cnxk_eth_dev *dev, uint8_t mcs_idx); +void cnxk_mcs_dev_fini(struct cnxk_eth_dev *dev); + +struct cnxk_macsec_sess *cnxk_eth_macsec_sess_get_by_sess(struct cnxk_eth_dev *dev, + const struct rte_security_session *sess); +int cnxk_mcs_flow_configure(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], struct rte_flow_error *error, + void **mcs_flow); +int cnxk_mcs_flow_destroy(struct cnxk_eth_dev *eth_dev, void *mcs_flow); + /* Other private functions */ int nix_recalc_mtu(struct rte_eth_dev *eth_dev); int nix_mtr_validate(struct rte_eth_dev *dev, uint32_t id); diff --git a/drivers/net/cnxk/cnxk_ethdev_mcs.c b/drivers/net/cnxk/cnxk_ethdev_mcs.c new file mode 100644 index 0000000000..b0205f45c5 --- /dev/null +++ b/drivers/net/cnxk/cnxk_ethdev_mcs.c @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2023 Marvell. + */ + +#include +#include +#include + +static int +cnxk_mcs_event_cb(void *userdata, struct roc_mcs_event_desc *desc, void *cb_arg) +{ + struct rte_eth_event_macsec_desc d = {0}; + + d.metadata = (uint64_t)userdata; + + switch (desc->type) { + case ROC_MCS_EVENT_SECTAG_VAL_ERR: + d.type = RTE_ETH_EVENT_MACSEC_SECTAG_VAL_ERR; + switch (desc->subtype) { + case ROC_MCS_EVENT_RX_SECTAG_V_EQ1: + d.subtype = RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_V_EQ1; + break; + case ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1: + d.subtype = RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_E_EQ0_C_EQ1; + break; + case ROC_MCS_EVENT_RX_SECTAG_SL_GTE48: + d.subtype = RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_SL_GTE48; + break; + case ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1: + d.subtype = RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_ES_EQ1_SC_EQ1; + break; + case ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1: + d.subtype = RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_SC_EQ1_SCB_EQ1; + break; + default: + plt_err("Unknown MACsec sub event : %d", desc->subtype); + } + break; + case ROC_MCS_EVENT_RX_SA_PN_HARD_EXP: + d.type = RTE_ETH_EVENT_MACSEC_RX_SA_PN_HARD_EXP; + break; + case ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP: + d.type = RTE_ETH_EVENT_MACSEC_RX_SA_PN_SOFT_EXP; + break; + case ROC_MCS_EVENT_TX_SA_PN_HARD_EXP: + d.type = RTE_ETH_EVENT_MACSEC_TX_SA_PN_HARD_EXP; + break; + case ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP: + d.type = RTE_ETH_EVENT_MACSEC_TX_SA_PN_SOFT_EXP; + break; + default: + plt_err("Unknown MACsec event type: %d", desc->type); + } + + rte_eth_dev_callback_process(cb_arg, RTE_ETH_EVENT_MACSEC, &d); + + return 0; +} + +void +cnxk_mcs_dev_fini(struct cnxk_eth_dev *dev) +{ + struct cnxk_mcs_dev *mcs_dev = dev->mcs_dev; + int rc; + + rc = roc_mcs_event_cb_unregister(mcs_dev->mdev, ROC_MCS_EVENT_SECTAG_VAL_ERR); + if (rc) + plt_err("Failed to unregister MCS event callback: rc: %d", rc); + + rc = roc_mcs_event_cb_unregister(mcs_dev->mdev, ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP); + if (rc) + plt_err("Failed to unregister MCS event callback: rc: %d", rc); + + rc = roc_mcs_event_cb_unregister(mcs_dev->mdev, ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP); + if (rc) + plt_err("Failed to unregister MCS event callback: rc: %d", rc); + + /* Cleanup MACsec dev */ + roc_mcs_dev_fini(mcs_dev->mdev); + + plt_free(mcs_dev); +} + +int +cnxk_mcs_dev_init(struct cnxk_eth_dev *dev, uint8_t mcs_idx) +{ + struct roc_mcs_intr_cfg intr_cfg = {0}; + struct roc_mcs_hw_info hw_info = {0}; + struct cnxk_mcs_dev *mcs_dev; + int rc; + + rc = roc_mcs_hw_info_get(&hw_info); + if (rc) { + plt_err("MCS HW info get failed: rc: %d ", rc); + return rc; + } + + mcs_dev = plt_zmalloc(sizeof(struct cnxk_mcs_dev), PLT_CACHE_LINE_SIZE); + if (!mcs_dev) + return -ENOMEM; + + mcs_dev->idx = mcs_idx; + mcs_dev->mdev = roc_mcs_dev_init(mcs_dev->idx); + if (!mcs_dev->mdev) { + plt_free(mcs_dev); + return rc; + } + mcs_dev->port_id = dev->eth_dev->data->port_id; + + intr_cfg.intr_mask = + ROC_MCS_CPM_RX_SECTAG_V_EQ1_INT | ROC_MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT | + ROC_MCS_CPM_RX_SECTAG_SL_GTE48_INT | ROC_MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT | + ROC_MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT | ROC_MCS_CPM_RX_PACKET_XPN_EQ0_INT | + ROC_MCS_CPM_RX_PN_THRESH_REACHED_INT | ROC_MCS_CPM_TX_PACKET_XPN_EQ0_INT | + ROC_MCS_CPM_TX_PN_THRESH_REACHED_INT | ROC_MCS_CPM_TX_SA_NOT_VALID_INT | + ROC_MCS_BBE_RX_DFIFO_OVERFLOW_INT | ROC_MCS_BBE_RX_PLFIFO_OVERFLOW_INT | + ROC_MCS_BBE_TX_DFIFO_OVERFLOW_INT | ROC_MCS_BBE_TX_PLFIFO_OVERFLOW_INT | + ROC_MCS_PAB_RX_CHAN_OVERFLOW_INT | ROC_MCS_PAB_TX_CHAN_OVERFLOW_INT; + + rc = roc_mcs_intr_configure(mcs_dev->mdev, &intr_cfg); + if (rc) { + plt_err("Failed to configure MCS interrupts: rc: %d", rc); + plt_free(mcs_dev); + return rc; + } + + rc = roc_mcs_event_cb_register(mcs_dev->mdev, ROC_MCS_EVENT_SECTAG_VAL_ERR, + cnxk_mcs_event_cb, dev->eth_dev, mcs_dev); + if (rc) { + plt_err("Failed to register MCS event callback: rc: %d", rc); + plt_free(mcs_dev); + return rc; + } + rc = roc_mcs_event_cb_register(mcs_dev->mdev, ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP, + cnxk_mcs_event_cb, dev->eth_dev, mcs_dev); + if (rc) { + plt_err("Failed to register MCS event callback: rc: %d", rc); + plt_free(mcs_dev); + return rc; + } + rc = roc_mcs_event_cb_register(mcs_dev->mdev, ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP, + cnxk_mcs_event_cb, dev->eth_dev, mcs_dev); + if (rc) { + plt_err("Failed to register MCS event callback: rc: %d", rc); + plt_free(mcs_dev); + return rc; + } + dev->mcs_dev = mcs_dev; + + return 0; +} diff --git a/drivers/net/cnxk/cnxk_ethdev_mcs.h b/drivers/net/cnxk/cnxk_ethdev_mcs.h new file mode 100644 index 0000000000..762c299fb8 --- /dev/null +++ b/drivers/net/cnxk/cnxk_ethdev_mcs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2023 Marvell. + */ + +#include + +#define CNXK_MACSEC_HASH_KEY 16 + +struct cnxk_mcs_dev { + uint64_t default_sci; + void *mdev; + uint8_t port_id; + uint8_t idx; +}; + +struct cnxk_mcs_event_data { + /* Valid for below events + * - ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP + * - ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP + */ + struct { + uint8_t secy_idx; + uint8_t sc_idx; + uint8_t sa_idx; + }; + /* Valid for below event + * - ROC_MCS_EVENT_FIFO_OVERFLOW + * + * Upon fatal error notification on a MCS port, driver resets below attributes of active + * flow entities(sc & sa) and then resets the port. + * - Reset NEXT_PN of active SAs to 1. + * - Reset TX active SA for each SC, TX_SA_ACTIVE = 0, SA_INDEX0_VLD = 1. + * - Clear SA_IN_USE for active ANs in RX_SA_MAP_MEM. + * - Clear all stats mapping to this port. + * - Reactivate SA_IN_USE for active ANs in RX_SA_MAP_MEM. + * + * UMD driver notifies the following flow entity(sc & sa) details in application callback, + * application is expected to exchange the Tx/Rx NEXT_PN, TX_SA_ACTIVE, active RX SC AN + * details with peer device so that peer device can resets it's MACsec flow states and than + * resume packet transfers. + */ + struct { + uint16_t *tx_sa_array; /* Tx SAs whose PN memories were reset (NEXT_PN=1) */ + uint16_t *rx_sa_array; /* Rx SAs whose PN memories were reset (NEXT_PN=1) */ + uint16_t *tx_sc_array; /* Tx SCs whose active SAs were reset (TX_SA_ACTIVE=0) */ + uint16_t *rx_sc_array; /* Rx SCs whose state was reset */ + uint8_t *sc_an_array; /* AN of Rx SCs(in rx_sc_array) which were reactivated */ + uint8_t num_tx_sa; /* num entries in tx_sa_array */ + uint8_t num_rx_sa; /* num entries in rx_sa_array */ + uint8_t num_tx_sc; /* num entries in tx_sc_array */ + uint8_t num_rx_sc; /* num entries in rx_sc_array */ + uint8_t lmac_id; /* lmac_id/port which was recovered from fatal error */ + }; +}; + +struct cnxk_mcs_event_desc { + struct rte_eth_dev *eth_dev; + enum roc_mcs_event_type type; + enum roc_mcs_event_subtype subtype; + struct cnxk_mcs_event_data metadata; +}; diff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build index 62b8bb90fb..ae6a7d9aac 100644 --- a/drivers/net/cnxk/meson.build +++ b/drivers/net/cnxk/meson.build @@ -22,6 +22,7 @@ sources = files( 'cnxk_ethdev.c', 'cnxk_ethdev_cman.c', 'cnxk_ethdev_devargs.c', + 'cnxk_ethdev_mcs.c', 'cnxk_ethdev_mtr.c', 'cnxk_ethdev_ops.c', 'cnxk_ethdev_sec.c', From patchwork Wed Jun 7 15:28:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128351 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D444442C4E; Wed, 7 Jun 2023 17:29:58 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 88D8F42D0C; Wed, 7 Jun 2023 17:29:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B5E3442DBA for ; Wed, 7 Jun 2023 17:29:05 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 357Dvh25028122; Wed, 7 Jun 2023 08:29:05 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; 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Wed, 7 Jun 2023 08:28:59 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 13/15] net/cnxk: create/destroy MACsec SC/SA Date: Wed, 7 Jun 2023 20:58:17 +0530 Message-ID: <20230607152819.226838-14-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: KXvxD96CuR8oS8epd1ZR-P6R919uETMq X-Proofpoint-GUID: KXvxD96CuR8oS8epd1ZR-P6R919uETMq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added support to create/destroy MACsec SA and SC. Signed-off-by: Akhil Goyal --- drivers/net/cnxk/cn10k_ethdev_sec.c | 9 +- drivers/net/cnxk/cnxk_ethdev_mcs.c | 250 ++++++++++++++++++++++++++++ drivers/net/cnxk/cnxk_ethdev_mcs.h | 16 ++ 3 files changed, 271 insertions(+), 4 deletions(-) diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 8dd2c8b7a5..1db29a0b55 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -9,6 +9,7 @@ #include #include +#include #include #include @@ -1090,10 +1091,10 @@ cn10k_eth_sec_ops_override(void) init_once = 1; /* Update platform specific ops */ - cnxk_eth_sec_ops.macsec_sa_create = NULL; - cnxk_eth_sec_ops.macsec_sc_create = NULL; - cnxk_eth_sec_ops.macsec_sa_destroy = NULL; - cnxk_eth_sec_ops.macsec_sc_destroy = NULL; + cnxk_eth_sec_ops.macsec_sa_create = cnxk_eth_macsec_sa_create; + cnxk_eth_sec_ops.macsec_sc_create = cnxk_eth_macsec_sc_create; + cnxk_eth_sec_ops.macsec_sa_destroy = cnxk_eth_macsec_sa_destroy; + cnxk_eth_sec_ops.macsec_sc_destroy = cnxk_eth_macsec_sc_destroy; cnxk_eth_sec_ops.session_create = cn10k_eth_sec_session_create; cnxk_eth_sec_ops.session_destroy = cn10k_eth_sec_session_destroy; cnxk_eth_sec_ops.capabilities_get = cn10k_eth_sec_capabilities_get; diff --git a/drivers/net/cnxk/cnxk_ethdev_mcs.c b/drivers/net/cnxk/cnxk_ethdev_mcs.c index b0205f45c5..89876abc57 100644 --- a/drivers/net/cnxk/cnxk_ethdev_mcs.c +++ b/drivers/net/cnxk/cnxk_ethdev_mcs.c @@ -6,6 +6,256 @@ #include #include +static int +mcs_resource_alloc(struct cnxk_mcs_dev *mcs_dev, enum mcs_direction dir, uint8_t rsrc_id[], + uint8_t rsrc_cnt, enum cnxk_mcs_rsrc_type type) +{ + struct roc_mcs_alloc_rsrc_req req = {0}; + struct roc_mcs_alloc_rsrc_rsp rsp = {0}; + int i; + + req.rsrc_type = type; + req.rsrc_cnt = rsrc_cnt; + req.dir = dir; + + if (roc_mcs_rsrc_alloc(mcs_dev->mdev, &req, &rsp)) { + plt_err("Cannot allocate mcs resource."); + return -1; + } + + for (i = 0; i < rsrc_cnt; i++) { + switch (rsp.rsrc_type) { + case CNXK_MCS_RSRC_TYPE_FLOWID: + rsrc_id[i] = rsp.flow_ids[i]; + break; + case CNXK_MCS_RSRC_TYPE_SECY: + rsrc_id[i] = rsp.secy_ids[i]; + break; + case CNXK_MCS_RSRC_TYPE_SC: + rsrc_id[i] = rsp.sc_ids[i]; + break; + case CNXK_MCS_RSRC_TYPE_SA: + rsrc_id[i] = rsp.sa_ids[i]; + break; + default: + plt_err("Invalid mcs resource allocated."); + return -1; + } + } + return 0; +} + +int +cnxk_eth_macsec_sa_create(void *device, struct rte_security_macsec_sa *conf) +{ + struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + uint8_t salt[RTE_SECURITY_MACSEC_SALT_LEN] = {0}; + struct roc_mcs_pn_table_write_req pn_req = {0}; + uint8_t hash_key_rev[CNXK_MACSEC_HASH_KEY] = {0}; + uint8_t hash_key[CNXK_MACSEC_HASH_KEY] = {0}; + struct cnxk_mcs_dev *mcs_dev = dev->mcs_dev; + struct roc_mcs_sa_plcy_write_req req = {0}; + uint8_t ciph_key[32] = {0}; + enum mcs_direction dir; + uint8_t sa_id = 0; + int i, ret = 0; + + if (!roc_feature_nix_has_macsec()) + return -ENOTSUP; + + dir = (conf->dir == RTE_SECURITY_MACSEC_DIR_TX) ? MCS_TX : MCS_RX; + ret = mcs_resource_alloc(mcs_dev, dir, &sa_id, 1, CNXK_MCS_RSRC_TYPE_SA); + if (ret) { + plt_err("Failed to allocate SA id."); + return -ENOMEM; + } + req.sa_index[0] = sa_id; + req.sa_cnt = 1; + req.dir = dir; + + if (conf->key.length != 16 && conf->key.length != 32) + return -EINVAL; + + for (i = 0; i < conf->key.length; i++) + ciph_key[i] = conf->key.data[conf->key.length - 1 - i]; + + memcpy(&req.plcy[0][0], ciph_key, conf->key.length); + + roc_aes_hash_key_derive(conf->key.data, conf->key.length, hash_key); + for (i = 0; i < CNXK_MACSEC_HASH_KEY; i++) + hash_key_rev[i] = hash_key[CNXK_MACSEC_HASH_KEY - 1 - i]; + + memcpy(&req.plcy[0][4], hash_key_rev, CNXK_MACSEC_HASH_KEY); + + for (i = 0; i < RTE_SECURITY_MACSEC_SALT_LEN; i++) + salt[i] = conf->salt[RTE_SECURITY_MACSEC_SALT_LEN - 1 - i]; + memcpy(&req.plcy[0][6], salt, RTE_SECURITY_MACSEC_SALT_LEN); + + req.plcy[0][7] |= (uint64_t)conf->ssci << 32; + req.plcy[0][8] = (conf->dir == RTE_SECURITY_MACSEC_DIR_TX) ? (conf->an & 0x3) : 0; + + ret = roc_mcs_sa_policy_write(mcs_dev->mdev, &req); + if (ret) { + plt_err("Failed to write SA policy."); + return -EINVAL; + } + pn_req.next_pn = ((uint64_t)conf->xpn << 32) | rte_be_to_cpu_32(conf->next_pn); + pn_req.pn_id = sa_id; + pn_req.dir = dir; + + ret = roc_mcs_pn_table_write(mcs_dev->mdev, &pn_req); + if (ret) { + plt_err("Failed to write PN table."); + return -EINVAL; + } + + return sa_id; +} + +int +cnxk_eth_macsec_sa_destroy(void *device, uint16_t sa_id, enum rte_security_macsec_direction dir) +{ + struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_mcs_dev *mcs_dev = dev->mcs_dev; + struct roc_mcs_clear_stats stats_req = {0}; + struct roc_mcs_free_rsrc_req req = {0}; + int ret = 0; + + if (!roc_feature_nix_has_macsec()) + return -ENOTSUP; + + stats_req.type = CNXK_MCS_RSRC_TYPE_SA; + stats_req.id = sa_id; + stats_req.dir = (dir == RTE_SECURITY_MACSEC_DIR_TX) ? MCS_TX : MCS_RX; + stats_req.all = 0; + + ret = roc_mcs_stats_clear(mcs_dev->mdev, &stats_req); + if (ret) + plt_err("Failed to clear stats for SA id %u, dir %u.", sa_id, dir); + + req.rsrc_id = sa_id; + req.dir = (dir == RTE_SECURITY_MACSEC_DIR_TX) ? MCS_TX : MCS_RX; + req.rsrc_type = CNXK_MCS_RSRC_TYPE_SA; + + ret = roc_mcs_rsrc_free(mcs_dev->mdev, &req); + if (ret) + plt_err("Failed to free SA id %u, dir %u.", sa_id, dir); + + return ret; +} + +int +cnxk_eth_macsec_sc_create(void *device, struct rte_security_macsec_sc *conf) +{ + struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_mcs_set_pn_threshold pn_thresh = {0}; + struct cnxk_mcs_dev *mcs_dev = dev->mcs_dev; + enum mcs_direction dir; + uint8_t sc_id = 0; + int i, ret = 0; + + if (!roc_feature_nix_has_macsec()) + return -ENOTSUP; + + dir = (conf->dir == RTE_SECURITY_MACSEC_DIR_TX) ? MCS_TX : MCS_RX; + ret = mcs_resource_alloc(mcs_dev, dir, &sc_id, 1, CNXK_MCS_RSRC_TYPE_SC); + if (ret) { + plt_err("Failed to allocate SC id."); + return -ENOMEM; + } + + if (conf->dir == RTE_SECURITY_MACSEC_DIR_TX) { + struct roc_mcs_tx_sc_sa_map req = {0}; + + req.sa_index0 = conf->sc_tx.sa_id & 0xFF; + req.sa_index1 = conf->sc_tx.sa_id_rekey & 0xFF; + req.rekey_ena = conf->sc_tx.re_key_en; + req.sa_index0_vld = conf->sc_tx.active; + req.sa_index1_vld = conf->sc_tx.re_key_en && conf->sc_tx.active; + req.tx_sa_active = 0; + req.sectag_sci = conf->sc_tx.sci; + req.sc_id = sc_id; + + ret = roc_mcs_tx_sc_sa_map_write(mcs_dev->mdev, &req); + if (ret) { + plt_err("Failed to map TX SC-SA"); + return -EINVAL; + } + pn_thresh.xpn = conf->sc_tx.is_xpn; + } else { + for (i = 0; i < RTE_SECURITY_MACSEC_NUM_AN; i++) { + struct roc_mcs_rx_sc_sa_map req = {0}; + + req.sa_index = conf->sc_rx.sa_id[i] & 0x7F; + req.sc_id = sc_id; + req.an = i & 0x3; + req.sa_in_use = 0; + /* Clearing the sa_in_use bit automatically clears + * the corresponding pn_thresh_reached bit + */ + ret = roc_mcs_rx_sc_sa_map_write(mcs_dev->mdev, &req); + if (ret) { + plt_err("Failed to map RX SC-SA"); + return -EINVAL; + } + req.sa_in_use = conf->sc_rx.sa_in_use[i]; + ret = roc_mcs_rx_sc_sa_map_write(mcs_dev->mdev, &req); + if (ret) { + plt_err("Failed to map RX SC-SA"); + return -EINVAL; + } + } + pn_thresh.xpn = conf->sc_rx.is_xpn; + } + + pn_thresh.threshold = conf->pn_threshold; + pn_thresh.dir = dir; + + ret = roc_mcs_pn_threshold_set(mcs_dev->mdev, &pn_thresh); + if (ret) { + plt_err("Failed to write PN threshold."); + return -EINVAL; + } + + return sc_id; +} + +int +cnxk_eth_macsec_sc_destroy(void *device, uint16_t sc_id, enum rte_security_macsec_direction dir) +{ + struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_mcs_dev *mcs_dev = dev->mcs_dev; + struct roc_mcs_clear_stats stats_req = {0}; + struct roc_mcs_free_rsrc_req req = {0}; + int ret = 0; + + if (!roc_feature_nix_has_macsec()) + return -ENOTSUP; + + stats_req.type = CNXK_MCS_RSRC_TYPE_SC; + stats_req.id = sc_id; + stats_req.dir = (dir == RTE_SECURITY_MACSEC_DIR_TX) ? MCS_TX : MCS_RX; + stats_req.all = 0; + + ret = roc_mcs_stats_clear(mcs_dev->mdev, &stats_req); + if (ret) + plt_err("Failed to clear stats for SC id %u, dir %u.", sc_id, dir); + + req.rsrc_id = sc_id; + req.dir = (dir == RTE_SECURITY_MACSEC_DIR_TX) ? MCS_TX : MCS_RX; + req.rsrc_type = CNXK_MCS_RSRC_TYPE_SC; + + ret = roc_mcs_rsrc_free(mcs_dev->mdev, &req); + if (ret) + plt_err("Failed to free SC id."); + + return ret; +} + static int cnxk_mcs_event_cb(void *userdata, struct roc_mcs_event_desc *desc, void *cb_arg) { diff --git a/drivers/net/cnxk/cnxk_ethdev_mcs.h b/drivers/net/cnxk/cnxk_ethdev_mcs.h index 762c299fb8..68c6493169 100644 --- a/drivers/net/cnxk/cnxk_ethdev_mcs.h +++ b/drivers/net/cnxk/cnxk_ethdev_mcs.h @@ -13,6 +13,14 @@ struct cnxk_mcs_dev { uint8_t idx; }; +enum cnxk_mcs_rsrc_type { + CNXK_MCS_RSRC_TYPE_FLOWID, + CNXK_MCS_RSRC_TYPE_SECY, + CNXK_MCS_RSRC_TYPE_SC, + CNXK_MCS_RSRC_TYPE_SA, + CNXK_MCS_RSRC_TYPE_PORT, +}; + struct cnxk_mcs_event_data { /* Valid for below events * - ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP @@ -59,3 +67,11 @@ struct cnxk_mcs_event_desc { enum roc_mcs_event_subtype subtype; struct cnxk_mcs_event_data metadata; }; + +int cnxk_eth_macsec_sa_create(void *device, struct rte_security_macsec_sa *conf); +int cnxk_eth_macsec_sc_create(void *device, struct rte_security_macsec_sc *conf); + +int cnxk_eth_macsec_sa_destroy(void *device, uint16_t sa_id, + enum rte_security_macsec_direction dir); +int cnxk_eth_macsec_sc_destroy(void *device, uint16_t sc_id, + enum rte_security_macsec_direction dir); From patchwork Wed Jun 7 15:28:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128352 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3190842C50; Wed, 7 Jun 2023 17:30:04 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B446F42DA9; Wed, 7 Jun 2023 17:29:10 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 41F3C42DBA for ; Wed, 7 Jun 2023 17:29:08 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 357Dvl07028208; Wed, 7 Jun 2023 08:29:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=nsiN3ubLSiUShYasIGO6vJhWI8x02UDNYN+aJ2TnIZ4=; b=hegPFRVvH/pa/cOi/WqgSUakZ9UfI8Gin+BKwC+kRpR/D1WhRU0QtzV/pRdQLXOIfgjV c2WTvXxeNGTNeZNA0SO0C7pq5byuYBUUClIOODoVON5fnR07pqUTN0Itz/DU3lPaNB8u v7v+xihxu6z2H70e+Fp8gW8ZkPwgoCy1cMwgn2gSHRX5NrU9IaQEmcKexRCNBgOI77dj ERretTs7Ze24r7Etsbg6Na8yRCcmXWktg7KDcszi1Rq3XSRZQOZbRHF5MiQ7BoecPiPg jky1hYJ9Pg3AndI2VpA5ImfGcjObXgP1MJ2wjOPRE4ZRICm0fte5UheF4ojzBLuFHNeO MQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r2a7bv802-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 07 Jun 2023 08:29:07 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 7 Jun 2023 08:29:05 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:29:05 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 0DCC13F708F; Wed, 7 Jun 2023 08:29:02 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 14/15] net/cnxk: add MACsec session and flow configuration Date: Wed, 7 Jun 2023 20:58:18 +0530 Message-ID: <20230607152819.226838-15-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 5sY8uKb_8M0WKLnR7xou0rDzXDSXxQ-X X-Proofpoint-GUID: 5sY8uKb_8M0WKLnR7xou0rDzXDSXxQ-X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added support for MACsec session/flow create/destroy. Signed-off-by: Akhil Goyal --- drivers/net/cnxk/cn10k_ethdev_sec.c | 11 +- drivers/net/cnxk/cn10k_flow.c | 23 ++- drivers/net/cnxk/cnxk_ethdev.c | 2 + drivers/net/cnxk/cnxk_ethdev.h | 16 ++ drivers/net/cnxk/cnxk_ethdev_mcs.c | 261 ++++++++++++++++++++++++++++ drivers/net/cnxk/cnxk_ethdev_mcs.h | 25 +++ drivers/net/cnxk/cnxk_ethdev_sec.c | 2 +- drivers/net/cnxk/cnxk_flow.c | 5 + 8 files changed, 341 insertions(+), 4 deletions(-) diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 1db29a0b55..f20e573338 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -642,7 +642,9 @@ cn10k_eth_sec_session_create(void *device, if (conf->action_type != RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL) return -ENOTSUP; - if (conf->protocol != RTE_SECURITY_PROTOCOL_IPSEC) + if (conf->protocol == RTE_SECURITY_PROTOCOL_MACSEC) + return cnxk_eth_macsec_session_create(dev, conf, sess); + else if (conf->protocol != RTE_SECURITY_PROTOCOL_IPSEC) return -ENOTSUP; if (rte_security_dynfield_register() < 0) @@ -887,13 +889,18 @@ cn10k_eth_sec_session_destroy(void *device, struct rte_security_session *sess) { struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_macsec_sess *macsec_sess; struct cnxk_eth_sec_sess *eth_sec; rte_spinlock_t *lock; void *sa_dptr; eth_sec = cnxk_eth_sec_sess_get_by_sess(dev, sess); - if (!eth_sec) + if (!eth_sec) { + macsec_sess = cnxk_eth_macsec_sess_get_by_sess(dev, sess); + if (macsec_sess) + return cnxk_eth_macsec_session_destroy(dev, sess); return -ENOENT; + } lock = eth_sec->inb ? &dev->inb.lock : &dev->outb.lock; rte_spinlock_lock(lock); diff --git a/drivers/net/cnxk/cn10k_flow.c b/drivers/net/cnxk/cn10k_flow.c index d7a3442c5f..db5e427362 100644 --- a/drivers/net/cnxk/cn10k_flow.c +++ b/drivers/net/cnxk/cn10k_flow.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(C) 2020 Marvell. */ -#include #include "cn10k_flow.h" #include "cn10k_ethdev.h" #include "cn10k_rx.h" +#include "cnxk_ethdev_mcs.h" +#include static int cn10k_mtr_connect(struct rte_eth_dev *eth_dev, uint32_t mtr_id) @@ -133,6 +134,7 @@ cn10k_flow_create(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr, const struct rte_flow_action *act_q = NULL; struct roc_npc *npc = &dev->npc; struct roc_npc_flow *flow; + void *mcs_flow = NULL; int vtag_actions = 0; uint32_t req_act = 0; int mark_actions; @@ -187,6 +189,17 @@ cn10k_flow_create(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr, } } + if (actions[0].type == RTE_FLOW_ACTION_TYPE_SECURITY && + cnxk_eth_macsec_sess_get_by_sess(dev, actions[0].conf) != NULL) { + rc = cnxk_mcs_flow_configure(eth_dev, attr, pattern, actions, error, &mcs_flow); + if (rc) { + rte_flow_error_set(error, rc, RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "Failed to configure mcs flow"); + return NULL; + } + return (struct rte_flow *)mcs_flow; + } + flow = cnxk_flow_create(eth_dev, attr, pattern, actions, error); if (!flow) { if (mtr) @@ -265,6 +278,14 @@ cn10k_flow_destroy(struct rte_eth_dev *eth_dev, struct rte_flow *rte_flow, } } + if (cnxk_eth_macsec_sess_get_by_sess(dev, (void *)flow) != NULL) { + rc = cnxk_mcs_flow_destroy(dev, (void *)flow); + if (rc < 0) + rte_flow_error_set(error, rc, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, "Failed to free mcs flow"); + return rc; + } + mtr_id = flow->mtr_id; rc = cnxk_flow_destroy(eth_dev, flow, error); if (!rc && mtr_id != ROC_NIX_MTR_ID_INVALID) { diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 5368f0777d..4b98faa729 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1969,6 +1969,8 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev) } dev->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_MACSEC_STRIP; dev->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_MACSEC_INSERT; + + TAILQ_INIT(&dev->mcs_list); } plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64 diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index d5bb06b823..45dc72b609 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -292,6 +292,21 @@ struct cnxk_eth_dev_sec_outb { uint64_t cpt_eng_caps; }; +/* MACsec session private data */ +struct cnxk_macsec_sess { + /* List entry */ + TAILQ_ENTRY(cnxk_macsec_sess) entry; + + /* Back pointer to session */ + struct rte_security_session *sess; + enum mcs_direction dir; + uint64_t sci; + uint8_t secy_id; + uint8_t sc_id; + uint8_t flow_id; +}; +TAILQ_HEAD(cnxk_macsec_sess_list, cnxk_macsec_sess); + struct cnxk_eth_dev { /* ROC NIX */ struct roc_nix nix; @@ -398,6 +413,7 @@ struct cnxk_eth_dev { /* MCS device */ struct cnxk_mcs_dev *mcs_dev; + struct cnxk_macsec_sess_list mcs_list; }; struct cnxk_eth_rxq_sp { diff --git a/drivers/net/cnxk/cnxk_ethdev_mcs.c b/drivers/net/cnxk/cnxk_ethdev_mcs.c index 89876abc57..b47991e259 100644 --- a/drivers/net/cnxk/cnxk_ethdev_mcs.c +++ b/drivers/net/cnxk/cnxk_ethdev_mcs.c @@ -256,6 +256,267 @@ cnxk_eth_macsec_sc_destroy(void *device, uint16_t sc_id, enum rte_security_macse return ret; } +struct cnxk_macsec_sess * +cnxk_eth_macsec_sess_get_by_sess(struct cnxk_eth_dev *dev, const struct rte_security_session *sess) +{ + struct cnxk_macsec_sess *macsec_sess = NULL; + + TAILQ_FOREACH(macsec_sess, &dev->mcs_list, entry) { + if (macsec_sess->sess == sess) + return macsec_sess; + } + + return NULL; +} + +int +cnxk_eth_macsec_session_create(struct cnxk_eth_dev *dev, struct rte_security_session_conf *conf, + struct rte_security_session *sess) +{ + struct cnxk_macsec_sess *macsec_sess_priv = SECURITY_GET_SESS_PRIV(sess); + struct rte_security_macsec_xform *xform = &conf->macsec; + struct cnxk_mcs_dev *mcs_dev = dev->mcs_dev; + struct roc_mcs_secy_plcy_write_req req; + enum mcs_direction dir; + uint8_t secy_id = 0; + uint8_t sectag_tci = 0; + int ret = 0; + + if (!roc_feature_nix_has_macsec()) + return -ENOTSUP; + + dir = (xform->dir == RTE_SECURITY_MACSEC_DIR_TX) ? MCS_TX : MCS_RX; + ret = mcs_resource_alloc(mcs_dev, dir, &secy_id, 1, CNXK_MCS_RSRC_TYPE_SECY); + if (ret) { + plt_err("Failed to allocate SECY id."); + return -ENOMEM; + } + + req.secy_id = secy_id; + req.dir = dir; + req.plcy = 0L; + + if (xform->dir == RTE_SECURITY_MACSEC_DIR_TX) { + sectag_tci = ((uint8_t)xform->tx_secy.sectag_version << 5) | + ((uint8_t)xform->tx_secy.end_station << 4) | + ((uint8_t)xform->tx_secy.send_sci << 3) | + ((uint8_t)xform->tx_secy.scb << 2) | + ((uint8_t)xform->tx_secy.encrypt << 1) | + (uint8_t)xform->tx_secy.encrypt; + req.plcy = (((uint64_t)xform->tx_secy.mtu & 0xFFFF) << 28) | + (((uint64_t)sectag_tci & 0x3F) << 22) | + (((uint64_t)xform->tx_secy.sectag_off & 0x7F) << 15) | + ((uint64_t)xform->tx_secy.sectag_insert_mode << 14) | + ((uint64_t)xform->tx_secy.icv_include_da_sa << 13) | + (((uint64_t)xform->cipher_off & 0x7F) << 6) | + ((uint64_t)xform->alg << 2) | + ((uint64_t)xform->tx_secy.protect_frames << 1) | + (uint64_t)xform->tx_secy.ctrl_port_enable; + } else { + req.plcy = ((uint64_t)xform->rx_secy.replay_win_sz << 18) | + ((uint64_t)xform->rx_secy.replay_protect << 17) | + ((uint64_t)xform->rx_secy.icv_include_da_sa << 16) | + (((uint64_t)xform->cipher_off & 0x7F) << 9) | + ((uint64_t)xform->alg << 5) | + ((uint64_t)xform->rx_secy.preserve_sectag << 4) | + ((uint64_t)xform->rx_secy.preserve_icv << 3) | + ((uint64_t)xform->rx_secy.validate_frames << 1) | + (uint64_t)xform->rx_secy.ctrl_port_enable; + } + + ret = roc_mcs_secy_policy_write(mcs_dev->mdev, &req); + if (ret) { + plt_err(" Failed to configure Tx SECY"); + return -EINVAL; + } + + if (xform->dir == RTE_SECURITY_MACSEC_DIR_RX) { + struct roc_mcs_rx_sc_cam_write_req rx_sc_cam = {0}; + + rx_sc_cam.sci = xform->sci; + rx_sc_cam.secy_id = secy_id & 0x3F; + rx_sc_cam.sc_id = xform->sc_id; + ret = roc_mcs_rx_sc_cam_write(mcs_dev->mdev, &rx_sc_cam); + if (ret) { + plt_err(" Failed to write rx_sc_cam"); + return -EINVAL; + } + } + macsec_sess_priv->sci = xform->sci; + macsec_sess_priv->sc_id = xform->sc_id; + macsec_sess_priv->secy_id = secy_id; + macsec_sess_priv->dir = dir; + macsec_sess_priv->sess = sess; + + TAILQ_INSERT_TAIL(&dev->mcs_list, macsec_sess_priv, entry); + + return 0; +} + +int +cnxk_eth_macsec_session_destroy(struct cnxk_eth_dev *dev, struct rte_security_session *sess) +{ + struct cnxk_mcs_dev *mcs_dev = dev->mcs_dev; + struct roc_mcs_clear_stats stats_req = {0}; + struct roc_mcs_free_rsrc_req req = {0}; + struct cnxk_macsec_sess *s; + int ret = 0; + + if (!roc_feature_nix_has_macsec()) + return -ENOTSUP; + + s = SECURITY_GET_SESS_PRIV(sess); + + stats_req.type = CNXK_MCS_RSRC_TYPE_SECY; + stats_req.id = s->secy_id; + stats_req.dir = s->dir; + stats_req.all = 0; + + ret = roc_mcs_stats_clear(mcs_dev->mdev, &stats_req); + if (ret) + plt_err("Failed to clear stats for SECY id %u, dir %u.", s->secy_id, s->dir); + + req.rsrc_id = s->secy_id; + req.dir = s->dir; + req.rsrc_type = CNXK_MCS_RSRC_TYPE_SECY; + + ret = roc_mcs_rsrc_free(mcs_dev->mdev, &req); + if (ret) + plt_err("Failed to free SC id."); + + TAILQ_REMOVE(&dev->mcs_list, s, entry); + + return ret; +} + +int +cnxk_mcs_flow_configure(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr __rte_unused, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_flow_error *error __rte_unused, void **mcs_flow) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_mcs_flowid_entry_write_req req = {0}; + const struct rte_flow_item_eth *eth_item = NULL; + struct cnxk_mcs_dev *mcs_dev = dev->mcs_dev; + struct cnxk_mcs_flow_opts opts = {0}; + struct cnxk_macsec_sess *sess; + struct rte_ether_addr src; + struct rte_ether_addr dst; + int ret; + int i = 0; + + if (!roc_feature_nix_has_macsec()) + return -ENOTSUP; + + sess = cnxk_eth_macsec_sess_get_by_sess(dev, + (const struct rte_security_session *)actions->conf); + if (sess == NULL) + return -EINVAL; + + ret = mcs_resource_alloc(mcs_dev, sess->dir, &sess->flow_id, 1, + CNXK_MCS_RSRC_TYPE_FLOWID); + if (ret) { + plt_err("Failed to allocate FLow id."); + return -ENOMEM; + } + req.sci = sess->sci; + req.flow_id = sess->flow_id; + req.secy_id = sess->secy_id; + req.sc_id = sess->sc_id; + req.ena = 1; + req.ctr_pkt = 0; + req.dir = sess->dir; + + while (pattern[i].type != RTE_FLOW_ITEM_TYPE_END) { + if (pattern[i].type == RTE_FLOW_ITEM_TYPE_ETH) + eth_item = pattern[i].spec; + else + plt_err("Unhandled flow item : %d", pattern[i].type); + i++; + } + if (eth_item) { + dst = eth_item->hdr.dst_addr; + src = eth_item->hdr.src_addr; + + /* Find ways to fill opts */ + + req.data[0] = + (uint64_t)dst.addr_bytes[0] << 40 | (uint64_t)dst.addr_bytes[1] << 32 | + (uint64_t)dst.addr_bytes[2] << 24 | (uint64_t)dst.addr_bytes[3] << 16 | + (uint64_t)dst.addr_bytes[4] << 8 | (uint64_t)dst.addr_bytes[5] | + (uint64_t)src.addr_bytes[5] << 48 | (uint64_t)src.addr_bytes[4] << 56; + req.data[1] = (uint64_t)src.addr_bytes[3] | (uint64_t)src.addr_bytes[2] << 8 | + (uint64_t)src.addr_bytes[1] << 16 | + (uint64_t)src.addr_bytes[0] << 24 | + (uint64_t)eth_item->hdr.ether_type << 32 | + ((uint64_t)opts.outer_tag_id & 0xFFFF) << 48; + req.data[2] = ((uint64_t)opts.outer_tag_id & 0xF0000) | + ((uint64_t)opts.outer_priority & 0xF) << 4 | + ((uint64_t)opts.second_outer_tag_id & 0xFFFFF) << 8 | + ((uint64_t)opts.second_outer_priority & 0xF) << 28 | + ((uint64_t)opts.bonus_data << 32) | + ((uint64_t)opts.tag_match_bitmap << 48) | + ((uint64_t)opts.packet_type & 0xF) << 56 | + ((uint64_t)opts.outer_vlan_type & 0x7) << 60 | + ((uint64_t)opts.inner_vlan_type & 0x1) << 63; + req.data[3] = ((uint64_t)opts.inner_vlan_type & 0x6) >> 1 | + ((uint64_t)opts.num_tags & 0x7F) << 2 | + ((uint64_t)opts.flowid_user & 0x1F) << 9 | + ((uint64_t)opts.express & 1) << 14 | + ((uint64_t)opts.lmac_id & 0x1F) << 15; + + req.mask[0] = 0x0; + req.mask[1] = 0xFFFFFFFF00000000; + req.mask[2] = 0xFFFFFFFFFFFFFFFF; + req.mask[3] = 0xFFFFFFFFFFFFFFFF; + + ret = roc_mcs_flowid_entry_write(mcs_dev->mdev, &req); + if (ret) + return ret; + *mcs_flow = (void *)(uintptr_t)actions->conf; + } else { + plt_err("Flow not confirured"); + return -EINVAL; + } + return 0; +} + +int +cnxk_mcs_flow_destroy(struct cnxk_eth_dev *dev, void *flow) +{ + const struct cnxk_macsec_sess *s = cnxk_eth_macsec_sess_get_by_sess(dev, flow); + struct cnxk_mcs_dev *mcs_dev = dev->mcs_dev; + struct roc_mcs_clear_stats stats_req = {0}; + struct roc_mcs_free_rsrc_req req = {0}; + int ret = 0; + + if (!roc_feature_nix_has_macsec()) + return -ENOTSUP; + + if (s == NULL) + return 0; + + stats_req.type = CNXK_MCS_RSRC_TYPE_FLOWID; + stats_req.id = s->flow_id; + stats_req.dir = s->dir; + stats_req.all = 0; + + ret = roc_mcs_stats_clear(mcs_dev->mdev, &stats_req); + if (ret) + plt_err("Failed to clear stats for Flow id %u, dir %u.", s->flow_id, s->dir); + + req.rsrc_id = s->flow_id; + req.dir = s->dir; + req.rsrc_type = CNXK_MCS_RSRC_TYPE_FLOWID; + + ret = roc_mcs_rsrc_free(mcs_dev->mdev, &req); + if (ret) + plt_err("Failed to free flow_id: %d.", s->flow_id); + + return ret; +} + static int cnxk_mcs_event_cb(void *userdata, struct roc_mcs_event_desc *desc, void *cb_arg) { diff --git a/drivers/net/cnxk/cnxk_ethdev_mcs.h b/drivers/net/cnxk/cnxk_ethdev_mcs.h index 68c6493169..2b1a6f2c90 100644 --- a/drivers/net/cnxk/cnxk_ethdev_mcs.h +++ b/drivers/net/cnxk/cnxk_ethdev_mcs.h @@ -21,6 +21,27 @@ enum cnxk_mcs_rsrc_type { CNXK_MCS_RSRC_TYPE_PORT, }; +struct cnxk_mcs_flow_opts { + uint32_t outer_tag_id; + /**< {VLAN_ID[11:0]}, or 20-bit MPLS label*/ + uint8_t outer_priority; + /**< {PCP/Pbits, DE/CFI} or {1'b0, EXP} for MPLS.*/ + uint32_t second_outer_tag_id; + /**< {VLAN_ID[11:0]}, or 20-bit MPLS label*/ + uint8_t second_outer_priority; + /**< {PCP/Pbits, DE/CFI} or {1'b0, EXP} for MPLS. */ + uint16_t bonus_data; + /**< 2 bytes of additional bonus data extracted from one of the custom tags*/ + uint8_t tag_match_bitmap; + uint8_t packet_type; + uint8_t outer_vlan_type; + uint8_t inner_vlan_type; + uint8_t num_tags; + bool express; + uint8_t lmac_id; + uint8_t flowid_user; +}; + struct cnxk_mcs_event_data { /* Valid for below events * - ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP @@ -75,3 +96,7 @@ int cnxk_eth_macsec_sa_destroy(void *device, uint16_t sa_id, enum rte_security_macsec_direction dir); int cnxk_eth_macsec_sc_destroy(void *device, uint16_t sc_id, enum rte_security_macsec_direction dir); + +int cnxk_eth_macsec_session_create(struct cnxk_eth_dev *dev, struct rte_security_session_conf *conf, + struct rte_security_session *sess); +int cnxk_eth_macsec_session_destroy(struct cnxk_eth_dev *dev, struct rte_security_session *sess); diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index a66d58ca61..dc17c128de 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -284,7 +284,7 @@ cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev, static unsigned int cnxk_eth_sec_session_get_size(void *device __rte_unused) { - return sizeof(struct cnxk_eth_sec_sess); + return RTE_MAX(sizeof(struct cnxk_macsec_sess), sizeof(struct cnxk_eth_sec_sess)); } struct rte_security_ops cnxk_eth_sec_ops = { diff --git a/drivers/net/cnxk/cnxk_flow.c b/drivers/net/cnxk/cnxk_flow.c index 9595fe9386..1bacb20784 100644 --- a/drivers/net/cnxk/cnxk_flow.c +++ b/drivers/net/cnxk/cnxk_flow.c @@ -300,6 +300,11 @@ cnxk_flow_validate(struct rte_eth_dev *eth_dev, uint32_t flowkey_cfg = 0; int rc; + /* Skip flow validation for MACsec. */ + if (actions[0].type == RTE_FLOW_ACTION_TYPE_SECURITY && + cnxk_eth_macsec_sess_get_by_sess(dev, actions[0].conf) != NULL) + return 0; + memset(&flow, 0, sizeof(flow)); flow.is_validate = true; From patchwork Wed Jun 7 15:28:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 128353 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6945E42C4E; Wed, 7 Jun 2023 17:30:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7248242F8C; Wed, 7 Jun 2023 17:29:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 5C9F442DC2 for ; Wed, 7 Jun 2023 17:29:11 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 357Dvh29028122; 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Wed, 7 Jun 2023 08:29:08 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:29:08 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id EF9D33F7084; Wed, 7 Jun 2023 08:29:05 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 15/15] net/cnxk: add MACsec stats Date: Wed, 7 Jun 2023 20:58:19 +0530 Message-ID: <20230607152819.226838-16-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: vh-svGoVyZRKrtflc7ix4uDKdc91IQ0n X-Proofpoint-GUID: vh-svGoVyZRKrtflc7ix4uDKdc91IQ0n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added support for MACsec SC/flow/session stats. Signed-off-by: Akhil Goyal --- drivers/net/cnxk/cn10k_ethdev_sec.c | 11 +++-- drivers/net/cnxk/cnxk_ethdev_mcs.c | 64 +++++++++++++++++++++++++++++ drivers/net/cnxk/cnxk_ethdev_mcs.h | 9 ++++ 3 files changed, 81 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index f20e573338..b98fc9378e 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -1058,12 +1058,17 @@ cn10k_eth_sec_session_stats_get(void *device, struct rte_security_session *sess, { struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_macsec_sess *macsec_sess; struct cnxk_eth_sec_sess *eth_sec; int rc; eth_sec = cnxk_eth_sec_sess_get_by_sess(dev, sess); - if (eth_sec == NULL) + if (eth_sec == NULL) { + macsec_sess = cnxk_eth_macsec_sess_get_by_sess(dev, sess); + if (macsec_sess) + return cnxk_eth_macsec_session_stats_get(dev, macsec_sess, stats); return -EINVAL; + } rc = roc_nix_inl_sa_sync(&dev->nix, eth_sec->sa, eth_sec->inb, ROC_NIX_INL_SA_OP_FLUSH); @@ -1107,6 +1112,6 @@ cn10k_eth_sec_ops_override(void) cnxk_eth_sec_ops.capabilities_get = cn10k_eth_sec_capabilities_get; cnxk_eth_sec_ops.session_update = cn10k_eth_sec_session_update; cnxk_eth_sec_ops.session_stats_get = cn10k_eth_sec_session_stats_get; - cnxk_eth_sec_ops.macsec_sc_stats_get = NULL; - cnxk_eth_sec_ops.macsec_sa_stats_get = NULL; + cnxk_eth_sec_ops.macsec_sc_stats_get = cnxk_eth_macsec_sc_stats_get; + cnxk_eth_sec_ops.macsec_sa_stats_get = cnxk_eth_macsec_sa_stats_get; } diff --git a/drivers/net/cnxk/cnxk_ethdev_mcs.c b/drivers/net/cnxk/cnxk_ethdev_mcs.c index b47991e259..851c83ff3f 100644 --- a/drivers/net/cnxk/cnxk_ethdev_mcs.c +++ b/drivers/net/cnxk/cnxk_ethdev_mcs.c @@ -517,6 +517,70 @@ cnxk_mcs_flow_destroy(struct cnxk_eth_dev *dev, void *flow) return ret; } +int +cnxk_eth_macsec_sa_stats_get(void *device, uint16_t sa_id, enum rte_security_macsec_direction dir, + struct rte_security_macsec_sa_stats *stats) +{ + RTE_SET_USED(device); + RTE_SET_USED(sa_id); + RTE_SET_USED(dir); + RTE_SET_USED(stats); + + return 0; +} + +int +cnxk_eth_macsec_sc_stats_get(void *device, uint16_t sc_id, enum rte_security_macsec_direction dir, + struct rte_security_macsec_sc_stats *stats) +{ + struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_mcs_dev *mcs_dev = dev->mcs_dev; + struct roc_mcs_stats_req req = {0}; + + if (!roc_feature_nix_has_macsec()) + return -ENOTSUP; + + req.id = sc_id; + req.dir = (dir == RTE_SECURITY_MACSEC_DIR_RX) ? MCS_RX : MCS_TX; + + return roc_mcs_sc_stats_get(mcs_dev->mdev, &req, (struct roc_mcs_sc_stats *)stats); +} + +int +cnxk_eth_macsec_session_stats_get(struct cnxk_eth_dev *dev, struct cnxk_macsec_sess *sess, + struct rte_security_stats *stats) +{ + struct cnxk_mcs_dev *mcs_dev = dev->mcs_dev; + struct roc_mcs_flowid_stats flow_stats = {0}; + struct roc_mcs_port_stats port_stats = {0}; + struct roc_mcs_stats_req req = {0}; + + if (!roc_feature_nix_has_macsec()) + return -ENOTSUP; + + req.id = sess->flow_id; + req.dir = sess->dir; + roc_mcs_flowid_stats_get(mcs_dev->mdev, &req, &flow_stats); + plt_nix_dbg("\n******* FLOW_ID IDX[%u] STATS dir: %u********\n", sess->flow_id, sess->dir); + plt_nix_dbg("TX: tcam_hit_cnt: 0x%lx\n", flow_stats.tcam_hit_cnt); + + req.id = mcs_dev->port_id; + req.dir = sess->dir; + roc_mcs_port_stats_get(mcs_dev->mdev, &req, &port_stats); + plt_nix_dbg("\n********** PORT[0] STATS ****************\n"); + plt_nix_dbg("RX tcam_miss_cnt: 0x%lx\n", port_stats.tcam_miss_cnt); + plt_nix_dbg("RX parser_err_cnt: 0x%lx\n", port_stats.parser_err_cnt); + plt_nix_dbg("RX preempt_err_cnt: 0x%lx\n", port_stats.preempt_err_cnt); + plt_nix_dbg("RX sectag_insert_err_cnt: 0x%lx\n", port_stats.sectag_insert_err_cnt); + + req.id = sess->secy_id; + req.dir = sess->dir; + + return roc_mcs_secy_stats_get(mcs_dev->mdev, &req, + (struct roc_mcs_secy_stats *)(&stats->macsec)); +} + static int cnxk_mcs_event_cb(void *userdata, struct roc_mcs_event_desc *desc, void *cb_arg) { diff --git a/drivers/net/cnxk/cnxk_ethdev_mcs.h b/drivers/net/cnxk/cnxk_ethdev_mcs.h index 2b1a6f2c90..4a59dd3df9 100644 --- a/drivers/net/cnxk/cnxk_ethdev_mcs.h +++ b/drivers/net/cnxk/cnxk_ethdev_mcs.h @@ -97,6 +97,15 @@ int cnxk_eth_macsec_sa_destroy(void *device, uint16_t sa_id, int cnxk_eth_macsec_sc_destroy(void *device, uint16_t sc_id, enum rte_security_macsec_direction dir); +int cnxk_eth_macsec_sa_stats_get(void *device, uint16_t sa_id, + enum rte_security_macsec_direction dir, + struct rte_security_macsec_sa_stats *stats); +int cnxk_eth_macsec_sc_stats_get(void *device, uint16_t sa_id, + enum rte_security_macsec_direction dir, + struct rte_security_macsec_sc_stats *stats); +int cnxk_eth_macsec_session_stats_get(struct cnxk_eth_dev *dev, struct cnxk_macsec_sess *sess, + struct rte_security_stats *stats); + int cnxk_eth_macsec_session_create(struct cnxk_eth_dev *dev, struct rte_security_session_conf *conf, struct rte_security_session *sess); int cnxk_eth_macsec_session_destroy(struct cnxk_eth_dev *dev, struct rte_security_session *sess);