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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CY4PEPF0000EE39.mail.protection.outlook.com (10.167.242.13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6477.13 via Frontend Transport; Thu, 8 Jun 2023 12:16:19 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Thu, 8 Jun 2023 05:16:06 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Thu, 8 Jun 2023 05:16:04 -0700 From: Gregory Etelson To: CC: , Subject: [PATCH] net/mlx5: fix actions template expansion Date: Thu, 8 Jun 2023 15:15:52 +0300 Message-ID: <20230608121552.339729-1-getelson@nvidia.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE39:EE_|BY5PR12MB4854:EE_ X-MS-Office365-Filtering-Correlation-Id: 6530e2eb-c6c3-46aa-23eb-08db681a2a6a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2023 12:16:19.1688 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6530e2eb-c6c3-46aa-23eb-08db681a2a6a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE39.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4854 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Static actions definitions used in template expansion were defined in conditional context. That context was destroyed by the time it's memory was accessed. Fixes: cf7f458b05f3 ("net/mlx5: add indirect QUOTA create/query/modify") Signed-off-by: Gregory Etelson --- drivers/net/mlx5/mlx5_flow_hw.c | 188 +++++++++++++------------------- 1 file changed, 78 insertions(+), 110 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index bbb88a6478..cb040a51ac 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -4637,78 +4637,80 @@ flow_hw_actions_template_replace_container(const *rm = (void *)(uintptr_t)new_masks; } -#define RX_META_COPY_ACTION ((const struct rte_flow_action) { \ - .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD, \ - .conf = &(struct rte_flow_action_modify_field){ \ - .operation = RTE_FLOW_MODIFY_SET, \ - .dst = { \ - .field = (enum rte_flow_field_id) \ - MLX5_RTE_FLOW_FIELD_META_REG, \ - .level = REG_B, \ - }, \ - .src = { \ - .field = (enum rte_flow_field_id) \ - MLX5_RTE_FLOW_FIELD_META_REG, \ - .level = REG_C_1, \ - }, \ - .width = 32, \ - } \ -}) - -#define RX_META_COPY_MASK ((const struct rte_flow_action) { \ - .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD, \ - .conf = &(struct rte_flow_action_modify_field){ \ - .operation = RTE_FLOW_MODIFY_SET, \ - .dst = { \ - .field = (enum rte_flow_field_id) \ - MLX5_RTE_FLOW_FIELD_META_REG, \ - .level = UINT32_MAX, \ - .offset = UINT32_MAX, \ - }, \ - .src = { \ - .field = (enum rte_flow_field_id) \ - MLX5_RTE_FLOW_FIELD_META_REG, \ - .level = UINT32_MAX, \ - .offset = UINT32_MAX, \ - }, \ - .width = UINT32_MAX, \ - } \ -}) - -#define QUOTA_COLOR_INC_ACTION ((const struct rte_flow_action) { \ - .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD, \ - .conf = &(struct rte_flow_action_modify_field) { \ - .operation = RTE_FLOW_MODIFY_ADD, \ - .dst = { \ - .field = RTE_FLOW_FIELD_METER_COLOR, \ - .level = 0, .offset = 0 \ - }, \ - .src = { \ - .field = RTE_FLOW_FIELD_VALUE, \ - .level = 1, \ - .offset = 0, \ - }, \ - .width = 2 \ - } \ -}) - -#define QUOTA_COLOR_INC_MASK ((const struct rte_flow_action) { \ - .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD, \ - .conf = &(struct rte_flow_action_modify_field) { \ - .operation = RTE_FLOW_MODIFY_ADD, \ - .dst = { \ - .field = RTE_FLOW_FIELD_METER_COLOR, \ - .level = UINT32_MAX, \ - .offset = UINT32_MAX, \ - }, \ - .src = { \ - .field = RTE_FLOW_FIELD_VALUE, \ - .level = 3, \ - .offset = 0 \ - }, \ - .width = UINT32_MAX \ - } \ -}) +/* Action template copies these actions in rte_flow_conv() */ + +static const struct rte_flow_action rx_meta_copy_action = { + .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD, + .conf = &(struct rte_flow_action_modify_field){ + .operation = RTE_FLOW_MODIFY_SET, + .dst = { + .field = (enum rte_flow_field_id) + MLX5_RTE_FLOW_FIELD_META_REG, + .level = REG_B, + }, + .src = { + .field = (enum rte_flow_field_id) + MLX5_RTE_FLOW_FIELD_META_REG, + .level = REG_C_1, + }, + .width = 32, + } +}; + +static const struct rte_flow_action rx_meta_copy_mask = { + .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD, + .conf = &(struct rte_flow_action_modify_field){ + .operation = RTE_FLOW_MODIFY_SET, + .dst = { + .field = (enum rte_flow_field_id) + MLX5_RTE_FLOW_FIELD_META_REG, + .level = UINT8_MAX, + .offset = UINT32_MAX, + }, + .src = { + .field = (enum rte_flow_field_id) + MLX5_RTE_FLOW_FIELD_META_REG, + .level = UINT8_MAX, + .offset = UINT32_MAX, + }, + .width = UINT32_MAX, + } +}; + +static const struct rte_flow_action quota_color_inc_action = { + .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD, + .conf = &(struct rte_flow_action_modify_field) { + .operation = RTE_FLOW_MODIFY_ADD, + .dst = { + .field = RTE_FLOW_FIELD_METER_COLOR, + .level = 0, .offset = 0 + }, + .src = { + .field = RTE_FLOW_FIELD_VALUE, + .level = 1, + .offset = 0, + }, + .width = 2 + } +}; + +static const struct rte_flow_action quota_color_inc_mask = { + .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD, + .conf = &(struct rte_flow_action_modify_field) { + .operation = RTE_FLOW_MODIFY_ADD, + .dst = { + .field = RTE_FLOW_FIELD_METER_COLOR, + .level = UINT8_MAX, + .offset = UINT32_MAX, + }, + .src = { + .field = RTE_FLOW_FIELD_VALUE, + .level = 3, + .offset = 0 + }, + .width = UINT32_MAX + } +}; /** * Create flow action template. @@ -4748,40 +4750,6 @@ flow_hw_actions_template_create(struct rte_eth_dev *dev, int set_vlan_vid_ix = -1; struct rte_flow_action_modify_field set_vlan_vid_spec = {0, }; struct rte_flow_action_modify_field set_vlan_vid_mask = {0, }; - const struct rte_flow_action_modify_field rx_mreg = { - .operation = RTE_FLOW_MODIFY_SET, - .dst = { - .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_B, - }, - .src = { - .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_C_1, - }, - .width = 32, - }; - const struct rte_flow_action_modify_field rx_mreg_mask = { - .operation = RTE_FLOW_MODIFY_SET, - .dst = { - .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT8_MAX, - .offset = UINT32_MAX, - }, - .src = { - .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT8_MAX, - .offset = UINT32_MAX, - }, - .width = UINT32_MAX, - }; - const struct rte_flow_action rx_cpy = { - .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD, - .conf = &rx_mreg, - }; - const struct rte_flow_action rx_cpy_mask = { - .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD, - .conf = &rx_mreg_mask, - }; struct rte_flow_action mf_actions[MLX5_HW_MAX_ACTS]; struct rte_flow_action mf_masks[MLX5_HW_MAX_ACTS]; uint32_t expand_mf_num = 0; @@ -4829,16 +4797,16 @@ flow_hw_actions_template_create(struct rte_eth_dev *dev, action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD; } if (action_flags & MLX5_FLOW_ACTION_QUOTA) { - mf_actions[expand_mf_num] = QUOTA_COLOR_INC_ACTION; - mf_masks[expand_mf_num] = QUOTA_COLOR_INC_MASK; + mf_actions[expand_mf_num] = quota_color_inc_action; + mf_masks[expand_mf_num] = quota_color_inc_mask; expand_mf_num++; } if (priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS && priv->sh->config.dv_esw_en && (action_flags & (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS))) { /* Insert META copy */ - mf_actions[expand_mf_num] = RX_META_COPY_ACTION; - mf_masks[expand_mf_num] = RX_META_COPY_MASK; + mf_actions[expand_mf_num] = rx_meta_copy_action; + mf_masks[expand_mf_num] = rx_meta_copy_mask; expand_mf_num++; } if (expand_mf_num) {