From patchwork Wed Jun 14 05:52:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 128660 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1CC1D42CAD; Wed, 14 Jun 2023 07:52:48 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 09F9A40DDB; Wed, 14 Jun 2023 07:52:48 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2086.outbound.protection.outlook.com [40.107.220.86]) by mails.dpdk.org (Postfix) with ESMTP id 09B2440A7D for ; Wed, 14 Jun 2023 07:52:47 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=I2Jdh3sCoabDuysgp6HWMmJXy2SfXoVcZ8lmNW1nSLacfiVuO/kPmeARYwf4OYmQ94mWE/UYEZSQgWVIWZcVTuec2DQwAEw6bYGKzz6Phj0UGhFd92PdJeZj7HA1BB8luwxbMCx7n6bpojSm8GRSxT3sIjpOR0SjjOsqR/Nx7WEGNpQ6quvfqzWFQwy7xRfzUFnXTbCyN0o82mbJgYdm2liZ1OVfW61vlEXZ9JVuc9xzRuIF5HtyuZg+CQTdqDSeHiAz2kId20fHsm2s4fXtRcFMlonu/sF4cLYfjU6PpDcpgDni5iD5dUC7TxSv0EOOzRLThGS1eSix95kJJ/gV8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=cwikCEGDejLwnDk5DHC1gc1Ur/Nom0pEwzmCUW7irbQ=; b=b+DuC53wGjHEc8O1ffIQcZ0sCAn0ExCH02prcnzaNpHQsOZBOzEfPalhnWzMWJ+RlQdhdoa3bn60sZLRXmdHTLLWyXFEKH+3kxzCP0P5ORQ5uPaDJITN+kepBr/8SYPX9ovo+xji6/VfHdBDZsooG3L8MTXMFNqIpg+33Rh0pA9lxRwfdfVMxcj/fX8Xf/ihDC87QhXRCK+Ms/C8kvysr/ICs6+WPoHZyODXomy1B5+fxjyfGfjvx+s7LoFZSCG0o+LNaZ32gk+BGO9mSN86NNE4Neg9atF8JzWsEWpJhg6ji7V9d3rtP6d4mHm3eMJ2A/upDnJktJSUTgocXQ/p8w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cwikCEGDejLwnDk5DHC1gc1Ur/Nom0pEwzmCUW7irbQ=; b=FUAkcshtdFb1A4vVXOqaDlx0FEJyxHSJisom1z6UO+bsiPJxI8JLaTAUMj+HXzBNl3xCdSfGpKIlYBXegnoUrdrJCQqhBzbvkfviNoVVo99sB+KXLj1HJ04zhHtFPKMALtYShgwfsF2dtKdKbtAnXaxiZ6ZP2aNMas2AU2GJ/DZz97rsKNI6G+XQLJyBcwQpkk2v8IIHODRtmAbulYw8qGaoav8Z8cTc3FEO3zuLuUrxjYS2FE7OtJsobg08vrqmKASny2zRJIc6Lm2Qvt/+0CpPwEcnLBy/s5gl7yDTawkhpKQCok98V1C34pO41o4vZpU2Y0jOOIBp2O/JZVLFbQ== Received: from BN9PR03CA0854.namprd03.prod.outlook.com (2603:10b6:408:13d::19) by BY5PR12MB4322.namprd12.prod.outlook.com (2603:10b6:a03:20a::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6477.29; Wed, 14 Jun 2023 05:52:44 +0000 Received: from BN8NAM11FT060.eop-nam11.prod.protection.outlook.com (2603:10b6:408:13d:cafe::f2) by BN9PR03CA0854.outlook.office365.com (2603:10b6:408:13d::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6477.37 via Frontend Transport; Wed, 14 Jun 2023 05:52:44 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by BN8NAM11FT060.mail.protection.outlook.com (10.13.177.211) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6500.23 via Frontend Transport; Wed, 14 Jun 2023 05:52:44 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 13 Jun 2023 22:52:41 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 13 Jun 2023 22:52:40 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37 via Frontend Transport; Tue, 13 Jun 2023 22:52:39 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko Subject: [PATCH 1/2] net/mlx5: align implementation with modify API Date: Wed, 14 Jun 2023 08:52:33 +0300 Message-ID: <20230614055234.2322466-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230614055234.2322466-1-michaelba@nvidia.com> References: <20230614055234.2322466-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT060:EE_|BY5PR12MB4322:EE_ X-MS-Office365-Filtering-Correlation-Id: 09d0ced4-0502-46ac-718a-08db6c9b92e5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MoolPDiixRX6X9a0Lwq1T0J+QV8N0rVBB7H0lMdoxEW2He7mSF8WNIzaE8oNlML+uaSvVCxFonB6zCu6q7aidf5CTZUeRuCFnzSbiPacR5QSecXzRzL+/7xV4x/fyK4+4opQUfH5csnK2/FK4r6W00NyvyQWyL5eF05tOnYhjOSuPEZTtsKT8vuE9ElzUMIxqTMGAAd9UPlnRumalO4CrKVXf4plRqiXEj4u56bG120rGjLMPB3kq5+x+Oqnva6eJtN/dOt14NZgUPiHDJEK5AaNRwcNRs3RbYpb6EtV8jkPaGQ1ShIh2fyjsSeJQAnou98B2Qs3kzBUY/CWt3XgdwgXJ/eGJkaJTXpdL2RiU1+i+0AEVbpbkMyW2DUXpY1PYmBJo3DHdKFbXwK8YRXd3D6oOBIlnDMlQn13JOrJEOLRkn2t6NZT8g8Z96EvttAZJvy/QDGn7lb+KMMN9bZJvoUSzw+tEtwjEFhANyr/M/7fH1WN+MmXUJrWW1MoBzkjvvY/SffMBRMVk7A0KYcHN2bV61biqpE1nqZSgWQsVU1spyVrnStacLvCcgGwtGLoR5noEbXSci697A/xX9tYI3MPOs9fI6/8Rou1FgvaZ/yeWPQ2BPwkS3XObPQbSrRNPgEwHSBrYJ67l7um0DNshroXsiHUrSNrocRi7ll/7aanpxeDAKv8JBVf56oNaaxpLJWHtfMGLD3j4xjDOo+LY8/PRL1YFXySdhuDclq4VJg= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(39860400002)(136003)(376002)(396003)(346002)(451199021)(40470700004)(46966006)(36840700001)(70206006)(8676002)(70586007)(54906003)(478600001)(5660300002)(36756003)(8936002)(6916009)(6666004)(4326008)(316002)(40460700003)(336012)(426003)(41300700001)(7696005)(55016003)(7636003)(356005)(82740400003)(40480700001)(83380400001)(186003)(86362001)(2906002)(1076003)(26005)(47076005)(36860700001)(82310400005)(107886003)(2616005)(6286002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jun 2023 05:52:44.1420 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 09d0ced4-0502-46ac-718a-08db6c9b92e5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4322 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Modify field action API has been changed to use "tag_index" instead of "level" fields to represent the tag array for TAG modification type. Although the old API still work, this patch move all internal API usage to use "tag_index". Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_flow.h | 12 +++++++++ drivers/net/mlx5/mlx5_flow_dv.c | 18 +++++++++++++ drivers/net/mlx5/mlx5_flow_hw.c | 47 ++++++++++++++++++++++++++------- 3 files changed, 67 insertions(+), 10 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 02e33c7fb3..568dae751e 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1108,6 +1108,18 @@ flow_dv_fetch_field(const uint8_t *data, uint32_t size) return ret; } +static inline bool +flow_modify_field_support_tag_array(enum rte_flow_field_id field) +{ + switch (field) { + case RTE_FLOW_FIELD_TAG: + return true; + default: + break; + } + return false; +} + struct field_modify_info { uint32_t size; /* Size of field in protocol header, in bytes. */ uint32_t offset; /* Offset of field in protocol header, in bytes. */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 7535500870..f6278935c1 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -5291,6 +5291,15 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, ret = flow_validate_modify_field_level(dst_data, error); if (ret) return ret; + if (dst_data->tag_index && + !flow_modify_field_support_tag_array(dst_data->field)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "destination tag index is not supported"); + if (dst_data->class_id) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "destination class ID is not supported"); } if (src_data->field != RTE_FLOW_FIELD_VALUE && src_data->field != RTE_FLOW_FIELD_POINTER) { @@ -5306,6 +5315,15 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, ret = flow_validate_modify_field_level(src_data, error); if (ret) return ret; + if (src_data->tag_index && + !flow_modify_field_support_tag_array(src_data->field)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "source tag index is not supported"); + if (src_data->class_id) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "source class ID is not supported"); } if ((dst_data->field == src_data->field) && (dst_data->level == src_data->level)) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index f17a2a0522..0c76ee7446 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -3653,6 +3653,15 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, ret = flow_validate_modify_field_level(&action_conf->dst, error); if (ret) return ret; + if (action_conf->dst.tag_index && + !flow_modify_field_support_tag_array(action_conf->dst.field)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "destination tag index is not supported"); + if (action_conf->dst.class_id) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "destination class id is not supported"); if (mask_conf->dst.level != UINT8_MAX) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, @@ -3667,6 +3676,15 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, "destination field mask and template are not equal"); if (action_conf->src.field != RTE_FLOW_FIELD_POINTER && action_conf->src.field != RTE_FLOW_FIELD_VALUE) { + if (action_conf->src.tag_index && + !flow_modify_field_support_tag_array(action_conf->src.field)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "source tag index is not supported"); + if (action_conf->src.class_id) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "source class id is not supported"); if (mask_conf->src.level != UINT8_MAX) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, @@ -4646,12 +4664,12 @@ static const struct rte_flow_action rx_meta_copy_action = { .dst = { .field = (enum rte_flow_field_id) MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_B, + .tag_index = REG_B, }, .src = { .field = (enum rte_flow_field_id) MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_C_1, + .tag_index = REG_C_1, }, .width = 32, } @@ -4665,12 +4683,14 @@ static const struct rte_flow_action rx_meta_copy_mask = { .field = (enum rte_flow_field_id) MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .src = { .field = (enum rte_flow_field_id) MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .width = UINT32_MAX, @@ -4701,6 +4721,7 @@ static const struct rte_flow_action quota_color_inc_mask = { .dst = { .field = RTE_FLOW_FIELD_METER_COLOR, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .src = { @@ -5824,7 +5845,7 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_C_0, + .tag_index = REG_C_0, .offset = rte_bsf32(tag_mask), }, .src = { @@ -5837,6 +5858,7 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev) .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .src = { @@ -5848,11 +5870,11 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_C_1, + .tag_index = REG_C_1, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_A, + .tag_index = REG_A, }, .width = 32, }; @@ -5861,11 +5883,13 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev) .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .width = UINT32_MAX, @@ -6181,7 +6205,7 @@ flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_C_0, + .tag_index = REG_C_0, }, .src = { .field = RTE_FLOW_FIELD_VALUE, @@ -6193,6 +6217,7 @@ flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev) .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .src = { @@ -6353,11 +6378,11 @@ flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_C_1, + .tag_index = REG_C_1, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_A, + .tag_index = REG_A, }, .width = 32, }; @@ -6366,11 +6391,13 @@ flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev) .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .width = UINT32_MAX, @@ -9514,11 +9541,11 @@ mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_C_1, + .tag_index = REG_C_1, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_A, + .tag_index = REG_A, }, .width = 32, }; From patchwork Wed Jun 14 05:52:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 128662 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A150D42CAD; Wed, 14 Jun 2023 07:52:58 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3E13B42BB1; Wed, 14 Jun 2023 07:52:53 +0200 (CEST) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2051.outbound.protection.outlook.com [40.107.93.51]) by mails.dpdk.org (Postfix) with ESMTP id 5981F40A7D for ; Wed, 14 Jun 2023 07:52:51 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XibQsDBOznvlHTnDVMJXAW6TZlbhoGIc9aZVHS5gFU2z+dxGRcLrZBkiwx2TIcU/7PzytnGxB3E2JH+EQH/1xFiP+osUkEoKH8z/mOAsKa60M/agekkkJy9Eo46bVZSj8e9oPsnzFVYTK/tclFaNfGJnpIfcYi6l5j7b/9TlU87zx7wxjrCWQhegs39ericdd7E2TKOz77SAiUL8wPcyig8EwmL9yAdly48WWVfMfF45YTVmfSaTUeQ3WJRBcBPxRPuWnjDkK7DVnvgcIifEQ3oyONfBZu3rwpMX28B2GhDQw2tvEh6CYC/E4WzME4aXJtHZ5foEDdefXN7Fth2cnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Y9WgGg/9re3Q7DCfX4Ig+GkS1SC6s9fAPMQJ7eck83c=; b=cmcthxCLE4oApbjFCcNu8ym602RVAql5wtCSepeLY4PjZclNdDS6w8Y6ogC4/FvKVM6w/BgzL5a9vqcvOruPlA+HPiSHxHoS9/1Qbgr9OdTuCEG9+eunoRSkmtrCMFl2n7qfmut+NVuPa3Zt0cuOGNO8Oa8P2j8fP2v9Lx0tPiYV/0hu+hXcZBcGdvwZrsxsic7kTXSlgr34HlaadDRrrgXqbn4gQEfkdhvkN8mWZG9Hj3odIeKQeBm/ULKbtJeUgWNZTKg2/45jqFJaWXk65gm31Ee9s5Nw3qSlS6UpfaSsyBPoTILEl5DxHi5BMOzHLt702cxoOMMi9R0zszgShA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Y9WgGg/9re3Q7DCfX4Ig+GkS1SC6s9fAPMQJ7eck83c=; b=gkUoQJpcy90arJxTCosoxe35kq8hrPGpjIAh66G0iRnYD1DfnkRVv7QeYjWFotsyb1t0qRu4n6ReUje1kpeHhQDwjTdtdBk250VQctBha/aPJRtDnv53oGonK6HRjQMDQOLTqXLIcO01Mx354IZCmcr8b1yijDYOqjm8b4A5+h2nKyZy58i5DD0WcBIKcvrTdFf9HneSttnbs0AyqnDwpXH5eNEikzaC+bwAcHolS9ho6XUVYInLP6r/s6PcwDXPy0oUmbuhixZB2TwEtnbUAGn/yrSwavGdCCMHJXTgQw92m3XSgroa8y6bX559k3dswU+v31k96UfssHtQCXoSRg== Received: from BN9PR03CA0856.namprd03.prod.outlook.com (2603:10b6:408:13d::21) by CH3PR12MB8581.namprd12.prod.outlook.com (2603:10b6:610:15d::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6455.39; Wed, 14 Jun 2023 05:52:46 +0000 Received: from BN8NAM11FT060.eop-nam11.prod.protection.outlook.com (2603:10b6:408:13d:cafe::2b) by BN9PR03CA0856.outlook.office365.com (2603:10b6:408:13d::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6477.35 via Frontend Transport; Wed, 14 Jun 2023 05:52:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by BN8NAM11FT060.mail.protection.outlook.com (10.13.177.211) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6500.23 via Frontend Transport; Wed, 14 Jun 2023 05:52:46 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 13 Jun 2023 22:52:42 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 13 Jun 2023 22:52:42 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37 via Frontend Transport; Tue, 13 Jun 2023 22:52:41 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko Subject: [PATCH 2/2] net/mlx5: add MPLS modify field support Date: Wed, 14 Jun 2023 08:52:34 +0300 Message-ID: <20230614055234.2322466-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230614055234.2322466-1-michaelba@nvidia.com> References: <20230614055234.2322466-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT060:EE_|CH3PR12MB8581:EE_ X-MS-Office365-Filtering-Correlation-Id: 8ac576e9-e6d6-4af6-2234-08db6c9b943f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CInOIDfG+JrmtrONpl8W6nJ6ObZR+HoNQltprWY+MhfzXsOT3U+UgL6sb0FhEU9jbsXP5iQp0msMDV6TZVtRtEqT31/Mf3//87QZ0XUMMo7gTrhEg5ic1ek8oaWloAWNFR4um7GbrvEwtu7VQpsDNLPLseCFsgF1LLsH/KIHbnqdP5Jc/+0F/4AD3IKDuLvonWGiUrZLCCbX8N0eYCpaxYzvr8RcfViXaZcfBZCqnk2TL1DLNJPo2PNgmaqAFaSPEh3xiYdckRXewdcVVUhqBfPseXF60Idvek8kg7/OP4MIIiFGezT+qYF6QpiwraknaDT2wBI8StQjxhadx/XQSzxuZwo6KpfWhmsDN5/3lEAmqCBz3WCqfsh8ipdZTSPiFcP3Bl1l5wA9Ct9XC76a7JGqPPS1QBDbpWCqRsurY+7WNFGIa42BA12hAKaamfIQ2atJb1umFbp29/db4k0I77bMS7hY/mo9WHtuuhc/PFUTz3Dvdx6A6W4HJAgXuM3KcetMd2bM6BtR6jV61csKj+63WTHcH8dAbqNNI5sholp7UbFxT3arMsxRTyukA68KuOtPMRddI4+IfkwxiR0/HdOTgW4ygLXhK1x11ExmN5QiCXXSRgFa2oIgWeAe1RFnkOSTkJmLLPCoLQGur8sL3kfyEc8QtorlzUST7Ax2A8kRqcJ+9SRpxHv5CwZGyOnH5Yij1IJ3QLsuBZf1bxYJUTJ0b3MHvhLtrL5WZ6VWPxAqFwR7xtkrV+fH3L69zmvj X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(39860400002)(396003)(136003)(346002)(376002)(451199021)(46966006)(40470700004)(36840700001)(70586007)(6916009)(478600001)(4326008)(8936002)(2906002)(41300700001)(54906003)(7696005)(6666004)(70206006)(5660300002)(8676002)(316002)(1076003)(26005)(107886003)(82310400005)(40460700003)(186003)(6286002)(7636003)(356005)(55016003)(40480700001)(82740400003)(83380400001)(426003)(336012)(2616005)(36756003)(36860700001)(47076005)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jun 2023 05:52:46.4234 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ac576e9-e6d6-4af6-2234-08db6c9b943f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8581 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for modify field in tunnel MPLS header. For now it is supported only to copy from. Signed-off-by: Michael Baum Acked-by: Matan Azrad --- doc/guides/nics/mlx5.rst | 2 ++ drivers/common/mlx5/mlx5_prm.h | 5 +++++ drivers/net/mlx5/mlx5_flow.h | 1 + drivers/net/mlx5/mlx5_flow_dv.c | 23 +++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow_hw.c | 10 +++++++--- 5 files changed, 38 insertions(+), 3 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 85db539f19..67f7c407fc 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -538,6 +538,8 @@ Limitations - Supports the 'set' and 'add' operations for ``RTE_FLOW_ACTION_TYPE_MODIFY_FIELD`` action. - Modification of an arbitrary place in a packet via the special ``RTE_FLOW_FIELD_START`` Field ID is not supported. + - Modification of the MPLS header is supported only in HWS and only to copy + from, the encapsulation level is always 0. - Modification of the 802.1Q Tag, VXLAN Network or GENEVE Network ID's is not supported. - Encapsulation levels are not supported, can modify outermost header fields only. - Offsets cannot skip past the boundary of a field. diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index d67c4336e6..4a8e1a10e5 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -787,6 +787,11 @@ enum mlx5_modification_field { MLX5_MODI_TUNNEL_HDR_DW_1 = 0x75, MLX5_MODI_GTPU_FIRST_EXT_DW_0 = 0x76, MLX5_MODI_HASH_RESULT = 0x81, + MLX5_MODI_IN_MPLS_LABEL_0 = 0x8a, + MLX5_MODI_IN_MPLS_LABEL_1, + MLX5_MODI_IN_MPLS_LABEL_2, + MLX5_MODI_IN_MPLS_LABEL_3, + MLX5_MODI_IN_MPLS_LABEL_4, MLX5_MODI_OUT_IPV6_NEXT_HDR = 0x4A, MLX5_MODI_INVALID = INT_MAX, }; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 568dae751e..ca9d7ac40c 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1113,6 +1113,7 @@ flow_modify_field_support_tag_array(enum rte_flow_field_id field) { switch (field) { case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_MPLS: return true; default: break; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index f6278935c1..8e89b41c2d 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1388,6 +1388,7 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev, case RTE_FLOW_FIELD_GENEVE_VNI: return 24; case RTE_FLOW_FIELD_GTP_TEID: + case RTE_FLOW_FIELD_MPLS: case RTE_FLOW_FIELD_TAG: return 32; case RTE_FLOW_FIELD_MARK: @@ -1435,6 +1436,12 @@ flow_modify_info_mask_32_masked(uint32_t length, uint32_t off, uint32_t post_mas return rte_cpu_to_be_32(mask & post_mask); } +static __rte_always_inline enum mlx5_modification_field +mlx5_mpls_modi_field_get(const struct rte_flow_action_modify_data *data) +{ + return MLX5_MODI_IN_MPLS_LABEL_0 + data->tag_index; +} + static void mlx5_modify_flex_item(const struct rte_eth_dev *dev, const struct mlx5_flex_item *flex, @@ -1893,6 +1900,16 @@ mlx5_flow_field_id_to_modify_info else info[idx].offset = off_be; break; + case RTE_FLOW_FIELD_MPLS: + MLX5_ASSERT(data->offset + width <= 32); + off_be = 32 - (data->offset + width); + info[idx] = (struct field_modify_info){4, 0, + mlx5_mpls_modi_field_get(data)}; + if (mask) + mask[idx] = flow_modify_info_mask_32(width, off_be); + else + info[idx].offset = off_be; + break; case RTE_FLOW_FIELD_TAG: { MLX5_ASSERT(data->offset + width <= 32); @@ -5362,6 +5379,12 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, RTE_FLOW_ERROR_TYPE_ACTION, action, "modifications of the GENEVE Network" " Identifier is not supported"); + if (dst_data->field == RTE_FLOW_FIELD_MPLS || + src_data->field == RTE_FLOW_FIELD_MPLS) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "modifications of the MPLS header " + "is not supported"); if (dst_data->field == RTE_FLOW_FIELD_MARK || src_data->field == RTE_FLOW_FIELD_MARK) if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 0c76ee7446..8f35356c41 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -3713,6 +3713,11 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, "modifying Geneve VNI is not supported"); + /* Due to HW bug, tunnel MPLS header is read only. */ + if (action_conf->dst.field == RTE_FLOW_FIELD_MPLS) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "MPLS cannot be used as destination"); return 0; } @@ -4243,9 +4248,8 @@ mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev, action_flags |= MLX5_FLOW_ACTION_METER; break; case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: - ret = flow_hw_validate_action_modify_field(action, - mask, - error); + ret = flow_hw_validate_action_modify_field(action, mask, + error); if (ret < 0) return ret; action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;