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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF000252A4.mail.protection.outlook.com (10.167.242.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.16 via Frontend Transport; Thu, 9 Nov 2023 18:02:04 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Thu, 9 Nov 2023 10:01:35 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Thu, 9 Nov 2023 10:01:33 -0800 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Bing Zhao CC: , Raslan Darawsheh , Subject: [PATCH] net/mlx5: fix unbind of incorrect hairpin queue Date: Thu, 9 Nov 2023 20:01:09 +0200 Message-ID: <20231109180109.3185537-1-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A4:EE_|PH0PR12MB5605:EE_ X-MS-Office365-Filtering-Correlation-Id: 932c076b-95bd-47d6-c7bc-08dbe14dfb7c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2023 18:02:04.9641 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 932c076b-95bd-47d6-c7bc-08dbe14dfb7c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5605 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Let's take an application with the following configuration: - It uses 2 ports. - Each port has 3 Rx queues and 3 Tx queues. - On each port, Rx queues have a following purposes: - Rx queue 0 - SW queue, - Rx queue 1 - hairpin queue, bound to Tx queue on the same port, - Rx queue 2 - hairpin queue, bound to Tx queue on another port. - On each port, Tx queues have a following purposes: - Tx queue 0 - SW queue, - Tx queue 1 - hairpin queue, bound to Rx queue on the same port, - Tx queue 2 - hairpin queue, bound to Rx queue on another port. - Application configured all of the hairpin queues for manual binding. After ports are configured and queues are set up, if the application does the following API call sequence: 1. rte_eth_dev_start(port_id=0) 2. rte_eth_hairpin_bind(tx_port=0, rx_port=0) 3. rte_eth_hairpin_bind(tx_port=0, rx_port=1) mlx5 PMD fails to modify SQ and logs this error: mlx5_common: mlx5_devx_cmds.c:2079: mlx5_devx_cmd_modify_sq(): Failed to modify SQ using DevX This error was caused by an incorrect unbind operation taken during error handling inside call (3). (3) fails, because port 1 (Rx side of the hairpin) was not started. As a result of this failure, PMD goes into error handling, where all previously bound hairpin queues are unbound. This is incorrect, since this error handling procedure in rte_eth_hairpin_bind() implementation assumes that all hairpin queues are bound to the same rx_port, which is not the case. The following sequence of function calls appears: - rte_eth_hairpin_queue_peer_unbind(rx_port=**1**, rx_queue=1, 0), - mlx5_hairpin_queue_peer_unbind(dev=**port 0**, tx_queue=1, 1). Which violates the hairpin queue destroy flow, by unbinding Tx queue 1 on port 0, before unbinding Rx queue 1 on port 1. This patch fixes that behavior, by filtering Tx queues on which error handling is done to only affect: - hairpin queues (it also reduces unnecessary debug log messages), - hairpin queues connected to the rx_port which is currently processed. Fixes: 37cd4501e873 ("net/mlx5: support two ports hairpin mode") Cc: bingz@nvidia.com Cc: stable@dpdk.org Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_trigger.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index 88dc271a21..329fa7da3e 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -845,6 +845,11 @@ mlx5_hairpin_bind_single_port(struct rte_eth_dev *dev, uint16_t rx_port) txq_ctrl = mlx5_txq_get(dev, i); if (txq_ctrl == NULL) continue; + if (!txq_ctrl->is_hairpin || + txq_ctrl->hairpin_conf.peers[0].port != rx_port) { + mlx5_txq_release(dev, i); + continue; + } rx_queue = txq_ctrl->hairpin_conf.peers[0].queue; rte_eth_hairpin_queue_peer_unbind(rx_port, rx_queue, 0); mlx5_hairpin_queue_peer_unbind(dev, i, 1);