From patchwork Tue Dec 5 10:00:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rakesh Kudurumalla X-Patchwork-Id: 134874 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A33DF43676; Tue, 5 Dec 2023 11:04:00 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5126242E15; Tue, 5 Dec 2023 11:04:00 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D05CB402C8 for ; Tue, 5 Dec 2023 11:03:58 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3B59ThEw007127 for ; Tue, 5 Dec 2023 02:03:58 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=jR3XSirp8skxC/9UW+iyYWv3to95pMdlucg7ZGrFnC8=; b=KgTORIAz5Yi3NdjOQiSZuovjlmbnXQZc3msQ+TGOT0HPq0IikTCf+u6zGJJ417tTiH3s AlQN5f0rNtlJDHIMQYvi+HppW1HdoI+8rpCcmHgGHGO4hsry5VivYWUXGoayUCjqyTkI Zp5gf6AiJGpVp1pabGwqmPluuQC6vVtQySGC8hNlxMkTom2aNBJziK0809/azZKg0rB0 vwIAdWbOSJo2QHNe1udm30DgdPUWlJM54BODlddGFYck7+xspX5btgdzyZbIi6cDzGOZ m7ITRuq5z/vNBGEHf2oQDwC3ShnpmzkohC00/D+JDOg/SHsV9FoX1XvF58k1QI5dzwTJ uw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ut0e68836-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 05 Dec 2023 02:03:57 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 5 Dec 2023 02:00:53 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 5 Dec 2023 02:00:52 -0800 Received: from localhost.localdomain (unknown [10.28.36.154]) by maili.marvell.com (Postfix) with ESMTP id CC1DB3F70A7; Tue, 5 Dec 2023 02:00:50 -0800 (PST) From: Rakesh Kudurumalla To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rakesh Kudurumalla Subject: [PATCH 1/3] common/cnxk: optimize ethdev teardown time Date: Tue, 5 Dec 2023 15:30:46 +0530 Message-ID: <20231205100048.1387058-1-rkudurumalla@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-GUID: bZGVDlOR6Z0D9GwHu1gnAsMqQ91jkp0e X-Proofpoint-ORIG-GUID: bZGVDlOR6Z0D9GwHu1gnAsMqQ91jkp0e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-05_04,2023-12-04_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org API mbox_alloc_msg_npa_aq_enq() mbox is called if SQ needs to be updated from mbox response else mbox call to kernel is bypassed reducing the time taken to complete roc_nix_tm_sq_aura_fc() function.This reduces ethdev teardown time by 20%. Signed-off-by: Rakesh Kudurumalla --- drivers/common/cnxk/roc_nix_tm_ops.c | 29 ++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index e1cef7a670..2c53472047 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -51,25 +51,26 @@ roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable) goto exit; /* Read back npa aura ctx */ - req = mbox_alloc_msg_npa_aq_enq(mbox); - if (req == NULL) { - rc = -ENOSPC; - goto exit; - } + if (enable) { + req = mbox_alloc_msg_npa_aq_enq(mbox); + if (req == NULL) { + rc = -ENOSPC; + goto exit; + } - req->aura_id = roc_npa_aura_handle_to_aura(aura_handle); - req->ctype = NPA_AQ_CTYPE_AURA; - req->op = NPA_AQ_INSTOP_READ; + req->aura_id = roc_npa_aura_handle_to_aura(aura_handle); + req->ctype = NPA_AQ_CTYPE_AURA; + req->op = NPA_AQ_INSTOP_READ; - rc = mbox_process_msg(mbox, (void *)&rsp); - if (rc) - goto exit; + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + goto exit; - /* Init when enabled as there might be no triggers */ - if (enable) + /* Init when enabled as there might be no triggers */ *(volatile uint64_t *)sq->fc = rsp->aura.count; - else + } else { *(volatile uint64_t *)sq->fc = sq->aura_sqb_bufs; + } /* Sync write barrier */ plt_wmb(); rc = 0; From patchwork Tue Dec 5 10:00:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rakesh Kudurumalla X-Patchwork-Id: 134875 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6E7C943676; Tue, 5 Dec 2023 11:04:05 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 716ED42E1E; Tue, 5 Dec 2023 11:04:03 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3D78342E1E for ; Tue, 5 Dec 2023 11:04:01 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3B59ThF1007127 for ; Tue, 5 Dec 2023 02:04:00 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=zT2iiqwqyly+0YG5oSDJh2BJIWNbYvxf3CMOPOg1cVM=; b=YTNc1+iz/IhEhv7SFnM5+EKAWAs16INyThKIQ/TbSpfl1ZeWlpwzmXcLVUP8BgcYQpjN ebpyR26mTApxXe4565A6WXlkFPiN+IYlhrtf4oH3Gw6LS14GDzMjShjEnDcy6SAzBI7W ns74hnFqQHwp3LB0Zp2OW8xWARvjGPz891+H/2Tmc+dj+EQ5g7UiZh2w7fz4MEm+me81 f/SDl0SdP3liWUsXCrDjBEANYNKP0NCaAiW/XIpomG/33bB/5k438fk5iuP6AJsVuMtk b2AuMe+gWz13o0Zl3HAOLRN+y9chXmUA4oobG/f9XzWhyymM9yuJclFOseBhEn6gbfS3 uw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ut0e68836-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 05 Dec 2023 02:03:59 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 5 Dec 2023 02:00:57 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 5 Dec 2023 02:00:56 -0800 Received: from localhost.localdomain (unknown [10.28.36.154]) by maili.marvell.com (Postfix) with ESMTP id 74D633F70A7; Tue, 5 Dec 2023 02:00:54 -0800 (PST) From: Rakesh Kudurumalla To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rakesh Kudurumalla Subject: [PATCH 2/3] common/cnxk: added new API to enable disable SQ Date: Tue, 5 Dec 2023 15:30:47 +0530 Message-ID: <20231205100048.1387058-2-rkudurumalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231205100048.1387058-1-rkudurumalla@marvell.com> References: <20231205100048.1387058-1-rkudurumalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: RreRbj4G_d7-EWqCZfshTaJZbPNPQPUz X-Proofpoint-ORIG-GUID: RreRbj4G_d7-EWqCZfshTaJZbPNPQPUz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-05_04,2023-12-04_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added a new roc API to disable SQB aura FC and update SQ state to disabled state in TX queue stop.The same SQ status is verified during sq flush to enable or disable SQB aura FC during ethdev teardown.This fix reduces teardown time by 90%. Signed-off-by: Rakesh Kudurumalla --- drivers/common/cnxk/roc_nix.h | 2 ++ drivers/common/cnxk/roc_nix_queue.c | 15 +++++++++++++++ drivers/common/cnxk/roc_nix_tm.c | 20 ++++++++++++-------- drivers/common/cnxk/version.map | 1 + 4 files changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index a96cf73757..82997c38ce 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -401,6 +401,7 @@ struct roc_nix_sq { void *sqe_mem; void *fc; uint8_t tc; + bool enable; }; struct roc_nix_link_info { @@ -952,6 +953,7 @@ void __roc_api roc_nix_cq_head_tail_get(struct roc_nix *roc_nix, uint16_t qid, uint32_t *head, uint32_t *tail); int __roc_api roc_nix_sq_init(struct roc_nix *roc_nix, struct roc_nix_sq *sq); int __roc_api roc_nix_sq_fini(struct roc_nix_sq *sq); +int __roc_api roc_nix_sq_ena_dis(struct roc_nix_sq *sq, bool enable); void __roc_api roc_nix_sq_head_tail_get(struct roc_nix *roc_nix, uint16_t qid, uint32_t *head, uint32_t *tail); diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index f96d5c3a96..ae4e0ea40c 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -92,6 +92,20 @@ nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable) return rc; } +int +roc_nix_sq_ena_dis(struct roc_nix_sq *sq, bool enable) +{ + int rc = 0; + + rc = roc_nix_tm_sq_aura_fc(sq, enable); + if (rc) + goto done; + + sq->enable = enable; +done: + return rc; +} + int roc_nix_rq_ena_dis(struct roc_nix_rq *rq, bool enable) { @@ -1409,6 +1423,7 @@ roc_nix_sq_init(struct roc_nix *roc_nix, struct roc_nix_sq *sq) } mbox_put(mbox); + sq->enable = true; nix->sqs[qid] = sq; sq->io_addr = nix->base + NIX_LF_OP_SENDX(0); /* Evenly distribute LMT slot for each sq */ diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c index ece88b5e99..6a61e448a1 100644 --- a/drivers/common/cnxk/roc_nix_tm.c +++ b/drivers/common/cnxk/roc_nix_tm.c @@ -887,10 +887,12 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq) if (!sq) continue; - rc = roc_nix_tm_sq_aura_fc(sq, false); - if (rc) { - plt_err("Failed to disable sqb aura fc, rc=%d", rc); - goto cleanup; + if (sq->enable) { + rc = roc_nix_tm_sq_aura_fc(sq, false); + if (rc) { + plt_err("Failed to disable sqb aura fc, rc=%d", rc); + goto cleanup; + } } /* Wait for sq entries to be flushed */ @@ -997,10 +999,12 @@ nix_tm_sq_flush_post(struct roc_nix_sq *sq) once = true; } - rc = roc_nix_tm_sq_aura_fc(s_sq, true); - if (rc) { - plt_err("Failed to enable sqb aura fc, rc=%d", rc); - return rc; + if (s_sq->enable) { + rc = roc_nix_tm_sq_aura_fc(s_sq, true); + if (rc) { + plt_err("Failed to enable sqb aura fc, rc=%d", rc); + return rc; + } } } diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index aa884a8fe2..4907b62013 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -339,6 +339,7 @@ INTERNAL { roc_nix_rx_queue_intr_disable; roc_nix_rx_queue_intr_enable; roc_nix_sq_dump; + roc_nix_sq_ena_dis; roc_nix_sq_fini; roc_nix_sq_head_tail_get; roc_nix_sq_init; From patchwork Tue Dec 5 10:00:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rakesh Kudurumalla X-Patchwork-Id: 134876 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 96DA143676; Tue, 5 Dec 2023 11:09:00 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 487D9402C8; Tue, 5 Dec 2023 11:09:00 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4F91C40275 for ; Tue, 5 Dec 2023 11:08:59 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3B5A3qAp012032 for ; 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Tue, 5 Dec 2023 02:01:00 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 5 Dec 2023 02:01:00 -0800 Received: from localhost.localdomain (unknown [10.28.36.154]) by maili.marvell.com (Postfix) with ESMTP id F2A6C3F7045; Tue, 5 Dec 2023 02:00:57 -0800 (PST) From: Rakesh Kudurumalla To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rakesh Kudurumalla Subject: [PATCH 3/3] net/cnxk: reduce Tx queue release time Date: Tue, 5 Dec 2023 15:30:48 +0530 Message-ID: <20231205100048.1387058-3-rkudurumalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231205100048.1387058-1-rkudurumalla@marvell.com> References: <20231205100048.1387058-1-rkudurumalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ZTYuMBRZRs6yqMMcHCPz1i6BQ4Y2qNDN X-Proofpoint-ORIG-GUID: ZTYuMBRZRs6yqMMcHCPz1i6BQ4Y2qNDN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-05_04,2023-12-04_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Invoked newly added roc API to disable SQB aura FC during TX queue start and TX queue stop. This fix reduces ethdev teardown time Signed-off-by: Rakesh Kudurumalla --- drivers/net/cnxk/cnxk_ethdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 5e11bbb017..2372a4e793 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1521,7 +1521,7 @@ cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid) if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED) return 0; - rc = roc_nix_tm_sq_aura_fc(sq, true); + rc = roc_nix_sq_ena_dis(sq, true); if (rc) { plt_err("Failed to enable sq aura fc, txq=%u, rc=%d", qid, rc); goto done; @@ -1543,7 +1543,7 @@ cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid) if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED) return 0; - rc = roc_nix_tm_sq_aura_fc(sq, false); + rc = roc_nix_sq_ena_dis(sq, false); if (rc) { plt_err("Failed to disable sqb aura fc, txq=%u, rc=%d", qid, rc);