From patchwork Thu Dec 7 13:46:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rakesh Kudurumalla X-Patchwork-Id: 134927 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B9BDF43699; Thu, 7 Dec 2023 14:47:00 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 42D4740278; Thu, 7 Dec 2023 14:47:00 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id D798440270 for ; Thu, 7 Dec 2023 14:46:58 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3B76M9B5017113 for ; Thu, 7 Dec 2023 05:46:57 -0800 DKIM-Signature: v=1; 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Thu, 7 Dec 2023 05:46:55 -0800 Received: from localhost.localdomain (unknown [10.28.36.154]) by maili.marvell.com (Postfix) with ESMTP id 785563F7051; Thu, 7 Dec 2023 05:46:53 -0800 (PST) From: Rakesh Kudurumalla To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rakesh Kudurumalla Subject: [PATCH v2 1/2] common/cnxk: support to dump debug info to file Date: Thu, 7 Dec 2023 19:16:50 +0530 Message-ID: <20231207134651.1718457-1-rkudurumalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231205094539.1377142-1-rkudurumalla@marvell.com> References: <20231205094539.1377142-1-rkudurumalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: HfStj2v_95dvA4-AoMJv3B46Tw4Rj0z_ X-Proofpoint-ORIG-GUID: HfStj2v_95dvA4-AoMJv3B46Tw4Rj0z_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-07_11,2023-12-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch dumps contents of receviced packet descriptor from CQ for debug to file Signed-off-by: Rakesh Kudurumalla --- V2: Resolve Warnings drivers/common/cnxk/roc_cpt.h | 2 +- drivers/common/cnxk/roc_cpt_debug.c | 56 +++++++++++++++++------------ drivers/common/cnxk/roc_nix.h | 2 +- drivers/common/cnxk/roc_nix_debug.c | 3 +- 4 files changed, 36 insertions(+), 27 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 787bccb27d..523a5964a3 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -191,7 +191,7 @@ void __roc_api roc_cpt_iq_enable(struct roc_cpt_lf *lf); int __roc_api roc_cpt_lmtline_init(struct roc_cpt *roc_cpt, struct roc_cpt_lmtline *lmtline, int lf_id); -void __roc_api roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth); +void __roc_api roc_cpt_parse_hdr_dump(FILE *file, const struct cpt_parse_hdr_s *cpth); int __roc_api roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, uint16_t sa_len); diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c index dce3638507..8e69b0a0e5 100644 --- a/drivers/common/cnxk/roc_cpt_debug.c +++ b/drivers/common/cnxk/roc_cpt_debug.c @@ -5,38 +5,48 @@ #include "roc_api.h" #include "roc_priv.h" +#define cpt_dump(file, fmt, ...) do { \ + if ((file) == NULL) \ + plt_dump(fmt, ##__VA_ARGS__); \ + else \ + fprintf(file, fmt "\n", ##__VA_ARGS__); \ +} while (0) + void -roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth) +roc_cpt_parse_hdr_dump(FILE *file, const struct cpt_parse_hdr_s *cpth) { struct cpt_frag_info_s *frag_info; uint32_t offset; uint64_t *slot; - plt_print("CPT_PARSE \t0x%p:", cpth); + cpt_dump(file, "CPT_PARSE \t0x%p:", cpth); /* W0 */ - plt_print("W0: cookie \t0x%x\t\tmatch_id \t0x%04x\t\terr_sum \t%u \t", - cpth->w0.cookie, cpth->w0.match_id, cpth->w0.err_sum); - plt_print("W0: reas_sts \t0x%x\t\tet_owr \t%u\t\tpkt_fmt \t%u \t", + cpt_dump(file, "W0: cookie \t0x%x\t\tmatch_id \t0x%04x \t", + cpth->w0.cookie, cpth->w0.match_id); + cpt_dump(file, "W0: err_sum \t%u \t", cpth->w0.err_sum); + cpt_dump(file, "W0: reas_sts \t0x%x\t\tet_owr \t%u\t\tpkt_fmt \t%u \t", cpth->w0.reas_sts, cpth->w0.et_owr, cpth->w0.pkt_fmt); - plt_print("W0: pad_len \t%u\t\tnum_frags \t%u\t\tpkt_out \t%u \t", + cpt_dump(file, "W0: pad_len \t%u\t\tnum_frags \t%u\t\tpkt_out \t%u \t", cpth->w0.pad_len, cpth->w0.num_frags, cpth->w0.pkt_out); /* W1 */ - plt_print("W1: wqe_ptr \t0x%016lx\t", plt_be_to_cpu_64(cpth->wqe_ptr)); + cpt_dump(file, "W1: wqe_ptr \t0x%016lx\t", + plt_be_to_cpu_64(cpth->wqe_ptr)); /* W2 */ - plt_print("W2: frag_age \t0x%x\t\torig_pf_func \t0x%04x", + cpt_dump(file, "W2: frag_age \t0x%x\t\torig_pf_func \t0x%04x", cpth->w2.frag_age, cpth->w2.orig_pf_func); - plt_print("W2: il3_off \t0x%x\t\tfi_pad \t0x%x\t\tfi_offset \t0x%x \t", - cpth->w2.il3_off, cpth->w2.fi_pad, cpth->w2.fi_offset); + cpt_dump(file, "W2: il3_off \t0x%x\t\tfi_pad \t0x%x \t", + cpth->w2.il3_off, cpth->w2.fi_pad); + cpt_dump(file, "W2: fi_offset \t0x%x \t", cpth->w2.fi_offset); /* W3 */ - plt_print("W3: hw_ccode \t0x%x\t\tuc_ccode \t0x%x\t\tspi \t0x%08x", + cpt_dump(file, "W3: hw_ccode \t0x%x\t\tuc_ccode \t0x%x\t\tspi \t0x%08x", cpth->w3.hw_ccode, cpth->w3.uc_ccode, cpth->w3.spi); /* W4 */ - plt_print("W4: esn \t%" PRIx64 " \t OR frag1_wqe_ptr \t0x%" PRIx64, + cpt_dump(file, "W4: esn \t%" PRIx64 " \t OR frag1_wqe_ptr \t0x%" PRIx64, cpth->esn, plt_be_to_cpu_64(cpth->frag1_wqe_ptr)); /* offset of 0 implies 256B, otherwise it implies offset*8B */ @@ -44,24 +54,24 @@ roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth) offset = (((offset - 1) & 0x1f) + 1) * 8; frag_info = PLT_PTR_ADD(cpth, offset); - plt_print("CPT Fraginfo \t0x%p:", frag_info); + cpt_dump(file, "CPT Fraginfo \t0x%p:", frag_info); /* W0 */ - plt_print("W0: f0.info \t0x%x", frag_info->w0.f0.info); - plt_print("W0: f1.info \t0x%x", frag_info->w0.f1.info); - plt_print("W0: f2.info \t0x%x", frag_info->w0.f2.info); - plt_print("W0: f3.info \t0x%x", frag_info->w0.f3.info); + cpt_dump(file, "W0: f0.info \t0x%x", frag_info->w0.f0.info); + cpt_dump(file, "W0: f1.info \t0x%x", frag_info->w0.f1.info); + cpt_dump(file, "W0: f2.info \t0x%x", frag_info->w0.f2.info); + cpt_dump(file, "W0: f3.info \t0x%x", frag_info->w0.f3.info); /* W1 */ - plt_print("W1: frag_size0 \t0x%x", frag_info->w1.frag_size0); - plt_print("W1: frag_size1 \t0x%x", frag_info->w1.frag_size1); - plt_print("W1: frag_size2 \t0x%x", frag_info->w1.frag_size2); - plt_print("W1: frag_size3 \t0x%x", frag_info->w1.frag_size3); + cpt_dump(file, "W1: frag_size0 \t0x%x", frag_info->w1.frag_size0); + cpt_dump(file, "W1: frag_size1 \t0x%x", frag_info->w1.frag_size1); + cpt_dump(file, "W1: frag_size2 \t0x%x", frag_info->w1.frag_size2); + cpt_dump(file, "W1: frag_size3 \t0x%x", frag_info->w1.frag_size3); slot = (uint64_t *)(frag_info + 1); - plt_print("Frag Slot2: WQE ptr \t%p", + cpt_dump(file, "Frag Slot2: WQE ptr \t%p", (void *)plt_be_to_cpu_64(slot[0])); - plt_print("Frag Slot3: WQE ptr \t%p", + cpt_dump(file, "Frag Slot3: WQE ptr \t%p", (void *)plt_be_to_cpu_64(slot[1])); } diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index cc650124ed..82997c38ce 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -549,7 +549,7 @@ int __roc_api roc_nix_rx_drop_re_set(struct roc_nix *roc_nix, bool ena); int __roc_api roc_nix_lf_get_reg_count(struct roc_nix *roc_nix); int __roc_api roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data); int __roc_api roc_nix_queues_ctx_dump(struct roc_nix *roc_nix, FILE *file); -void __roc_api roc_nix_cqe_dump(const struct nix_cqe_hdr_s *cq); +void __roc_api roc_nix_cqe_dump(FILE *file, const struct nix_cqe_hdr_s *cq); void __roc_api roc_nix_rq_dump(struct roc_nix_rq *rq, FILE *file); void __roc_api roc_nix_cq_dump(struct roc_nix_cq *cq, FILE *file); void __roc_api roc_nix_sq_dump(struct roc_nix_sq *sq, FILE *file); diff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c index 8c7d902f1e..8962a76097 100644 --- a/drivers/common/cnxk/roc_nix_debug.c +++ b/drivers/common/cnxk/roc_nix_debug.c @@ -808,9 +808,8 @@ roc_nix_queues_ctx_dump(struct roc_nix *roc_nix, FILE *file) /* Dumps struct nix_cqe_hdr_s and union nix_rx_parse_u */ void -roc_nix_cqe_dump(const struct nix_cqe_hdr_s *cq) +roc_nix_cqe_dump(FILE *file, const struct nix_cqe_hdr_s *cq) { - FILE *file = NULL; const union nix_rx_parse_u *rx = (const union nix_rx_parse_u *)((const uint64_t *)cq + 1); const uint64_t *sgs = (const uint64_t *)(rx + 1); From patchwork Thu Dec 7 13:46:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rakesh Kudurumalla X-Patchwork-Id: 134928 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 62D9B43699; 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Thu, 07 Dec 2023 05:47:03 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 7 Dec 2023 05:47:00 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 7 Dec 2023 05:47:00 -0800 Received: from localhost.localdomain (unknown [10.28.36.154]) by maili.marvell.com (Postfix) with ESMTP id DA6D03F7051; Thu, 7 Dec 2023 05:46:57 -0800 (PST) From: Rakesh Kudurumalla To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rakesh Kudurumalla Subject: [PATCH v2 2/2] net/cnxk: dump Rx descriptor info to file Date: Thu, 7 Dec 2023 19:16:51 +0530 Message-ID: <20231207134651.1718457-2-rkudurumalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231207134651.1718457-1-rkudurumalla@marvell.com> References: <20231205094539.1377142-1-rkudurumalla@marvell.com> <20231207134651.1718457-1-rkudurumalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: yC0u5Pt_8HW_zylBukVp_QUSgdaBS7HE X-Proofpoint-GUID: yC0u5Pt_8HW_zylBukVp_QUSgdaBS7HE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-07_11,2023-12-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for eth_rx_descriptor_dump for cn9k and cn10k. This patch dumps contents of receviced packet descriptor from CQ for debug to file Signed-off-by: Rakesh Kudurumalla --- drivers/net/cnxk/cn10k_ethdev.c | 67 +++++++++++++++++++++++++++++++++ drivers/net/cnxk/cn9k_ethdev.c | 53 ++++++++++++++++++++++++++ 2 files changed, 120 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index 4a4e97287c..a2e943a3d0 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -656,6 +656,72 @@ cn10k_nix_reassembly_conf_set(struct rte_eth_dev *eth_dev, return rc; } +static int +cn10k_nix_rx_avail_get(struct cn10k_eth_rxq *rxq) +{ + uint32_t qmask = rxq->qmask; + uint64_t reg, head, tail; + int available; + + /* Use LDADDA version to avoid reorder */ + reg = roc_atomic64_add_sync(rxq->wdata, rxq->cq_status); + /* CQ_OP_STATUS operation error */ + if (reg & BIT_ULL(NIX_CQ_OP_STAT_OP_ERR) || + reg & BIT_ULL(NIX_CQ_OP_STAT_CQ_ERR)) + return 0; + tail = reg & 0xFFFFF; + head = (reg >> 20) & 0xFFFFF; + if (tail < head) + available = tail - head + qmask + 1; + else + available = tail - head; + + return available; +} + +static int +cn10k_rx_descriptor_dump(const struct rte_eth_dev *eth_dev, uint16_t qid, + uint16_t offset, uint16_t num, FILE *file) +{ + struct cn10k_eth_rxq *rxq = eth_dev->data->rx_queues[qid]; + const uint64_t data_off = rxq->data_off; + const uint32_t qmask = rxq->qmask; + const uintptr_t desc = rxq->desc; + struct cpt_parse_hdr_s *cpth; + uint32_t head = rxq->head; + struct nix_cqe_hdr_s *cq; + uint16_t count = 0; + int available_pkts; + uint64_t cq_w1; + + available_pkts = cn10k_nix_rx_avail_get(rxq); + + if ((offset + num - 1) >= available_pkts) { + plt_err("Invalid BD num=%u\n", num); + return -EINVAL; + } + + while (count < num) { + cq = (struct nix_cqe_hdr_s *)(desc + CQE_SZ(head) + + count + offset); + cq_w1 = *((const uint64_t *)cq + 1); + if (cq_w1 & BIT(11)) { + rte_iova_t buff = *((rte_iova_t *)((uint64_t *)cq + 9)); + struct rte_mbuf *mbuf = + (struct rte_mbuf *)(buff - data_off); + cpth = (struct cpt_parse_hdr_s *) + ((uintptr_t)mbuf + (uint16_t)data_off); + roc_cpt_parse_hdr_dump(file, cpth); + } else { + roc_nix_cqe_dump(file, cq); + } + + count++; + head &= qmask; + } + return 0; +} + static int cn10k_nix_tm_mark_vlan_dei(struct rte_eth_dev *eth_dev, int mark_green, int mark_yellow, int mark_red, @@ -794,6 +860,7 @@ nix_eth_dev_ops_override(void) cn10k_nix_reassembly_capability_get; cnxk_eth_dev_ops.ip_reassembly_conf_get = cn10k_nix_reassembly_conf_get; cnxk_eth_dev_ops.ip_reassembly_conf_set = cn10k_nix_reassembly_conf_set; + cnxk_eth_dev_ops.eth_rx_descriptor_dump = cn10k_rx_descriptor_dump; } /* Update platform specific tm ops */ diff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c index bae4dda5e2..67f21a9c7f 100644 --- a/drivers/net/cnxk/cn9k_ethdev.c +++ b/drivers/net/cnxk/cn9k_ethdev.c @@ -664,6 +664,58 @@ cn9k_nix_tm_mark_ip_dscp(struct rte_eth_dev *eth_dev, int mark_green, return rc; } +static int +cn9k_nix_rx_avail_get(struct cn9k_eth_rxq *rxq) +{ + uint32_t qmask = rxq->qmask; + uint64_t reg, head, tail; + int available; + + /* Use LDADDA version to avoid reorder */ + reg = roc_atomic64_add_sync(rxq->wdata, rxq->cq_status); + /* CQ_OP_STATUS operation error */ + if (reg & BIT_ULL(NIX_CQ_OP_STAT_OP_ERR) || + reg & BIT_ULL(NIX_CQ_OP_STAT_CQ_ERR)) + return 0; + tail = reg & 0xFFFFF; + head = (reg >> 20) & 0xFFFFF; + if (tail < head) + available = tail - head + qmask + 1; + else + available = tail - head; + + return available; +} + +static int +cn9k_rx_descriptor_dump(const struct rte_eth_dev *eth_dev, uint16_t qid, + uint16_t offset, uint16_t num, FILE *file) +{ + struct cn9k_eth_rxq *rxq = eth_dev->data->rx_queues[qid]; + const uint32_t qmask = rxq->qmask; + const uintptr_t desc = rxq->desc; + uint32_t head = rxq->head; + struct nix_cqe_hdr_s *cq; + uint16_t count = 0; + int available_pkts; + + available_pkts = cn9k_nix_rx_avail_get(rxq); + + if ((offset + num - 1) >= available_pkts) { + plt_err("Invalid BD num=%u\n", num); + return -EINVAL; + } + + while (count < num) { + cq = (struct nix_cqe_hdr_s *)(desc + CQE_SZ(head) + + count + offset); + roc_nix_cqe_dump(file, cq); + count++; + head &= qmask; + } + return 0; +} + /* Update platform specific eth dev ops */ static void nix_eth_dev_ops_override(void) @@ -687,6 +739,7 @@ nix_eth_dev_ops_override(void) cnxk_eth_dev_ops.mtr_ops_get = NULL; cnxk_eth_dev_ops.timesync_read_tx_timestamp = cn9k_nix_timesync_read_tx_timestamp; + cnxk_eth_dev_ops.eth_rx_descriptor_dump = cn9k_rx_descriptor_dump; } /* Update platform specific eth dev ops */