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Wed, 28 Feb 2024 01:51:04 -0800 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , , , Erez Shitrit Subject: [PATCH] net/mlx5/hws: enable multiple integrity items Date: Wed, 28 Feb 2024 11:50:55 +0200 Message-ID: <20240228095055.3108270-1-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE7:EE_|SA0PR12MB7479:EE_ X-MS-Office365-Filtering-Correlation-Id: d63787b9-5988-4ebb-c5cc-08dc3842d12d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gpPGRN+J91OZuTq5p2fDykQC+jcp/PcrfHX2Oy3jfo4vK8qVTheekaVfLlBomygADQhhzJzcztQoidWC9iqpPiIiv66R6FpjWZaW4F0MzFYDLN4n8E7bwOBLc5qHk20HxN+0fIpJCpATz/M9IMUA/pSqPNJ+Y+bQXofswugX8f82QnZj66AEys8OieL1x4QvxvpQSA4uByY5P3v8N6lWqPd9XEdA9favCIsqUTQ4E+G1CKvR7ySd04VUB0dGVV/Y1VR2GaDx/n/S9E5FTnrWJ9h0Ln6jOv5G5ISPwxAfiLFwLq7h3v7jqP/opbG27SmOg9oO5MzHaJ64QKiQmInYy8kmckE9i6kT9mApLoNwAq3QdcTMZNdYPFwSxfAsZYnfGjQRL1AY6E9GTaxSPQ9FcGJLuoC0kPtUL2+oa4mbsmHTARgojLavXbDoAOdsjSQ7YH5CMt/qGq+hx9sZ3MnBMSWu5phA/hZa1xUxTkPOHOgi3jMzAalHk51UW+xTwBhfos4cgk8C4FiEX0a66WOe5+GX9n9DxrF+GD/xQ50dCMtzaP+SLNUxlCTdr+YQLSMjnx4ya9cjz5XEVxG+qhQrmO7PlDvExeCdtPcMbWmGx3HQTdrFzzOVBPgVqjWuAWAN8m1flyAkFYGHJunRyDk1i3ZffdiqRixxH+5l49bZJnfPbhGAyVe/mh6G2G4Hl8GpFqmx2eUnPIfsadASmQ80DrGlDxx0M5j2IlMg5Qm9YRGAZ9ZJF1LiayFEzIM0lBFP X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(82310400014)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2024 09:51:20.7108 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d63787b9-5988-4ebb-c5cc-08dc3842d12d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7479 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The integrity item uses the DW "oks1" in header layout. It includes the all supported bits for both inner and outer. When item is integrity type, the relevant bits are turned on and all DW is submitted. When user provides more then single integrity item in same pattern, the last one overrides the values were submitted before. This is problematic when user wants to match integrity bits for both inner and outer in same pattern, he cannot merge them into single item since rte_flow API provides encapsulation level field to match either inner or outer. This patch avoids the overriding values, when "oks1" is submitted, operator "or" is used instead of regular set. Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer") Cc: valex@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Reviewed-by: Erez Shitrit Acked-by: Matan Azrad --- drivers/net/mlx5/hws/mlx5dr_definer.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index e036aca781..0e15aafb8a 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -44,6 +44,10 @@ (bit_off))); \ } while (0) +/* Getter function based on bit offset and mask, for 32bit DW*/ +#define DR_GET_32(p, byte_off, bit_off, mask) \ + ((rte_be_to_cpu_32(*((const rte_be32_t *)(p) + ((byte_off) / 4))) >> (bit_off)) & (mask)) + /* Setter function based on bit offset and mask */ #define DR_SET(p, v, byte_off, bit_off, mask) \ do { \ @@ -509,7 +513,7 @@ mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc, { bool inner = (fc->fname == MLX5DR_DEFINER_FNAME_INTEGRITY_I); const struct rte_flow_item_integrity *v = item_spec; - uint32_t ok1_bits = 0; + uint32_t ok1_bits = DR_GET_32(tag, fc->byte_off, fc->bit_off, fc->bit_mask); if (v->l3_ok) ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) :