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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230034)(36860700007)(376008)(1800799018)(82310400020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2024 16:25:06.1885 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad773a1a-33e1-4c0d-2d86-08dc8afc3868 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8830 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Extract code responsible for validation if port specified in configuration of RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT action is correct. Allow for reuse of this logic for both RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT actions and RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT items. Signed-off-by: Dariusz Sosnowski Acked-by: Ori Kam --- drivers/net/mlx5/mlx5_flow_hw.c | 63 +++++++++++++++++++++------------ 1 file changed, 40 insertions(+), 23 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index eb89dcf454..aee0201cbc 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -6046,6 +6046,42 @@ flow_hw_validate_action_port_representor(struct rte_eth_dev *dev __rte_unused, return 0; } +static int +flow_hw_validate_target_port_id(struct rte_eth_dev *dev, + uint16_t target_port_id) +{ + struct mlx5_priv *port_priv; + struct mlx5_priv *dev_priv; + + if (target_port_id == MLX5_REPRESENTED_PORT_ESW_MGR) + return 0; + + port_priv = mlx5_port_to_eswitch_info(target_port_id, false); + if (!port_priv) { + rte_errno = EINVAL; + DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for port %u", + dev->data->port_id, target_port_id); + return -rte_errno; + } + + dev_priv = mlx5_dev_to_eswitch_info(dev); + if (!dev_priv) { + rte_errno = EINVAL; + DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy", + dev->data->port_id); + return -rte_errno; + } + + if (port_priv->domain_id != dev_priv->domain_id) { + rte_errno = EINVAL; + DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy", + dev->data->port_id); + return -rte_errno; + } + + return 0; +} + static int flow_hw_validate_action_represented_port(struct rte_eth_dev *dev, const struct rte_flow_action *action, @@ -6062,32 +6098,13 @@ flow_hw_validate_action_represented_port(struct rte_eth_dev *dev, "cannot use represented_port actions" " without an E-Switch"); if (mask_conf && mask_conf->port_id) { - struct mlx5_priv *port_priv; - struct mlx5_priv *dev_priv; - if (!action_conf) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, "port index was not provided"); - port_priv = mlx5_port_to_eswitch_info(action_conf->port_id, false); - if (!port_priv) - return rte_flow_error_set(error, rte_errno, - RTE_FLOW_ERROR_TYPE_ACTION, - action, - "failed to obtain E-Switch" - " info for port"); - dev_priv = mlx5_dev_to_eswitch_info(dev); - if (!dev_priv) - return rte_flow_error_set(error, rte_errno, - RTE_FLOW_ERROR_TYPE_ACTION, - action, - "failed to obtain E-Switch" - " info for transfer proxy"); - if (port_priv->domain_id != dev_priv->domain_id) - return rte_flow_error_set(error, rte_errno, - RTE_FLOW_ERROR_TYPE_ACTION, - action, - "cannot forward to port from" - " a different E-Switch"); + + if (flow_hw_validate_target_port_id(dev, action_conf->port_id)) + return rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION, + action, "port index is invalid"); } return 0; } From patchwork Wed Jun 12 16:24:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 141113 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9C6A341F45; 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Signed-off-by: Dariusz Sosnowski Acked-by: Ori Kam --- drivers/net/mlx5/mlx5_flow.c | 59 +++++++++++++++++++++++++----------- drivers/net/mlx5/mlx5_flow.h | 3 ++ 2 files changed, 44 insertions(+), 18 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 7bcbbc74b5..5374c95954 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -2020,6 +2020,46 @@ mlx5_flow_validate_action_drop(struct rte_eth_dev *dev, return 0; } +/* + * Check if a queue specified in the queue action is valid. + * + * @param[in] dev + * Pointer to the Ethernet device structure. + * @param[in] action + * Pointer to the queue action. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_flow_validate_target_queue(struct rte_eth_dev *dev, + const struct rte_flow_action *action, + struct rte_flow_error *error) +{ + const struct rte_flow_action_queue *queue = action->conf; + struct mlx5_priv *priv = dev->data->dev_private; + + if (mlx5_is_external_rxq(dev, queue->index)) + return 0; + if (!priv->rxqs_n) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION_CONF, + NULL, "No Rx queues configured"); + if (queue->index >= priv->rxqs_n) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION_CONF, + &queue->index, + "queue index out of range"); + if (mlx5_rxq_get(dev, queue->index) == NULL) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION_CONF, + &queue->index, + "queue is not configured"); + return 0; +} + /* * Validate the queue action. * @@ -2044,7 +2084,6 @@ mlx5_flow_validate_action_queue(const struct rte_flow_action *action, const struct rte_flow_attr *attr, struct rte_flow_error *error) { - struct mlx5_priv *priv = dev->data->dev_private; const struct rte_flow_action_queue *queue = action->conf; if (!queue) @@ -2060,23 +2099,7 @@ mlx5_flow_validate_action_queue(const struct rte_flow_action *action, return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, "queue action not supported for egress."); - if (mlx5_is_external_rxq(dev, queue->index)) - return 0; - if (!priv->rxqs_n) - return rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_ACTION_CONF, - NULL, "No Rx queues configured"); - if (queue->index >= priv->rxqs_n) - return rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_ACTION_CONF, - &queue->index, - "queue index out of range"); - if (mlx5_rxq_get(dev, queue->index) == NULL) - return rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_ACTION_CONF, - &queue->index, - "queue is not configured"); - return 0; + return mlx5_flow_validate_target_queue(dev, action, error); } /** diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 92e2ecedb3..da7d06d033 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -3018,6 +3018,9 @@ int mlx5_flow_validate_action_mark(struct rte_eth_dev *dev, uint64_t action_flags, const struct rte_flow_attr *attr, struct rte_flow_error *error); +int mlx5_flow_validate_target_queue(struct rte_eth_dev *dev, + const struct rte_flow_action *action, + struct rte_flow_error *error); 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This allows validation of items, provided by the user during flow rule creation, against pattern template. Signed-off-by: Dariusz Sosnowski Acked-by: Ori Kam --- drivers/net/mlx5/mlx5_flow.h | 2 ++ drivers/net/mlx5/mlx5_flow_hw.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index da7d06d033..5c2cc2b7c1 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1522,6 +1522,8 @@ struct rte_flow_pattern_template { /* Manages all GENEVE TLV options used by this pattern template. */ struct mlx5_geneve_tlv_options_mng geneve_opt_mng; uint8_t flex_item; /* flex item index. */ + /* Items on which this pattern template is based on. */ + struct rte_flow_item *items; }; /* Flow action template struct. */ diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index aee0201cbc..0ddae54ed2 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -8767,6 +8767,7 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev, .mask = &tag_m, .last = NULL }; + int it_items_size; unsigned int i = 0; int rc; @@ -8810,6 +8811,31 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev, it->attr = *attr; it->item_flags = item_flags; it->orig_item_nb = orig_item_nb; + it_items_size = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, NULL, 0, tmpl_items, error); + if (it_items_size <= 0) { + rte_flow_error_set(error, ENOMEM, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "Failed to determine buffer size for pattern"); + goto error; + } + it_items_size = RTE_ALIGN(it_items_size, 16); + it->items = mlx5_malloc(MLX5_MEM_ZERO, it_items_size, 0, rte_dev_numa_node(dev->device)); + if (it->items == NULL) { + rte_flow_error_set(error, ENOMEM, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "Cannot allocate memory for pattern"); + goto error; + } + rc = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, it->items, it_items_size, tmpl_items, error); + if (rc <= 0) { + rte_flow_error_set(error, ENOMEM, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "Failed to store pattern"); + goto error; + } it->mt = mlx5dr_match_template_create(tmpl_items, attr->relaxed_matching); if (!it->mt) { rte_flow_error_set(error, rte_errno, @@ -8824,6 +8850,7 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev, else if (attr->egress) it->implicit_tag = true; mlx5_free(copied_items); + copied_items = NULL; } /* Either inner or outer, can't both. */ if (it->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT | @@ -8884,6 +8911,7 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev, mlx5_geneve_tlv_options_unregister(priv, &it->geneve_opt_mng); if (it->mt) claim_zero(mlx5dr_match_template_destroy(it->mt)); + mlx5_free(it->items); mlx5_free(it); } if (copied_items) @@ -8926,6 +8954,7 @@ flow_hw_pattern_template_destroy(struct rte_eth_dev *dev, flow_hw_flex_item_release(dev, &template->flex_item); mlx5_geneve_tlv_options_unregister(priv, &template->geneve_opt_mng); claim_zero(mlx5dr_match_template_destroy(template->mt)); + mlx5_free(template->items); mlx5_free(template); return 0; } From patchwork Wed Jun 12 16:24:22 2024 Content-Type: text/plain; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN2PEPF000044A7.mail.protection.outlook.com (10.167.243.101) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7677.15 via Frontend Transport; Wed, 12 Jun 2024 16:25:17 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 12 Jun 2024 09:24:57 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 12 Jun 2024 09:24:55 -0700 From: Dariusz Sosnowski To: Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Matan Azrad CC: Subject: [PATCH v2 4/8] net/mlx5: store original actions in template Date: Wed, 12 Jun 2024 18:24:22 +0200 Message-ID: <20240612162426.978117-5-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240612162426.978117-1-dsosnowski@nvidia.com> References: <20240605183419.489323-1-dsosnowski@nvidia.com> <20240612162426.978117-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A7:EE_|SN7PR12MB7418:EE_ X-MS-Office365-Filtering-Correlation-Id: bdeb6a79-fe78-4e6c-3fad-08dc8afc3f7f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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For example: - RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID actions is replaced with modify field action. - Modify field action is added for preserving metadata between FDB and NIC domains. - Modify field action is added when quota action is used to amend ASO syndrome. Types of actions and their order in flow rules based on some actions template must match the original, not modified one. This patch adds preserving of the original actions for actions template to allow for easier validation of ordering and types on fast path. Signed-off-by: Dariusz Sosnowski Acked-by: Ori Kam --- drivers/net/mlx5/mlx5_flow.h | 1 + drivers/net/mlx5/mlx5_flow_hw.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 5c2cc2b7c1..8e99e76e5d 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1532,6 +1532,7 @@ struct rte_flow_actions_template { /* Template attributes. */ struct rte_flow_actions_template_attr attr; struct rte_flow_action *actions; /* Cached flow actions. */ + struct rte_flow_action *orig_actions; /* Original flow actions. */ struct rte_flow_action *masks; /* Cached action masks.*/ struct mlx5dr_action_template *tmpl; /* mlx5dr action template. */ uint64_t action_flags; /* Bit-map of all valid action in template. */ diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 0ddae54ed2..ddc9cf24d6 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -7745,6 +7745,7 @@ __flow_hw_actions_template_create(struct rte_eth_dev *dev, { struct mlx5_priv *priv = dev->data->dev_private; int len, act_len, mask_len; + int orig_act_len; unsigned int act_num; unsigned int i; struct rte_flow_actions_template *at = NULL; @@ -7862,6 +7863,10 @@ __flow_hw_actions_template_create(struct rte_eth_dev *dev, len += RTE_ALIGN(mask_len, 16); len += RTE_ALIGN(act_num * sizeof(*at->dr_off), 16); len += RTE_ALIGN(act_num * sizeof(*at->src_off), 16); + orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, actions, error); + if (orig_act_len <= 0) + return NULL; + len += RTE_ALIGN(orig_act_len, 16); at = mlx5_malloc(MLX5_MEM_ZERO, len + sizeof(*at), RTE_CACHE_LINE_SIZE, rte_socket_id()); if (!at) { @@ -7889,6 +7894,12 @@ __flow_hw_actions_template_create(struct rte_eth_dev *dev, at->src_off = RTE_PTR_ADD(at->dr_off, RTE_ALIGN(act_num * sizeof(*at->dr_off), 16)); memcpy(at->src_off, src_off, act_num * sizeof(at->src_off[0])); + at->orig_actions = RTE_PTR_ADD(at->src_off, + RTE_ALIGN(act_num * sizeof(*at->src_off), 16)); + orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->orig_actions, orig_act_len, + actions, error); + if (orig_act_len <= 0) + goto error; at->actions_num = act_num; for (i = 0; i < at->actions_num; ++i) at->dr_off[i] = UINT16_MAX; From patchwork Wed Jun 12 16:24:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 141112 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A513B41F45; Wed, 12 Jun 2024 18:25:34 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B95B240151; Wed, 12 Jun 2024 18:25:18 +0200 (CEST) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2048.outbound.protection.outlook.com [40.107.243.48]) by mails.dpdk.org (Postfix) with ESMTP id 69486410E8 for ; Wed, 12 Jun 2024 18:25:17 +0200 (CEST) ARC-Seal: i=1; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230034)(36860700007)(376008)(1800799018)(82310400020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2024 16:25:13.0794 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d4cc57e-21e0-4638-e024-08dc8afc3c7e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7271 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When template table is created, list of unmasked actions is recorded for future flow rule insertions. This patch expands entries for RTE_FLOW_ACTION_TYPE_INDIRECT actions in this list with information about expected indirect action type. This will be used in follow up commits which add flow rule operation validation. Specifically, this will be used to verify if indirect action provided by the user references an action of a correct type. Signed-off-by: Dariusz Sosnowski Acked-by: Ori Kam --- drivers/net/mlx5/mlx5_flow.h | 4 ++++ drivers/net/mlx5/mlx5_flow_hw.c | 22 ++++++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 8e99e76e5d..33847e2272 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1442,6 +1442,10 @@ struct mlx5_action_construct_data { uint16_t action_dst; /* mlx5dr_rule_action dst offset. */ indirect_list_callback_t indirect_list_cb; union { + struct { + /* Expected type of indirection action. */ + enum rte_flow_action_type expected_type; + } indirect; struct { /* encap data len. */ uint16_t len; diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index ddc9cf24d6..21a885517a 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -997,6 +997,24 @@ __flow_hw_act_data_general_append(struct mlx5_priv *priv, return 0; } +static __rte_always_inline int +__flow_hw_act_data_indirect_append(struct mlx5_priv *priv, + struct mlx5_hw_actions *acts, + enum rte_flow_action_type type, + enum rte_flow_action_type mask_type, + uint16_t action_src, + uint16_t action_dst) +{ + struct mlx5_action_construct_data *act_data; + + act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst); + if (!act_data) + return -1; + act_data->indirect.expected_type = mask_type; + LIST_INSERT_HEAD(&acts->act_list, act_data, next); + return 0; +} + static __rte_always_inline int flow_hw_act_data_indirect_list_append(struct mlx5_priv *priv, struct mlx5_hw_actions *acts, @@ -2482,9 +2500,9 @@ __flow_hw_translate_actions_template(struct rte_eth_dev *dev, if (flow_hw_shared_action_translate (dev, actions, acts, src_pos, dr_pos)) goto err; - } else if (__flow_hw_act_data_general_append + } else if (__flow_hw_act_data_indirect_append (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT, - src_pos, dr_pos)){ + masks->type, src_pos, dr_pos)){ goto err; } break; From patchwork Wed Jun 12 16:24:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 141116 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E3EAC44060; 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This patch expands entries for RTE_FLOW_ACTION_TYPE_MODIFY_FIELD actions in this list with a copy of the action from the template. This will be used in follow up commits which add flow rule operation validation. Specifically, to validate that RTE_FLOW_ACTION_TYPE_MODIFY_FIELD action passed by the user is correctly configured. Signed-off-by: Dariusz Sosnowski Acked-by: Ori Kam --- drivers/net/mlx5/mlx5_flow.h | 2 ++ drivers/net/mlx5/mlx5_flow_hw.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 33847e2272..6974d4e075 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1472,6 +1472,8 @@ struct mlx5_action_construct_data { * PRM actions. */ uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS]; + /* Copy of action passed to the action template. */ + struct rte_flow_action_modify_field action; } modify_header; struct { bool symmetric_hash_function; /* Symmetric RSS hash */ diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 21a885517a..19d6105be8 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -1112,6 +1112,7 @@ __flow_hw_act_data_hdr_modify_append(struct mlx5_priv *priv, enum rte_flow_action_type type, uint16_t action_src, uint16_t action_dst, + const struct rte_flow_action_modify_field *mf, uint16_t mhdr_cmds_off, uint16_t mhdr_cmds_end, bool shared, @@ -1124,6 +1125,7 @@ __flow_hw_act_data_hdr_modify_append(struct mlx5_priv *priv, act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst); if (!act_data) return -1; + act_data->modify_header.action = *mf; act_data->modify_header.mhdr_cmds_off = mhdr_cmds_off; act_data->modify_header.mhdr_cmds_end = mhdr_cmds_end; act_data->modify_header.shared = shared; @@ -1601,7 +1603,7 @@ flow_hw_modify_field_compile(struct rte_eth_dev *dev, if (shared) return 0; ret = __flow_hw_act_data_hdr_modify_append(priv, acts, RTE_FLOW_ACTION_TYPE_MODIFY_FIELD, - src_pos, mhdr->pos, + src_pos, mhdr->pos, conf, cmds_start, cmds_end, shared, field, dcopy, mask); if (ret) From patchwork Wed Jun 12 16:24:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 141114 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2D52744060; Wed, 12 Jun 2024 18:25:55 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CDA1C4111C; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230034)(376008)(82310400020)(1800799018)(36860700007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2024 16:25:17.3594 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 07de7a43-8af9-40a3-f163-08dc8afc3f0b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7881 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add mlx5_fp_debug_enabled() function which: - returns true if RTE_LIBRTE_MLX5_DEBUG is defined, - returns false otherwise. This allows for conditional execution of code meant to be executed only when mlx5 debug mode is enabled, without adding conditional compilation guards inside source code. When mlx5 debug mode is disabled, any code running if mlx5_fp_debug_enabled() returns true will be removed by optimizing compiler due to dead code elimination. Signed-off-by: Dariusz Sosnowski Acked-by: Ori Kam --- drivers/common/mlx5/mlx5_common.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h index 14c70edbef..1abd1e8239 100644 --- a/drivers/common/mlx5/mlx5_common.h +++ b/drivers/common/mlx5/mlx5_common.h @@ -109,6 +109,19 @@ pmd_drv_log_basename(const char *s) #endif /* RTE_LIBRTE_MLX5_DEBUG */ +/** + * Returns true if debug mode is enabled for fast path operations. + */ +static inline bool +mlx5_fp_debug_enabled(void) +{ +#ifdef RTE_LIBRTE_MLX5_DEBUG + return true; +#else + return false; +#endif +} + /* Allocate a buffer on the stack and fill it with a printf format string. */ #define MKSTR(name, ...) \ int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ From patchwork Wed Jun 12 16:24:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 141117 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EFE9544060; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230034)(36860700007)(376008)(1800799018)(82310400020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2024 16:25:23.1062 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14879e5e-fb2e-480b-0f83-08dc8afc4293 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044AC.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8285 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds validation to implementations of the following API functions: - rte_flow_async_create() - rte_flow_async_create_by_index() - rte_flow_async_update() - rte_flow_async_destroy() These validations are enabled if and only if RTE_LIBRTE_MLX5_DEBUG macro is defined. Signed-off-by: Dariusz Sosnowski Acked-by: Ori Kam --- doc/guides/rel_notes/release_24_07.rst | 1 + drivers/net/mlx5/mlx5_flow_hw.c | 491 ++++++++++++++++++++++++- 2 files changed, 488 insertions(+), 4 deletions(-) diff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst index 7688ed2764..5f37e2283c 100644 --- a/doc/guides/rel_notes/release_24_07.rst +++ b/doc/guides/rel_notes/release_24_07.rst @@ -86,6 +86,7 @@ New Features * Added match with Tx queue. * Added match with external Tx queue. * Added match with E-Switch manager. + * Added flow item and actions validation to async flow API. Removed Items diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 19d6105be8..1db35c7d16 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -332,6 +332,32 @@ mlx5_flow_ct_init(struct rte_eth_dev *dev, static __rte_always_inline uint32_t flow_hw_tx_tag_regc_mask(struct rte_eth_dev *dev); static __rte_always_inline uint32_t flow_hw_tx_tag_regc_value(struct rte_eth_dev *dev); +static int flow_hw_async_create_validate(struct rte_eth_dev *dev, + const uint32_t queue, + const struct rte_flow_template_table *table, + const struct rte_flow_item items[], + const uint8_t pattern_template_index, + const struct rte_flow_action actions[], + const uint8_t action_template_index, + struct rte_flow_error *error); +static int flow_hw_async_create_by_index_validate(struct rte_eth_dev *dev, + const uint32_t queue, + const struct rte_flow_template_table *table, + const uint32_t rule_index, + const struct rte_flow_action actions[], + const uint8_t action_template_index, + struct rte_flow_error *error); +static int flow_hw_async_update_validate(struct rte_eth_dev *dev, + const uint32_t queue, + const struct rte_flow_hw *flow, + const struct rte_flow_action actions[], + const uint8_t action_template_index, + struct rte_flow_error *error); +static int flow_hw_async_destroy_validate(struct rte_eth_dev *dev, + const uint32_t queue, + const struct rte_flow_hw *flow, + struct rte_flow_error *error); + const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops; /* DR action flags with different table. */ @@ -3856,6 +3882,11 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev, uint32_t res_idx = 0; int ret; + if (mlx5_fp_debug_enabled()) { + if (flow_hw_async_create_validate(dev, queue, table, items, pattern_template_index, + actions, action_template_index, error)) + return NULL; + } flow = mlx5_ipool_malloc(table->flow, &flow_idx); if (!flow) goto error; @@ -3995,10 +4026,10 @@ flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev, uint32_t res_idx = 0; int ret; - if (unlikely(rule_index >= table->cfg.attr.nb_flows)) { - rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, - "Flow rule index exceeds table size"); - return NULL; + if (mlx5_fp_debug_enabled()) { + if (flow_hw_async_create_by_index_validate(dev, queue, table, rule_index, + actions, action_template_index, error)) + return NULL; } flow = mlx5_ipool_malloc(table->flow, &flow_idx); if (!flow) @@ -4131,6 +4162,11 @@ flow_hw_async_flow_update(struct rte_eth_dev *dev, uint32_t res_idx = 0; int ret; + if (mlx5_fp_debug_enabled()) { + if (flow_hw_async_update_validate(dev, queue, of, actions, action_template_index, + error)) + return -rte_errno; + } aux = mlx5_flow_hw_aux(dev->data->port_id, of); nf = &aux->upd_flow; memset(nf, 0, sizeof(struct rte_flow_hw)); @@ -4239,6 +4275,10 @@ flow_hw_async_flow_destroy(struct rte_eth_dev *dev, &fh->table->cfg.attr); int ret; + if (mlx5_fp_debug_enabled()) { + if (flow_hw_async_destroy_validate(dev, queue, fh, error)) + return -rte_errno; + } fh->operation_type = !resizable ? MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY : MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY; @@ -16147,6 +16187,449 @@ mlx5_reformat_action_destroy(struct rte_eth_dev *dev, return 0; } +static bool +flow_hw_is_item_masked(const struct rte_flow_item *item) +{ + const uint8_t *byte; + int size; + int i; + + if (item->mask == NULL) + return false; + + switch ((int)item->type) { + case MLX5_RTE_FLOW_ITEM_TYPE_TAG: + size = sizeof(struct rte_flow_item_tag); + break; + case MLX5_RTE_FLOW_ITEM_TYPE_SQ: + size = sizeof(struct mlx5_rte_flow_item_sq); + break; + default: + size = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_MASK, NULL, 0, item, NULL); + /* + * Pattern template items are passed to this function. + * These items were already validated, so error is not expected. + * Also, if mask is NULL, then spec size is bigger than 0 always. + */ + MLX5_ASSERT(size > 0); + } + + byte = (const uint8_t *)item->mask; + for (i = 0; i < size; ++i) + if (byte[i]) + return true; + + return false; +} + +static int +flow_hw_validate_rule_pattern(struct rte_eth_dev *dev, + const struct rte_flow_template_table *table, + const uint8_t pattern_template_idx, + const struct rte_flow_item items[], + struct rte_flow_error *error) +{ + const struct rte_flow_pattern_template *pt; + const struct rte_flow_item *pt_item; + + if (pattern_template_idx >= table->nb_item_templates) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "Pattern template index out of range"); + + pt = table->its[pattern_template_idx]; + pt_item = pt->items; + + /* If any item was prepended, skip it. */ + if (pt->implicit_port || pt->implicit_tag) + pt_item++; + + for (; pt_item->type != RTE_FLOW_ITEM_TYPE_END; pt_item++, items++) { + if (pt_item->type != items->type) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, + items, "Item type does not match the template"); + + /* + * Assumptions: + * - Currently mlx5dr layer contains info on which fields in masks are supported. + * - This info is not exposed to PMD directly. + * - Because of that, it is assumed that since pattern template is correct, + * then, items' masks in pattern template have nonzero values only in + * supported fields. + * This is known, because a temporary mlx5dr matcher is created during pattern + * template creation to validate the template. + * - As a result, it is safe to look for nonzero bytes in mask to determine if + * item spec is needed in a flow rule. + */ + if (!flow_hw_is_item_masked(pt_item)) + continue; + + if (items->spec == NULL) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + items, "Item spec is required"); + + switch (items->type) { + const struct rte_flow_item_ethdev *ethdev; + const struct rte_flow_item_tx_queue *tx_queue; + struct mlx5_txq_ctrl *txq; + + case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: + ethdev = items->spec; + if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) { + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items, + "Invalid port"); + } + break; + case RTE_FLOW_ITEM_TYPE_TX_QUEUE: + tx_queue = items->spec; + if (mlx5_is_external_txq(dev, tx_queue->tx_queue)) + continue; + txq = mlx5_txq_get(dev, tx_queue->tx_queue); + if (!txq) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items, + "Invalid Tx queue"); + mlx5_txq_release(dev, tx_queue->tx_queue); + default: + break; + } + } + + return 0; +} + +static bool +flow_hw_valid_indirect_action_type(const struct rte_flow_action *user_action, + const enum rte_flow_action_type expected_type) +{ + uint32_t user_indirect_type = MLX5_INDIRECT_ACTION_TYPE_GET(user_action->conf); + uint32_t expected_indirect_type; + + switch ((int)expected_type) { + case RTE_FLOW_ACTION_TYPE_RSS: + case MLX5_RTE_FLOW_ACTION_TYPE_RSS: + expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_RSS; + break; + case RTE_FLOW_ACTION_TYPE_COUNT: + case MLX5_RTE_FLOW_ACTION_TYPE_COUNT: + expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_COUNT; + break; + case RTE_FLOW_ACTION_TYPE_AGE: + expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_AGE; + break; + case RTE_FLOW_ACTION_TYPE_CONNTRACK: + expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_CT; + break; + case RTE_FLOW_ACTION_TYPE_METER_MARK: + case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK: + expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_METER_MARK; + break; + case RTE_FLOW_ACTION_TYPE_QUOTA: + expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_QUOTA; + break; + default: + return false; + } + + return user_indirect_type == expected_indirect_type; +} + +static int +flow_hw_validate_rule_actions(struct rte_eth_dev *dev, + const struct rte_flow_template_table *table, + const uint8_t actions_template_idx, + const struct rte_flow_action actions[], + struct rte_flow_error *error) +{ + const struct rte_flow_actions_template *at; + const struct mlx5_hw_actions *hw_acts; + const struct mlx5_action_construct_data *act_data; + unsigned int idx; + + if (actions_template_idx >= table->nb_action_templates) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "Actions template index out of range"); + + at = table->ats[actions_template_idx].action_template; + hw_acts = &table->ats[actions_template_idx].acts; + + for (idx = 0; actions[idx].type != RTE_FLOW_ACTION_TYPE_END; ++idx) { + const struct rte_flow_action *user_action = &actions[idx]; + const struct rte_flow_action *tmpl_action = &at->orig_actions[idx]; + + if (user_action->type != tmpl_action->type) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, + user_action, + "Action type does not match type specified in " + "actions template"); + } + + /* + * Only go through unmasked actions and check if configuration is provided. + * Configuration of masked actions is ignored. + */ + LIST_FOREACH(act_data, &hw_acts->act_list, next) { + const struct rte_flow_action *user_action; + + user_action = &actions[act_data->action_src]; + + /* Skip actions which do not require conf. */ + switch ((int)user_action->type) { + case RTE_FLOW_ACTION_TYPE_COUNT: + case MLX5_RTE_FLOW_ACTION_TYPE_COUNT: + case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK: + continue; + default: + break; + } + + if (user_action->conf == NULL) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, + user_action, + "Action requires configuration"); + + switch ((int)user_action->type) { + enum rte_flow_action_type expected_type; + const struct rte_flow_action_ethdev *ethdev; + const struct rte_flow_action_modify_field *mf; + + case RTE_FLOW_ACTION_TYPE_INDIRECT: + expected_type = act_data->indirect.expected_type; + if (!flow_hw_valid_indirect_action_type(user_action, expected_type)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION_CONF, + user_action, + "Indirect action type does not match " + "the type specified in the mask"); + break; + case RTE_FLOW_ACTION_TYPE_QUEUE: + if (mlx5_flow_validate_target_queue(dev, user_action, error)) + return -rte_errno; + break; + case RTE_FLOW_ACTION_TYPE_RSS: + if (mlx5_validate_action_rss(dev, user_action, error)) + return -rte_errno; + break; + case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: + /* TODO: Compare other fields if needed. */ + mf = user_action->conf; + if (mf->operation != act_data->modify_header.action.operation || + mf->src.field != act_data->modify_header.action.src.field || + mf->dst.field != act_data->modify_header.action.dst.field || + mf->width != act_data->modify_header.action.width) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION_CONF, + user_action, + "Modify field configuration does not " + "match configuration from actions " + "template"); + break; + case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: + ethdev = user_action->conf; + if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) { + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION_CONF, + user_action, "Invalid port"); + } + break; + default: + break; + } + } + + return 0; +} + +static int +flow_hw_async_op_validate(struct rte_eth_dev *dev, + const uint32_t queue, + const struct rte_flow_template_table *table, + struct rte_flow_error *error) +{ + struct mlx5_priv *priv = dev->data->dev_private; + + MLX5_ASSERT(table != NULL); + + if (table->cfg.external && queue >= priv->hw_attr->nb_queue) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "Incorrect queue"); + + return 0; +} + +/** + * Validate user input for rte_flow_async_create() implementation. + * + * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[in] queue + * The queue to create the flow. + * @param[in] table + * Pointer to template table. + * @param[in] items + * Items with flow spec value. + * @param[in] pattern_template_index + * The item pattern flow follows from the table. + * @param[in] actions + * Action with flow spec value. + * @param[in] action_template_index + * The action pattern flow follows from the table. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 if user input is valid. + * Negative errno otherwise, rte_errno and error struct is populated. + */ +static int +flow_hw_async_create_validate(struct rte_eth_dev *dev, + const uint32_t queue, + const struct rte_flow_template_table *table, + const struct rte_flow_item items[], + const uint8_t pattern_template_index, + const struct rte_flow_action actions[], + const uint8_t action_template_index, + struct rte_flow_error *error) +{ + if (flow_hw_async_op_validate(dev, queue, table, error)) + return -rte_errno; + + if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "Only pattern insertion is allowed on this table"); + + if (flow_hw_validate_rule_pattern(dev, table, pattern_template_index, items, error)) + return -rte_errno; + + if (flow_hw_validate_rule_actions(dev, table, action_template_index, actions, error)) + return -rte_errno; + + return 0; +} + +/** + * Validate user input for rte_flow_async_create_by_index() implementation. + * + * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[in] queue + * The queue to create the flow. + * @param[in] table + * Pointer to template table. + * @param[in] rule_index + * Rule index in the table. + * Inserting a rule to already occupied index results in undefined behavior. + * @param[in] actions + * Action with flow spec value. + * @param[in] action_template_index + * The action pattern flow follows from the table. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 if user input is valid. + * Negative errno otherwise, rte_errno and error struct is set. + */ +static int +flow_hw_async_create_by_index_validate(struct rte_eth_dev *dev, + const uint32_t queue, + const struct rte_flow_template_table *table, + const uint32_t rule_index, + const struct rte_flow_action actions[], + const uint8_t action_template_index, + struct rte_flow_error *error) +{ + if (flow_hw_async_op_validate(dev, queue, table, error)) + return -rte_errno; + + if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_INDEX) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "Only index insertion is allowed on this table"); + + if (rule_index >= table->cfg.attr.nb_flows) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "Flow rule index exceeds table size"); + + if (flow_hw_validate_rule_actions(dev, table, action_template_index, actions, error)) + return -rte_errno; + + return 0; +} + + +/** + * Validate user input for rte_flow_async_update() implementation. + * + * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[in] queue + * The queue to create the flow. + * @param[in] flow + * Flow rule to be updated. + * @param[in] actions + * Action with flow spec value. + * @param[in] action_template_index + * The action pattern flow follows from the table. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 if user input is valid. + * Negative errno otherwise, rte_errno and error struct is set. + */ +static int +flow_hw_async_update_validate(struct rte_eth_dev *dev, + const uint32_t queue, + const struct rte_flow_hw *flow, + const struct rte_flow_action actions[], + const uint8_t action_template_index, + struct rte_flow_error *error) +{ + if (flow_hw_async_op_validate(dev, queue, flow->table, error)) + return -rte_errno; + + if (flow_hw_validate_rule_actions(dev, flow->table, action_template_index, actions, error)) + return -rte_errno; + + return 0; +} + +/** + * Validate user input for rte_flow_async_destroy() implementation. + * + * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[in] queue + * The queue to create the flow. + * @param[in] flow + * Flow rule to be destroyed. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 if user input is valid. + * Negative errno otherwise, rte_errno and error struct is set. + */ +static int +flow_hw_async_destroy_validate(struct rte_eth_dev *dev, + const uint32_t queue, + const struct rte_flow_hw *flow, + struct rte_flow_error *error) +{ + if (flow_hw_async_op_validate(dev, queue, flow->table, error)) + return -rte_errno; + + return 0; +} + static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops = { .async_create = flow_hw_async_flow_create, .async_create_by_index = flow_hw_async_flow_create_by_index,